800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs AD9513 FEATURES 1.6 GHz differential clock input 3 programmable dividers Divide-by in range from1 to 32 Phase select for coarse delay adjust Three 800 MHz/250 MHz LVDS/CMOS clock outputs Additive output jitter 300 fs rms Time delays up to 11.6 ns Device configured with 4-level logic pins Space-saving, 32-lead LFCSP FUNCTIONAL BLOCK DIAGRAM RSET VS GND AD9513 LVDS/CMOS OUT0 /1. . . /32 OUT0B LVDS/CMOS CLK OUT1 /1. . . /32 CLKB OUT1B LVDS/CMOS SYNCB APPLICATIONS OUT2B SETUP LOGIC VREF S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 05595-001 Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure ATE OUT2 ∆t /1. . . /32 Figure 1. GENERAL DESCRIPTION The AD9513 features a three-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are three independent clock outputs that can be set to either LVDS or CMOS levels. These outputs operate to 800 MHz in LVDS mode and to 250 MHz in CMOS mode. Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to the other clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment. One of the outputs features a delay element with three selectable full-scale delay values (1.8 ns, 6.0 ns, and 11.6 ns), each with 16 steps of fine adjustment. The AD9513 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ⅓ VS. The VREF pin provides a level of ⅔ VS. VS (3.3 V) and GND (0 V) provide the other two logic levels. The AD9513 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9513 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is −40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD9513 TABLE OF CONTENTS Features .............................................................................................. 1 Power-On SYNC .................................................................... 17 Applications....................................................................................... 1 SYNCB..................................................................................... 17 Functional Block Diagram .............................................................. 1 RSET Resistor ............................................................................. 18 General Description ......................................................................... 1 VREF............................................................................................ 18 Specifications..................................................................................... 3 Setup Configuration................................................................... 18 Clock Input.................................................................................... 3 Divider Phase Offset .................................................................. 20 Clock Outputs ............................................................................... 3 Delay Block ................................................................................. 21 Timing Characteristics ................................................................ 4 Outputs ........................................................................................ 21 Clock Output Phase Noise .......................................................... 6 Power Supply............................................................................... 22 Clock Output Additive Time Jitter............................................. 8 Exposed Metal Paddle ........................................................... 22 SYNCB, VREF, and Setup Pins ................................................... 9 Power Management ................................................................... 22 Power.............................................................................................. 9 Applications..................................................................................... 23 Timing Diagrams............................................................................ 10 Using the AD9513 Outputs for ADC Clock Applications.... 23 Absolute Maximum Ratings.......................................................... 11 LVDS Clock Distribution .......................................................... 23 Thermal Characteristics ............................................................ 11 CMOS Clock Distribution ........................................................ 23 ESD Caution................................................................................ 11 Setup Pins (S0 to S10)................................................................ 24 Pin Configuration and Function Descriptions........................... 12 Power and Grounding Considerations and Power Supply Rejection...................................................................................... 24 Terminology .................................................................................... 13 Typical Performance Characteristics ........................................... 14 Functional Description .................................................................. 17 Overall.......................................................................................... 17 Phase Noise and Jitter Measurement Setups........................... 25 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 26 CLK, CLKB—Differential Clock Input ................................... 17 Synchronization.......................................................................... 17 REVISION HISTORY 9/05—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD9513 SPECIFICATIONS Typical (typ) is given for VS = 3.3 V ± 5%; TA = 25°C, RSET = 4.12 kΩ, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation. CLOCK INPUT Table 1. Parameter CLOCK INPUT (CLK) Input Frequency Input Sensitivity 1 Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance Min Typ 0 1.5 1.3 4.0 150 1.6 150 4.8 2 Max Unit 1.6 GHz mV p-p V V mV p-p kΩ pF 1.7 1.8 5.6 Test Conditions/Comments Self-biased; enables ac coupling With 200 mV p-p signal applied; dc-coupled CLK ac-coupled; CLKB ac-bypassed to RF ground Self-biased 1 A slew rate of 1 V/ns is required to meet jitter, phase noise, and propagation delay specifications. CLOCK OUTPUTS Table 2. Parameter LVDS CLOCK OUTPUT Differential Output Frequency Differential Output Voltage (VOD) Delta VOD Output Offset Voltage (VOS) Delta VOS Short-Circuit Current (ISA, ISB) CMOS CLOCK OUTPUT Single-Ended Output Frequency Output Voltage High (VOH) Output Voltage Low (VOL) Min Typ 0 250 350 1.125 1.23 14 0 VS − 0.1 Max Unit 800 450 30 1.375 25 24 MHz mV mV V mV mA 250 MHz V V 0.1 Rev. 0 | Page 3 of 28 Test Conditions/Comments Termination = 100 Ω differential Output shorted to GND Single-ended measurements; termination open Complementary output on (OUT1B) With 5 pF load @ 1 mA load @ 1 mA load AD9513 TIMING CHARACTERISTICS CLK input slew rate = 1 V/ns or greater. Table 3. Parameter LVDS Output Rise Time, tRL Output Fall Time, tFL PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT OUT0, OUT1, OUT2 Divide = 1 Divide = 2 − 32 Variation with Temperature OUT2 Divide = 1 Divide = 2 − 32 Variation with Temperature OUTPUT SKEW, LVDS OUTPUTS OUT0 to OUT1 on Same Part, tSKV 1 OUT0 to OUT2 on Same Part, tSKV1 All LVDS OUTs Across Multiple Parts, tSKV_AB 2 Same LVDS OUTs Across Multiple Parts, tSKV_AB2 CMOS Output Rise Time, tRC Output Fall Time, tFC PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT OUT0, OUT1 Divide = 1 Divide = 2 − 32 Variation with Temperature OUT2 Divide = 1 Divide = 2 − 32 Variation with Temperature OUTPUT SKEW, CMOS OUTPUTS All CMOS OUTs on Same Part, tSKC1 All CMOS OUTs Across Multiple Parts, tSKC_AB2 Same CMOS OUTs Across Multiple Parts, tSKC_AB2 LVDS-TO-CMOS OUT Output Skew, tSKV_C DELAY ADJUST (OUT2; LVDS AND CMOS) S0 = 1/3 Zero-Scale Delay Time 3 Zero-Scale Variation with Temperature Full-Scale Time Delay3 Full-Scale Variation with Temperature S0 = 2/3 Zero-Scale Delay Time3 Zero-Scale Variation with Temperature Full-Scale Time Delay3 Full-Scale Variation with Temperature Min Typ Max Unit 200 210 350 350 ps ps 1.03 1.09 1.29 1.35 0.9 1.62 1.68 ns ns ps/°C 1.07 1.13 1.35 1.41 0.9 1.69 1.75 ns ns ps/°C −135 −205 −20 −65 +125 +90 375 300 ps ps ps ps 650 650 865 990 ps ps 1.14 1.19 1.46 1.51 1 1.89 1.94 ns ns ps/°C 1.20 1.24 1.53 1.57 1 1.97 2.01 ns ns ps/°C +135 415 330 ps ps ps 510 ps Test Conditions/Comments Termination = 100 Ω differential 20% to 80%, measured differentially 80% to 20%, measured differentially Delay off on OUT2 Delay off on OUT2 B outputs are inverted; termination = open 20% to 80%; CLOAD = 3 pF 80% to 20%; CLOAD = 3 pF Delay off on OUT2 Delay off on OUT2 −230 0.35 0.20 1.8 −0.38 ns ps/°C ns ps/°C 0.48 0.31 6.0 −1.3 ns ps/°C ns ps/°C Rev. 0 | Page 4 of 28 Everything the same; different logic type LVDS to CMOS on same part AD9513 Parameter S0 = 1 Zero-Scale Delay Time3 Zero-Scale Variation with Temperature Full-Scale Time Delay3 Full-Scale Variation with Temperature Linearity, DNL Linearity, INL 1 2 3 Min Typ Max 0.59 0.47 11.6 −5 0.2 0.2 Unit Test Conditions/Comments ns ps/°C ns ps/°C LSB LSB This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature. This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature. Incremental delay; does not include propagation delay. Rev. 0 | Page 5 of 28 AD9513 CLOCK OUTPUT PHASE NOISE Table 4. Parameter CLK-TO-LVDS ADDITIVE PHASE NOISE CLK = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK = 491.52 MHz, OUT = 122.88 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset Min Typ Max Unit −100 −110 −118 −129 −135 −140 −148 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −112 −122 −132 −142 −148 −152 −155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −108 −118 −128 −138 −145 −148 −154 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −118 −129 −136 −147 −153 −156 −158 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −108 −118 −128 −138 −145 −148 −155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. 0 | Page 6 of 28 Test Conditions/Comments AD9513 Parameter CLK = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK-TO-CMOS ADDITIVE PHASE NOISE CLK = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK = 78.6432 MHz, OUT = 78.6432 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK = 78.6432 MHz, OUT = 39.3216 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset Min Typ Max Unit −118 −127 −137 −147 −154 −156 −158 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −110 −121 −130 −140 −145 −149 −156 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −125 −132 −143 −152 −158 −160 −162 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −122 −132 −140 −150 −155 −158 −160 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −128 −136 −146 −155 −161 −162 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. 0 | Page 7 of 28 Test Conditions/Comments AD9513 CLOCK OUTPUT ADDITIVE TIME JITTER Table 5. Parameter LVDS OUTPUT ADDITIVE TIME JITTER CLK= 400 MHz LVDS (OUT0) = 100 MHz Divide Ratio = 4 LVDS (OUT1, OUT2) = 100 MHz CLK = 400 MHz LVDS (OUT0) = 100 MHz Divide Ratio = 4 LVDS (OUT1, OUT2) = 50 MHz CLK = 400 MHz LVDS (OUT1) = 100 MHz Divide Ratio = 4 LVDS (OUT0, OUT2) = 100 MHz CLK = 400 MHz LVDS (OUT1) = 100 MHz Divide Ratio = 4 LVDS (OUT0, OUT2) = 50 MHz CLK = 400 MHz LVDS (OUT2) = 100 MHz Divide Ratio = 4 LVDS (OUT0, OUT1) = 100 MHz CLK = 400 MHz LVDS (OUT2) = 100 MHz Divide Ratio = 4 LVDS (OUT0, OUT1) = 50 MHz CLK = 400 MHz LVDS (OUT2) = 100 MHz Divide Ratio = 4 CMOS (OUT0, OUT1) = 50 MHz CMOS OUTPUT ADDITIVE TIME JITTER CLK = 400 MHz CMOS (OUT0) = 100 MHz Divide Ratio = 4 LVDS (OUT2) = 100 MHz CLK = 400 MHz CMOS (OUT0) = 100 MHz Divide Ratio = 4 CMOS (OUT1, OUT2) = 50 MHz CLK = 400 MHz CMOS (OUT1) = 100 MHz Divide Ratio = 4 CMOS (OUT0, OUT2) = 50 MHz CLK = 400 MHz CMOS (OUT2) = 100 MHz Divide Ratio = 4 CMOS (OUT0, OUT1) = 50 MHz CLK = 400 MHz CMOS (OUT2) = 100 MHz Divide Ratio = 4 LVDS (OUT0, OUT1) = 50 MHz Min Typ Max Unit 300 fs rms 300 fs rms 305 fs rms 310 fs rms 310 fs rms 315 fs rms 345 fs rms Test Conditions/Comments Calculated from SNR of ADC method Interferer Interferer Interferer Interferer Interferer Interferer Interferer Calculated from SNR of ADC method 300 fs rms 300 fs rms Interferer Interferer 335 fs rms 355 fs rms 340 fs rms Interferer Interferer Interferer Rev. 0 | Page 8 of 28 AD9513 Parameter DELAY BLOCK ADDITIVE TIME JITTER 1 Delay FS = 1.8 ns Fine Adj. 00000 Delay FS = 1.8 ns Fine Adj. 11111 Delay FS = 6.0 ns Fine Adj. 00000 Delay FS = 6.0 ns Fine Adj. 11111 Delay FS = 11.6 ns Fine Adj. 00000 Delay FS = 11.6 ns Fine Adj. 11111 1 Min Typ Max Unit 0.71 1.2 1.3 2.7 2.0 2.8 Test Conditions/Comments 100 MHz output; incremental additive jitter1 ps rms ps rms ps rms ps rms ps rms ps rms This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter should be added to this value using the root sum of the squares (RSS) method. SYNCB, VREF, AND SETUP PINS Table 6. Parameter SYNCB Logic High Logic Low Capacitance VREF Output Voltage S0 TO S10 Levels 0 1/3 2/3 1 Min Typ Max Unit 0.40 V V pF 0.76·VS V 0.1·VS 0.45·VS 0.8·VS V V V V 2.7 2 0.62·VS 0.2·VS 0.55·VS 0.9·VS Test Conditions/Comments Minimum − maximum from 0 mA to 1 mA load POWER Table 7. Parameter POWER-ON SYNCHRONIZATION 1 VS Transit Time from 2.2 V to 3.1 V POWER DISSIPATION POWER DELTA Divider (Divide = 2 to Divide = 1) LVDS Output CMOS Output (Static) CMOS Output (@ 62.5 MHz) CMOS Output (@ 125 MHz) Delay Block 1 Min Typ Max 35 Unit ms Test Conditions/Comments See the Power-On SYNC section. 175 325 575 mW 240 320 460 605 615 840 mW mW All three outputs on. LVDS (divide = 2). No clock. Does not include power dissipated in external resistors. All three outputs on. CMOS (divide = 2); 62.5 MHz out (5 pF load). All three outputs on. CMOS (divide = 2); 125 MHz out (5 pF load). 15 20 30 65 70 30 30 50 40 110 145 45 45 85 50 155 220 65 mW mW mW mW mW mW For each divider. No clock. No clock. No clock. Single-ended. At 62.5 MHz out with 5 pF load. Single-ended. At 125 MHz out with 5 pF load. Off to 1.8 ns fs, delay word = 60; output clocking at 62.5 MHz. This is the rise time of the VS supply that is required to ensure that a synchronization of the outputs occurs on power-up. The critical factor is the time it takes the VS to transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs are not synchronized. Rev. 0 | Page 9 of 28 AD9513 TIMING DIAGRAMS tCLK CLK SINGLE-ENDED 80% CMOS 3pF LOAD tLVDS tCMOS Figure 2. CLK/CLKB to Clock Output Timing, DIV = 1 Mode 80% LVDS 05595-065 20% tFL tFC Figure 4. CMOS Timing, Single-Ended, 3 pF Load DIFFERENTIAL tRL tRC Figure 3. LVDS Timing, Differential Rev. 0 | Page 10 of 28 05595-066 05595-002 20% AD9513 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter or Pin VS RSET CLK CLK OUT0, OUT1, OUT2 FUNCTION STATUS Junction Temperature 1 Storage Temperature Lead Temperature (10 sec) With Respect to GND GND GND CLKB GND GND GND Min −0.3 −0.3 −0.3 −1.2 −0.3 −0.3 −0.3 −65 Max +3.6 VS + 0.3 VS + 0.3 +1.2 VS + 0.3 VS + 0.3 VS + 0.3 150 +150 300 Unit V V V V V V V °C °C °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. THERMAL CHARACTERISTICS 2 Thermal Resistance 32-Lead LFCSP 3 θJA = 36.6°C/W 1 See Thermal Characteristics for θJA. Thermal impedance measurements were taken on a 4-layer board in still air in accordance with EIA/JESD51-7. 3 The external pad of this package must be soldered to adequate copper land on board. 2 ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 11 of 28 AD9513 25 S0 27 OUT0B 26 VS 29 VS 28 OUT0 30 VS 32 RSET 31 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VS 1 THE EXPOSED PADDLE IS AN ELECTRICAL AND THERMAL CONNECTION 24 VS CLK 2 23 OUT1 CLKB 3 VS 4 1 21 VS TOP VIEW (Not to Scale) SYNCB 5 32 25 24 22 OUT1B AD9513 20 VS VREF 6 EXPOSED PAD (BOTTOM VIEW) GND 19 OUT2 S10 7 18 OUT2B S9 8 9 8 05595-006 17 16 05595-005 S1 16 S3 14 S2 15 S5 12 S4 13 S6 11 S8 9 S7 10 17 VS Figure 6. Exposed Paddle Figure 5. 32-Lead LFCSP Pin Configuration Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be soldered to a PCB land that functions as both a heat dissipation path as well as an electrical ground. Table 9. Pin Function Descriptions Pin No. 1, 4 ,17 ,20, 21, 24, 26, 29, 30 2 3 5 6 7 to16, 25 Mnemonic VS Description Power Supply (3.3 V). CLK CLKB SYNCB VREF S10 to S1, S0 18 19 22 23 27 28 31 32 OUT2B OUT2 OUT1B OUT1 OUT0B OUT0 GND RSET Clock Input. Complementary Clock Input. Used to Synchronize Outputs. Provides 2/3 VS for use as one of the four logic levels on S0 to S10. Setup Select Pins. These are 4-state logic. The logic levels are VS, GND, 1/3 VS, and 2/3 VS. The VREF pin provides 2/3 VS. Each pin is internally biased to 1/3 VS so that a pin requiring that logic level should be left NC (no connection). Complementary LVDS/Inverted CMOS Output. LVDS/CMOS Output. Complementary LVDS/Inverted CMOS Output. OUT6 includes a delay block. LVDS/CMOS Output. OUT6 includes a delay block. Complementary LVDS/Inverted CMOS Output. OUT5 includes a delay block. LVDS/CMOS Output. OUT5 includes a delay block. Ground. The exposed paddle on the back of the chip is also GND. Current Set Resistor to Ground. Nominal value = 4.12 kΩ. Rev. 0 | Page 12 of 28 AD9513 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 degrees for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although there are many causes that can contribute to phase jitter, one major component is due to random noise that is characterized statistically as being Gaussian (normal) in distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. It is also meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings is seen to vary. For a square wave, the time jitter is seen as a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Since these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the SNR and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. Additive Phase Noise It is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device as the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contribute their own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. Additive Time Jitter It is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device will affect the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contribute their own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev. 0 | Page 13 of 28 AD9513 TYPICAL PERFORMANCE CHARACTERISTICS 0.4 0.7 3 LVDS (DIV ON) 0.6 3 CMOS (DIV ON) 0.5 POWER (W) POWER (W) 0.3 3 LVDS (DIV = 1) 0.4 3 CMOS (DIV OFF) 0.3 0.2 200 400 600 800 STOP 5GHz 05595-051 0 20 40 60 80 Figure 9. Power vs. Frequency—CMOS Figure 7. Power vs. Frequency—LVDS START 300kHz 0.1 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) 05595-097 0.1 05595-050 0.2 Figure 8. CLK Smith Chart (Evaluation Board) Rev. 0 | Page 14 of 28 100 120 AD9513 HORIZ 500ps/DIV 700 650 600 550 500 100 300 500 700 05595-013 VERT 100mV/DIV 05595-010 DIFFERENTIAL SWING (mV p-p) 750 900 OUTPUT FREQUENCY (MHz) Figure 10. LVDS Differential Output @ 800 MHz Figure 12. LVDS Differential Output Swing vs. Frequency 3.5 2pF 3.0 OUTPUT (VPK) 2.5 10pF 2.0 1.5 1.0 HORIZ 1ns/DIV Figure 11. CMOS Single-Ended Output @ 250 MHz with 10 pF Load 05595-011 VERT 500mV/DIV 0 0 100 200 300 400 500 600 OUTPUT FREQUENCY (MHz) Figure 13. CMOS Single-Ended Output Swing vs. Frequency and Load Rev. 0 | Page 15 of 28 05595-014 20pF 0.5 –80 –90 –90 –100 –100 –110 –110 –120 –130 –120 –130 –140 –140 –150 –150 –160 –160 –170 10 100 1k 10k 100k 1M –170 10 10M 05595-049 L(f) (dBc/Hz) –80 05595-048 L(f) (dBc/Hz) AD9513 100 1k OFFSET (Hz) –100 –110 –110 –120 –120 –130 –140 –140 –150 –160 –160 10k 10M –130 –150 1k 1M 100k 1M 10M –170 10 OFFSET (Hz) 05595-046 L(f) (dBc/Hz) –100 100 100k Figure 16. Additive Phase Noise—LVDS DIV2, 122.88 MHz 05595-045 L(f) (dBc/Hz) Figure 14. Additive Phase Noise—LVDS DIV 1, 245.76 MHz –170 10 10k OFFSET (Hz) 100 1k 10k 100k 1M OFFSET (Hz) Figure 15. Additive Phase Noise—CMOS DIV 1, 245.76 MHz Figure 17. Additive Phase Noise—CMOS DIV4, 61.44 MHz Rev. 0 | Page 16 of 28 10M AD9513 3.3V FUNCTIONAL DESCRIPTION 3.1V 2.2V OVERALL 35ms MAX VS 0V CLK CLOCK FREQUENCY IS EXAMPLE ONLY OUT DIVIDE = 2 PHASE = 0 OUT2 includes an analog delay block that can be set to add an additional delay of 1.8 ns, 6.0 ns, or 11.6 ns full scale, each with 16 levels of fine adjustment. < 65ms 05595-094 The AD9513 provides for the distribution of its input clock on up to three outputs. Each output can be set to either LVDS or CMOS logic levels. Each output has its own divider that can be set for a divide ratio selected from a list of integer values from 1 (bypassed) to 32. INTERNAL SYNC NODE Figure 19. Power-On Sync Timing CLK, CLKB—DIFFERENTIAL CLOCK INPUT SYNCB The CLK and CLKB pins are differential clock input pins. This input works up to 1600 MHz. The jitter performance is degraded by a slew rate below 1 V/ns. The input level should be between approximately 150 mV p-p to no more than 2 V p-p. Anything greater can result in turning on the protection diodes on the input pins. If the setup configuration of the AD9513 is changed during operation, the outputs can become unsynchronized. The outputs can be resynchronized to each other at any time. Synchronization occurs when the SYNCB pin is pulled low and released. The clock outputs (except where divide = 1) are forced into a fixed state (determined by the divide and phase settings) and held there in a static condition, until the SYNCB pin is returned to high. Upon release of the SYNCB pin, after four cycles of the clock signal at CLK, all outputs continue clocking in synchronicity (except where divide = 1). See Figure 18 for the CLK equivalent input circuit. This input is fully differential and self-biased. The signal should be accoupled using capacitors. If a single-ended input must be used, this can be accommodated by ac coupling to one side of the differential input only. The other side of the input should be bypassed to a quiet ac ground by a capacitor. 3 CLK CYCLES CLOCK INPUT STAGE 4 CLK CYCLES CLK OUT CLK EXAMPLE: DIVIDE ≥ 8 PHASE = 0 EXAMPLE DIVIDE RATIO PHASE = 0 SYNCB 05595-093 VS When divide = 1 for an output, that output is not affected by SYNCB. Figure 20. SYNCB Timing with Clock Present CLKB 4 CLK CYCLES 2.5kΩ CLK OUT DEPENDS ON PREVIOUS STATE 05595-021 5kΩ SYNCB MIN 5ns Figure 18. Clock Input Equivalent Circuit § § § EXAMPLE DIVIDE RATIO PHASE = 0 § DEPENDS ON PREVIOUS STATE AND DIVIDE RATIO Figure 21. SYNCB Timing with No Clock Present SYNCHRONIZATION Power-On SYNC A power-on sync (POS) is issued when the VS power supply is turned on to ensure that the outputs start in synchronization. The power-on sync works only if the VS power supply transitions the region from 2.2 V to 3.1 V within 35 ms. The POS can occur up to 65 ms after VS crosses 2.2 V. Only outputs which are not divide = 1 are synchronized. The outputs of the AD9513 can be synchronized by using the SYNCB pin. Synchronization aligns the phases of the clock outputs, respecting any phase offset that has been set on an output’s divider. SYNCB Figure 22. SYNCB Equivalent Input Circuit Rev. 0 | Page 17 of 28 05595-092 5kΩ 05595-022 2.5kΩ AD9513 Synchronization is initiated by pulling the SYNCB pin low for a minimum of 5 ns. The input clock does not have to be present at the time the command is issued. The synchronization occurs after four input clock cycles. The synchronization applies to clock outputs • that are not turned OFF • where the divider is not divide = 1 (divider bypassed) The AD9513 operation is determined by the combination of logic levels present at the setup pins. The setup configurations for the AD9513 are shown in Table 11 to Table 16. The four logic levels are referred to as 0, ⅓, ⅔, and 1. These numbers represent the fraction of the VS voltage that defines the logic levels. See the setup pin thresholds in Table 6. The meaning of some of the pin settings is changed by the settings of other pins. For example, S0 determines whether S3, and S4 sets OUT2 delay (S0 ≠ 0) or OUT2 phase (S0 = 0). An output with its divider set to divide = 1 (divider bypassed) is always synchronized with the input clock, with a propagation delay. The SYNCB pin must be pulled up for normal operation. Do not let the SYNCB pin float. RSET RESISTOR The internal bias currents of the AD9513 are set by the RSET resistor. This resistor should be as close as possible to the value given as a condition in the Specifications section (RSET = 4.12 kΩ). This is a standard 1% resistor value and should be readily obtainable. The bias currents set by this resistor determine the logic levels and operating conditions of the internal blocks of the AD9513. The performance figures given in the Specifications section assume that this resistor value is used for RSET. VREF The VREF pin provides a voltage level of ⅔ VS. This voltage is one of the four logic levels used by the setup pins (S0 to S10). These pins set the operation of the AD9513. The VREF pin provides sufficient drive capability to drive as many of the setup pins as necessary, up to all on a single part. The VREF pin should be used for no other purpose. SETUP CONFIGURATION The specific operation of the AD9513 is set by the logic levels applied to the setup pins (S10 to S0). These pins use four-state logic. The logic levels used are VS and GND, plus ⅓ VS and ⅔ VS. The ⅓ VS level is provided by the internal self-biasing on each of the setup pins (S10 to S0). This is the level seen by a setup pin that is left not connected (NC). The ⅔ VS level is provided by the VREF pin. All setup pins requiring the ⅔VS level must be tied to the VREF pin. S2 indicates which outputs are in use, as shown in Table 10. This allows the same pins (S5 and S6, S7 and S8) to determine the settings for two different outputs, depending on which outputs are in use. Table 10. S2 Indicates Which Outputs Are in Use S2 0 1/3 2/3 1 The fine delay values set by S3 and S4 (when the delay is being used, S0 ≠ 0) are fractions of the full-scale delay. Note that the longest setting is 15/16 of full scale. The full-scale delay times are given in Table 3. To determine the actual delay, take the fraction corresponding to the fine delay setting and multiply by the full-scale value set by Table 3 corresponding to the S0 value and add the LVDS or CMOS propagation delay time (see Table 3). The full-scale delay times shown in Table 11, and referred to elsewhere, are nominal time values. The value at S2 also determines whether S5 and S6 set OUT2 divide (S2 ≠ 0) or OUT1 phase (S2 = 0). In addition, S2 determines whether S7 and S8 set OUT1 divide (S2 ≠ 1) or OUT2 phase (S2 = 1 and S0 ≠ 0). In addition, the value of S2 determines whether S9 and S10 set OUT0 divide (S2 ≠ 2/3) or OUT2 divide (S2 = 2/3). VS 60kΩ 05595-023 SETUP PIN S0 TO S10 30kΩ Outputs OUT2 Off All Outputs On OUT0 Off OUT1 Off Figure 23. Setup Pin (S0 to S10) Equivalent Circuit Rev. 0 | Page 18 of 28 AD9513 Table 11. Output Delay Full Scale S0 0 1/3 2/3 1 Table 14. OUT2 Divide or OUT1 Phase Delay Bypass 1.8 ns 6.0 ns 11.6 ns Table 12. Output Logic Configuration S1 0 1/3 2/3 1 0 1/3 2/3 1 0 1/3 2/3 1 0 1/3 2/3 1 S2 0 0 0 0 1/3 1/3 1/3 1/3 2/3 2/3 2/3 2/3 1 1 1 1 OUT0 OFF CMOS LVDS LVDS CMOS LVDS LVDS CMOS OFF OFF OFF OFF LVDS CMOS LVDS CMOS OUT1 LVDS CMOS LVDS CMOS CMOS LVDS LVDS CMOS OFF OFF OFF CMOS OFF OFF OFF OFF OUT2 OFF OFF OFF OFF CMOS LVDS CMOS LVDS OFF LVDS CMOS OFF CMOS LVDS LVDS CMOS Table 13. OUT2 Delay or Phase S3 0 1/3 2/3 1 0 1/3 2/3 1 0 1/3 2/3 1 0 1/3 2/3 1 S4 0 0 0 0 1/3 1/3 1/3 1/3 2/3 2/3 2/3 2/3 1 1 1 1 OUT2 Delay (S0 ≠ 0) 0 1/16 1/8 3/16 1/4 5/16 3/8 7/16 1/2 9/16 5/8 11/16 3/4 13/16 7/8 15/16 OUT2 Phase (S0 = 0) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S5 S6 OUT2 Divide (Duty Cycle1) (S2 ≠ 0) OUT1 Phase (S2 = 0) 0 1/3 2/3 1 0 1/3 2/3 1 0 1/3 2/3 1 0 1/3 2/3 1 0 0 0 0 1/3 1/3 1/3 1/3 2/3 2/3 2/3 2/3 1 1 1 1 1 2 (50%) 3 (33%) 4 (50%) 5 (40%) 6 (50%) 8 (50%) 9 (44%) 10 (50%) 12 (50%) 15 (47%) 16 (50%) 18 (50%) 24 (50%) 30 (50%) 32 (50%) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 Duty cycle is the clock signal high time divided by the total period. Table 15. OUT1 Divide or OUT2 Phase S7 S8 OUT1 Divide (Duty Cycle1) (S2 ≠ 1) OUT2 Phase (S2 = 1 and S0 ≠ 0) 0 1/3 2/3 1 0 1/3 2/3 1 0 1/3 2/3 1 0 1/3 2/3 1 0 0 0 0 1/3 1/3 1/3 1/3 2/3 2/3 2/3 2/3 1 1 1 1 1 2 (50%) 3 (33%) 4 (50%) 5 (40%) 6 (50%) 8 (50%) 9 (44%) 10 (50%) 12 (50%) 15 (47%) 16 (50%) 18 (50%) 24 (50%) 30 (50%) 32 (50%) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 Duty cycle is the clock signal high time divided by the total period. Rev. 0 | Page 19 of 28 AD9513 Table 16. OUT0 Divide or OUT2 Divide S9 0 1/3 2/3 1 0 1/3 2/3 1 0 1/3 2/3 1 0 1/3 2/3 1 1 For example: OUT0 Divide (Duty Cycle1) S2 ≠ 2/3 1 2 (50%) 3 (33%) 4 (50%) 5 (40%) 6 (50%) 8 (50%) 9 (44%) 10 (50%) 12 (50%) 15 (47%) 16 (50%) 18 (50%) 24 (50%) 30 (50%) 32 (50%) S10 0 0 0 0 1/3 1/3 1/3 1/3 2/3 2/3 2/3 2/3 1 1 1 1 OUT2 Divide (Duty Cycle1) S2 = 2/3 7 (43%) 11 (45%) 13 (46%) 14 (50%) 17 (47%) 19 (47%) 20 (50%) 21 (48%) 22 (50%) 23 (48%) 25 (48%) 26 (50%) 27 (48%) 28 (50%) 29 (48%) 31 (48%) CLK = 491.52 MHz tCLK = 1/491.52 = 2.0345 ns For Divide = 4: Phase Offset 0 = 0 ns Phase Offset 1 = 2.0345 ns Phase Offset 2 = 4.069 ns Phase Offset 3 = 6.104 ns The outputs can also be described as: Phase Offset 0 = 0° Phase Offset 1 = 90° Phase Offset 2 = 180° Phase Offset 3 = 270° Duty cycle is the clock signal high time divided by the total period. DIVIDER PHASE OFFSET The phase offset of OUT1 and OUT2 can be selected (see Table 13 to Table 15). This allows the relative phase of the outputs to be set. After a SYNC operation (see the Synchronization section), the phase offset word of each divider determines the number of input clock (CLK) cycles to wait before initiating a clock output edge. By giving each divider a different phase offset, output-tooutput delays can be set in increments of the fast clock period, tCLK. Setting the phase offset to Phase = 4 results in the same relative phase as Phase = 0° or 360°. The resolution of the phase offset is set by the fast clock period (tCLK) at CLK. The maximum unique phase offset is less than the divide ratio, up to a phase offset of 15. Phase offsets can be related to degrees by calculating the phase step for a particular divide ratio: Phase Step = 360°/Divide Ratio Figure 24 shows four cases, each with the divider set to divide = 4. By incrementing the phase offset from 0 to 3, the output is offset from the initial edge by a multiple of tCLK. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Divide = 4 15 Phase Step = 360°/4 = 90° CLOCK INPUT CLK DIVIDER OUTPUT DIV = 4 Using some of the same examples: tCLK Unique Phase Offsets in Degrees Are Phase = 0°, 90°, 180°, 270° PHASE = 0 Divide = 9 PHASE = 1 Phase Step = 360°/9 = 40° PHASE = 2 Unique Phase Offsets in Degrees Are Phase = 0°, 40°, 80°, 120°, 160°, 200°, 240°, 280°, 320° PHASE = 3 tCLK 05595-024 2 × tCLK 3 × tCLK Figure 24. Phase Offset—Divider Set for Divide = 4, Phase Set from 0 to 2 Rev. 0 | Page 20 of 28 AD9513 DELAY BLOCK OUTPUTS OUT2 includes an analog delay element that gives variable time delays (ΔT) in the clock signal passing through that output. Each of the three AD9513 outputs can be selected either as LVDS differential outputs or as pairs of CMOS single-ended outputs. If selected as CMOS, the OUT is a noninverted, singleended output, and OUTB is an inverted, single-ended output. CLOCK INPUT OUT1 ONLY 3.5mA MUX ÷N ØSELECT LVDS CMOS ∆T OUTPUT DRIVER OUT 05595-025 FINE DELAY ADJUST (16 STEPS) FULL SCALE : 1.5ns, 5ns, 10ns OUTB The AD9513 allows for the selection of three full-scale delays, 1.8 ns, 6.0 ns, and 11.6 ns, set by delay full-scale (see Table 11). Each of these full-scale delays can be scaled by 16 fine adjustment values, which are set by the delay word (see Table 13). The delay block adds some jitter to the output. This means that the delay function should be used primarily for clocking digital chips, such as FPGA, ASIC, DUC, and DDC, rather than for supplying a sample clock for data converters. The jitter is higher for longer full scales because the delay block uses a ramp and trip points to create the variable delay. A longer ramp means more noise has a chance of being introduced. When the delay block is OFF (bypassed), it is also powered down. Rev. 0 | Page 21 of 28 3.5mA Figure 26. LVDS Output Simplified Equivalent Circuit VS OUT1/ OUT1B 05595-028 The amount of delay that can be used is determined by the output frequency. The amount of delay is limited to less than one-half cycle of the clock period. For example, for a 10 MHz clock, the delay can extend to the full 11.6 ns maximum. However, for a 100 MHz clock, the maximum delay is less than 5 ns (or half of the period). 05595-027 Figure 25. Analog Delay Block Figure 27. CMOS Equivalent Output Circuit AD9513 POWER MANAGEMENT POWER SUPPLY The AD9513 requires a 3.3 V ± 5% power supply for VS. The tables in the Specifications section give the performance expected from the AD9513 with the power supply voltage within this range. In no case should the absolute maximum range of −0.3 V to +3.6 V, with respect to GND, be exceeded on Pin VS. Good engineering practice should be followed in the layout of power supply traces and the ground plane of the PCB. The power supply should be bypassed on the PCB with adequate capacitance (>10 μF). The AD9513 should be bypassed with adequate capacitors (0.1 μF) at all power pins as close as possible to the part. The layout of the AD9513 evaluation board (AD9513/PCB) is a good example. In some cases, the AD9513 can be configured to use less power by turning off functions that are not being used. The power-saving options include the following: • A divider is powered down when set to divide = 1 (bypassed). • Adjustable delay block on OUT2 is powered down when in off mode (S0 = 0). • An unneeded output can be powered down (see Table 12). This also powers down the divider for that output. Exposed Metal Paddle The exposed metal paddle on the AD9513 package is an electrical connection, as well as a thermal enhancement. For the device to function properly, the paddle must be properly attached to ground (GND). The exposed paddle of the AD9513 package must be soldered down. The AD9513 must dissipate heat through its exposed paddle. The PCB acts as a heat sink for the AD9513. The PCB attachment must provide a good thermal path to a larger heat dissipation area, such as a ground plane on the PCB. This requires a grid of vias from the top layer down to the ground plane (see Figure 28).The AD9513 evaluation board (AD9513/PCB)provides a good example of how the part should be attached to the PCB. 05595-035 VIAS TO GND PLANE Figure 28. PCB Land for Attaching Exposed Paddle Rev. 0 | Page 22 of 28 AD9513 APPLICATIONS USING THE AD9513 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed, analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought of as a sampling mixer; any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. Clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at ≥14-bit resolution being the most stringent. The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock. Considering an ideal ADC of infinite resolution where the step size and quantization error can be ignored, the available SNR can be expressed approximately by ADC (differential or single-ended, logic level, termination) should be considered when selecting the best clocking/ converter solution. LVDS CLOCK DISTRIBUTION The AD9513 provides three clock outputs that are selectable as either CMOS or LVDS levels. LVDS uses a current mode output stage. The current is 3.5 mA, which yields 350 mV output swing across a 100 Ω resistor. The LVDS outputs meet or exceed all ANSI/TIA/EIA-644 specifications. A recommended termination circuit for the LVDS outputs is shown in Figure 30. VS ⎡ 1 ⎤ SNR = 20 × log ⎢ ⎥ ⎢⎣ 2πft j ⎥⎦ 100Ω 100Ω DIFFERENTIAL (COUPLED) LVDS 05595-032 LVDS VS where f is the highest analog frequency being digitized. Figure 30. LVDS Output Termination tj is the rms jitter on the sampling clock. Figure 29 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (ENOB). 1 SNR = 20log 2πf T A J 100 18 The AD9513 provides three outputs that are selectable as either CMOS or LVDS levels. When selected as CMOS, an output provides for driving devices requiring CMOS level logic at their clock inputs. 16 TJ = 100 fS 200 70 400 f 14 fS S 12 1ps 60 2ps 10 10p s 8 50 40 Whenever single-ended CMOS clocking is used, some of the following general guidelines should be used. ENOB SNR (dB) 90 80 100 05595-091 6 30 10 CMOS CLOCK DISTRIBUTION 1k fA FULL-SCALE SINE WAVE ANALOG FREQUENCY (MHz) Figure 29. ENOB and SNR vs. Analog Input Frequency See Application Note AN-756 and Application Note AN-501 at www.analog.com. Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB. (Distributing a single-ended clock on a noisy PCB can result in coupled noise on the sample clock. Differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment.) The AD9513 features LVDS outputs that provide differential clock outputs, which enable clock solutions that maximize converter SNR performance. The input requirements of the Point-to-point nets should be designed such that a driver has one receiver only on the net, if possible. This allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the net. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. The value of the resistor is dependent on the board design and timing requirements (typically 10 Ω to 100 Ω is used). CMOS outputs are also limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 3 inches are recommended to preserve signal rise/fall times and preserve signal integrity. Rev. 0 | Page 23 of 28 CMOS 10Ω 60.4Ω 1.0 INCH MICROSTRIP 5pF GND 05595-033 110 See Application Note AN-586 at www.analog.com for more information on LVDS. Figure 31. Series Termination of CMOS Output AD9513 Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9513 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in Figure 32. The far-end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets. 50Ω OUT1/OUT1B SELECTED AS CMOS The setup pins that require a logic level of ⅔ VS should be tied together, along with the VREF pin, and bypassed to ground via a capacitor. Many applications seek high speed and performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the PCB is as important as the circuit design. Proper RF techniques must be used for device selection, placement, and routing, as well as power supply bypassing and grounding to ensure optimum performance. 100Ω 100Ω 3pF 05595-034 10Ω The setup pins that require a logic level of ⅓ VS (internal selfbias) should be tied together and bypassed to ground via a capacitor. POWER AND GROUNDING CONSIDERATIONS AND POWER SUPPLY REJECTION VS CMOS SETUP PINS (S0 TO S10) Figure 32. CMOS Output with Far-End Termination Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9513 offers LVDS outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters. Rev. 0 | Page 24 of 28 AD9513 PHASE NOISE AND JITTER MEASUREMENT SETUPS WENZEL OSCILLATOR EVALUATION BOARD ZFL1000VH2 SPLITTER ZESC-2-11 OUT1 TERM AMP OUT1B TERM +28dB CLK ATTENUATOR –12dB SIG IN ATTENUATOR –7dB REF IN 0° EVALUATION BOARD ZFL1000VH2 OUT1 TERM AMP OUT1B TERM +28dB CLK VARIABLE DELAY COLBY PDL30A 0.01ns STEP TO 10ns 05595-041 BALUN AD9513 Figure 33. Additive Phase Noise Measurement Configuration WENZEL OSCILLATOR ANALOG SOURCE EVALUATION BOARD PC AD9513 BALUN WENZEL OSCILLATOR OUT1 TERM OUT1B TERM CLK SNR ADC CLK FFT tJ_RMS 05595-042 DATA CAPTURE CARD FIFO Figure 34. Jitter Determination by Measuring SNR of ADC 2 t J_RMS = ⎡V ⎤ ⎢ A_RMS ⎥ − SND × BW 2 − θ QUANTIZATION 2 + θ THERMAL 2 + θ DNL 2 ⎢ SNR ⎥ ⎣ 10 20 ⎦ 2 2π × f A × V A_PK ( ) ( [ where: tj_RMS is the rms time jitter. SNR is the signal-to-noise ratio. SND is the source noise density in nV/√Hz. BW is the SND filter bandwidth. VA is the analog source voltage. fA is the analog frequency. The θ terms are the quantization, thermal, and DNL errors. Rev. 0 | Page 25 of 28 ] AGILENT E5500B PHASE NOISE MEASUREMENT SYSTEM BALUN AD9513 ) AD9513 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX 25 24 PIN 1 INDICATOR TOP VIEW 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 32 1 3.25 3.10 SQ 2.95 EXPOSED PAD (BOTTOM VIEW) 17 16 9 8 0.25 MIN 3.50 REF 0.80 MAX 0.65 TYP 12° MAX 1.00 0.85 0.80 PIN 1 INDICATOR 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 35. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model AD9513BCPZ 1 AD9513BCPZ-REEL71 AD9513/PCB 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ Evaluation Board Z = Pb-free part. Rev. 0 | Page 26 of 28 Package Option CP-32-2 CP-32-2 AD9513 NOTES Rev. 0 | Page 27 of 28 AD9513 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05595–0–9/05(0) Rev. 0 | Page 28 of 28