AD AD9515BCPZ

1.6 GHz Clock Distribution IC, Dividers,
Delay Adjust, Two Outputs
AD9515
FEATURES
FUNCTIONAL BLOCK DIAGRAM
1.6 GHz differential clock input
2 programmable dividers
Divide-by in range from1 to 32
Phase select for coarse delay adjust
1.6 GHz LVPECL clock output
Additive output jitter 225 fs rms
800 MHz/250 MHz LVDS/CMOS clock output
Additive output jitter 300 fs rms/290 fs rms
Time delays up to 10 ns
Device configured with 4-level logic pins
Space-saving, 32-lead LFCSP
RSET
VS
GND
AD9515
LVPECL
OUT0
/1. . . /32
OUT0B
CLK
CLKB
LVDS/CMOS
OUT1
Δt
/1. . . /32
OUT1B
SYNCB
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
ATE
VREF
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
05597-001
SETUP LOGIC
Figure 1.
GENERAL DESCRIPTION
The AD9515 features a two-output clock distribution IC in a
design that emphasizes low jitter and phase noise to maximize
data converter performance. Other applications with
demanding phase noise and jitter requirements also benefit
from this part.
There are two independent clock outputs. One output is
LVPECL, while the other output can be set to either LVDS or
CMOS levels. The LVPECL output operates to 1.6 GHz. The
other output operates to 800 MHz in LVDS mode and to
250 MHz in CMOS mode.
Each output has a programmable divider that can be set to
divide by a selected set of integers ranging from 1 to 32. The
phase of one clock output relative to the other clock output can
be set by means of a divider phase select function that serves as
a coarse timing adjustment.
The LVDS/CMOS output features a delay element with three
selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each
with 16 steps of fine adjustment.
The AD9515 does not require an external controller for
operation or setup. The device is programmed by means of
11 pins (S0 to S10) using 4-level logic. The programming pins
are internally biased to ⅓ VS. The VREF pin provides a level of
⅔ VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.
The AD9515 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9515 is available in a 32-lead LFCSP and operates from
a single 3.3 V supply. The temperature range is −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD9515
TABLE OF CONTENTS
Features .............................................................................................. 1
Synchronization.......................................................................... 18
Applications....................................................................................... 1
RSET Resistor ................................................................................ 19
Functional Block Diagram .............................................................. 1
VREF............................................................................................ 19
General Description ......................................................................... 1
Setup Configuration................................................................... 19
Revision History ............................................................................... 2
Programming .................................................................................. 20
Specifications..................................................................................... 3
Divider Phase Offset .................................................................. 22
Clock Input.................................................................................... 3
Delay Block ................................................................................. 22
Clock Outputs ............................................................................... 3
Outputs ........................................................................................ 23
Timing Characteristics ................................................................ 4
Power Supply............................................................................... 23
Clock Output Phase Noise .......................................................... 5
Power Management ................................................................... 24
Clock Output Additive Time Jitter............................................. 8
Applications..................................................................................... 25
SYNCB, VREF, and Setup Pins ................................................... 9
Using the AD9515 Outputs for ADC Clock Applications.... 25
Power............................................................................................ 10
LVPECL Clock Distribution ..................................................... 25
Timing Diagrams............................................................................ 11
LVDS Clock Distribution .......................................................... 26
Absolute Maximum Ratings.......................................................... 12
CMOS Clock Distribution ........................................................ 26
Thermal Characteristics ............................................................ 12
Setup Pins (S0 to S10)................................................................ 26
ESD Caution................................................................................ 12
Power and Grounding Considerations and Power Supply
Rejection...................................................................................... 26
Pin Configuration and Function Descriptions........................... 13
Terminology .................................................................................... 14
Typical Performance Characteristics ........................................... 15
Functional Description .................................................................. 18
Phase Noise and Jitter Measurement Setups........................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
Overall.......................................................................................... 18
CLK, CLKB—Differential Clock Input ................................... 18
REVISION HISTORY
7/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD9515
SPECIFICATIONS
Typical (typ) is given for VS = 3.3 V ± 5%, TA = 25°C, RSET = 4.12 kΩ, LVPECL swing = 790 mV, unless otherwise noted. Minimum (min)
and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation.
CLOCK INPUT
Table 1.
Parameter
CLOCK INPUT (CLK)
Input Frequency 1
Input Sensitivity1
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Min
Typ
0
1.5
1.3
4.0
150
1.6
150
4.8
2
Max
Unit
1.6
GHz
mV p-p
V
V
mV p-p
kΩ
pF
1.7
1.8
5.6
Test Conditions/Comments
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLKB ac-bypassed to RF ground
Self-biased
1
A slew rate of 1 V/ns is required to meet jitter, phase noise, and propagation delay specifications.
CLOCK OUTPUTS
Table 2.
Parameter
LVPECL CLOCK OUTPUT
(OUT0) Differential
Output Frequency
Output High Voltage (VOH)
Output Low Voltage (VOL)
Output Differential Voltage (VOD)
LVDS CLOCK OUTPUT
(OUT1) Differential
Output Frequency
Differential Output Voltage (VOD)
Delta VOD
Output Offset Voltage (VOS)
Delta VOS
Short-Circuit Current (ISA, ISB)
CMOS CLOCK OUTPUT
(OUT1) Single-Ended
Output Frequency
Output Voltage High (VOH)
Output Voltage Low (VOL)
Min
Typ
Max
Unit
0
VS − 1.1
VS − 1.90
640
VS − 0.96
VS − 1.76
790
1.6
VS − 0.82
VS − 1.52
960
GHz
V
V
mV
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
Termination = 100 Ω differential
0
250
350
1.125
1.23
14
0
VS − 0.1
800
450
30
1.375
25
24
MHz
mV
mV
V
mV
mA
250
MHz
V
V
0.1
Rev. 0 | Page 3 of 28
Output shorted to GND
Single-ended measurements; termination open
Complementary output on (OUT1B)
With 5 pF load
@ 1 mA load
@ 1 mA load
AD9515
TIMING CHARACTERISTICS
CLK input slew rate = 1 V/ns or greater.
Table 3.
Parameter
LVPECL
Output Rise Time, tRP
Output Fall Time, tFP
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUT
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, LVPECL OUTPUT
LVPECL OUT Across Multiple Parts, tSKP_AB3 1
LVDS
Output Rise Time, tRL
Output Fall Time, tFL
PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT
OUT3 to OUT4
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, LVDS OUTPUT
LVDS OUT Across Multiple Parts, tSKV_AB1
CMOS
Output Rise Time, tRC
Output Fall Time, tFC
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, CMOS OUTPUT
CMOS OUT Across Multiple Parts, tSKC_AB1
LVPECL-TO-LVDS OUT
Output Delay, tSKP_V
LVPECL-TO-CMOS OUT
Output Delay, tSKP_C
DELAY ADJUST (OUT2; LVDS AND CMOS)
S0 = 1/3
Zero Scale Delay Time 2
Zero Scale Variation with Temperature
Full Scale Time Delay2
Full Scale Variation with Temperature
S0 = 2/3
Zero Scale Delay Time2
Zero Scale Variation with Temperature
Full Scale Time Delay2
Full Scale Variation with Temperature
Min
355
395
1.00
1.05
Typ
Max
Unit
60
60
100
100
ps
ps
480
530
0.5
635
710
ps
ps
ps/°C
125
ps
200
210
350
350
ps
ps
1.25
1.30
0.9
1.55
1.60
ns
ns
ps/°C
230
ps
650
650
865
990
ps
ps
1.45
1.50
1
1.75
1.80
ns
ns
ps/°C
300
ps
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
20% to 80%, measured differentially
80% to 20%, measured differentially
Termination = 100 Ω differential
20% to 80%, measured differentially
80% to 20%, measured differentially
Delay off on OUT4
Delay off on OUT4
1.10
1.15
B outputs are inverted; termination = open
20% to 80%; CLOAD = 3 pF
80% to 20%; CLOAD = 3 pF
Delay off on OUT4
Delay off on OUT4
700
970
1150
ps
0.88
1.14
1.43
ns
0.34
0.20
1.7
−0.38
ns
ps/°C
ns
ps/°C
0.45
0.31
5.9
−1.3
ns
ps/°C
ns
ps/°C
Rev. 0 | Page 4 of 28
Everything the same; different logic type
LVPECL to LVDS on same part
Everything the same; different logic type
LVPECL to CMOS on same part
AD9515
Parameter
S0 = 1
Zero Scale Delay Time2
Zero Scale Variation with Temperature
Full Scale Time Delay2
Full Scale Variation with Temperature
Linearity, DNL
Linearity, INL
1
2
Min
Typ
Max
0.56
0.47
11.4
−5
0.2
0.2
Unit
Test Conditions/Comments
ns
ps/°C
ns
ps/°C
LSB
LSB
This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.
Incremental delay; does not include propagation delay.
CLOCK OUTPUT PHASE NOISE
CLK input slew rate = 1 V/ns or greater.
Table 4.
Parameter
CLK-TO-LVPECL ADDITIVE PHASE NOISE
CLK = 622.08 MHz, OUT = 622.08 MHz
Divide = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK = 622.08 MHz, OUT = 155.52 MHz
Divide = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK = 622.08 MHz, OUT = 38.88 MHz
Divide = 16
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK = 491.52 MHz, OUT = 61.44 MHz
Divide = 8
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
> 1 MHz Offset
Min
Typ
Max
Unit
−125
−132
−140
−148
−153
−154
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−128
−140
−148
−155
−161
−161
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−135
−145
−158
−165
−165
−166
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−131
−142
−153
−160
−165
−165
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. 0 | Page 5 of 28
Test Conditions/Comments
AD9515
Parameter
CLK = 491.52 MHz, OUT = 245.76 MHz
Divide = 2
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK = 245.76 MHz, OUT = 61.44 MHz
Divide = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK-TO-LVDS ADDITIVE PHASE NOISE
CLK = 622.08 MHz, OUT= 622.08 MHz
Divide = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK = 622.08 MHz, OUT = 155.52 MHz
Divide = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK = 491.52 MHz, OUT = 245.76 MHz
Divide = 2
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
Min
Typ
Max
Unit
−125
−132
−140
−151
−157
−158
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−138
−144
−154
−163
−164
−165
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−100
−110
−118
−129
−135
−140
−148
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−112
−122
−132
−142
−148
−152
−155
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−108
−118
−128
−138
−145
−148
−154
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. 0 | Page 6 of 28
Test Conditions/Comments
AD9515
Parameter
CLK = 491.52 MHz, OUT = 122.88 MHz
Divide = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK = 245.76 MHz, OUT = 245.76 MHz
Divide = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK = 245.76 MHz, OUT = 122.88 MHz
Divide = 2
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK-TO-CMOS ADDITIVE PHASE NOISE
CLK = 245.76 MHz, OUT = 245.76 MHz
Divide = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK = 245.76 MHz, OUT = 61.44 MHz
Divide = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
Min
Typ
Max
Unit
−118
−129
−136
−147
−153
−156
−158
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−108
−118
−128
−138
−145
−148
−155
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−118
−127
−137
−147
−154
−156
−158
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−110
−121
−130
−140
−145
−149
−156
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−125
−132
−143
−152
−158
−160
−162
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. 0 | Page 7 of 28
Test Conditions/Comments
AD9515
Parameter
CLK = 78.6432 MHz, OUT = 78.6432 MHz
Divide = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK = 78.6432 MHz, OUT = 39.3216 MHz
Divide = 2
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
Min
Typ
Max
Unit
−122
−132
−140
−150
−155
−158
−160
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−128
−136
−146
−155
−161
−162
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Test Conditions/Comments
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 5.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK = 622.08 MHz
LVPECL (OUT0) = 622.08 MHz
Divide = 1
CLK = 622.08 MHz
LVPECL (OUT0) = 155.52 MHz
Divide = 4
CLK = 400 MHz
LVPECL (OUT0) = 100 MHz
Divide = 4
CLK = 400 MHz
LVPECL (OUT0) = 100 MHz
Divide = 4
LVDS (OUT1) = 100 MHz
CLK = 400 MHz
LVPECL (OUT0) = 100 MHz
Divide = 4
LVDS (OUT1) = 50 MHz
CLK = 400 MHz
LVPECL (OUT0) = 100 MHz
Divide = 4
CMOS (OUT1) = 50 MHz
LVDS OUTPUT ADDITIVE TIME JITTER
CLK = 400 MHz
LVDS (OUT1) = 100 MHz
Divide = 4
CLK = 400 MHz
LVDS (OUT1) = 100 MHz
Divide = 4
LVPECL (OUT0)= 50 MHz
Min
Typ
Max
Unit
Test Conditions/Comments
40
fs rms
BW = 12 kHz − 20 MHz (OC-12)
OUT1 off
55
fs rms
BW = 12 kHz − 20 MHz (OC-3)
OUT1 off
215
fs rms
Calculated from SNR of ADC method
OUT1 off
215
fs rms
Calculated from SNR of ADC method
225
fs rms
Interferer
Calculated from SNR of ADC method
230
fs rms
Interferer
Calculated from SNR of ADC method
300
fs rms
350
fs rms
Interferer
Delay off
Calculated from SNR of ADC method
OUT0 off
Calculated from SNR of ADC method
OUT0 off
Interferer
Rev. 0 | Page 8 of 28
AD9515
Parameter
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 400 MHz
CMOS (OUT1) = 100 MHz
Divide = 4
Min
CLK = 400 MHz
CMOS (OUT1) = 100 MHz
Divide = 4
LVPECL (OUT0) = 50 MHz
DELAY BLOCK ADDITIVE TIME JITTER 1
Delay FS = 1.5 ns Fine Adj. 00000
Delay FS = 1.5 ns Fine Adj. 11111
Delay FS = 5 ns Fine Adj. 00000
Delay FS = 5 ns Fine Adj. 11111
Delay FS = 10 ns Fine Adj. 00000
Delay FS = 10 ns Fine Adj. 11111
1
Typ
Max
Unit
290
fs rms
Test Conditions/Comments
Delay off
Calculated from SNR of ADC method
315
fs rms
Calculated from SNR of ADC method
Interferer
100 MHz output; incremental additive jitter
0.71
1.2
1.3
2.7
2.0
2.8
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
SYNCB, VREF, AND SETUP PINS
Table 6.
Parameter
SYNCB
Logic High
Logic Low
Capacitance
VREF
Output Voltage
S0 TO S10
Levels
0
1/3
2/3
1
Min
Typ
Max
Unit
0.40
V
V
pF
0.76 VS
V
0.1 VS
0.45 VS
0.8 VS
V
V
V
V
2.7
2
0.62 VS
0.2 VS
0.55 VS
0.9 VS
Test Conditions/Comments
Minimum − maximum from 0 mA to 1 mA load
Rev. 0 | Page 9 of 28
AD9515
POWER
Table 7.
Parameter
POWER-ON SYNCHRONIZATION 1
VS Transit Time from 2.2 V to 3.1 V
POWER DISSIPATION
POWER DELTA
Divider (Divide = 2 to Divide = 1)
LVPECL Output
LVDS Output
CMOS Output (Static)
CMOS Output (@ 62.5 MHz)
CMOS Output (@ 125 MHz)
Delay Block
1
Min
Typ
Max
35
Unit
ms
Test Conditions/Comments
See the Power-On SYNC section.
215
285
380
mW
300
370
465
mW
330
405
510
mW
Both outputs on. LVPECL (divide = 2), LVDS (divide = 2). No clock.
Does not include power dissipated in external resistors.
Both outputs on. LVPECL (divide = 2), CMOS (divide = 2);
at 62.5 MHz out (5 pF load).
Both outputs on. LVPECL, CMOS (divide = 2);
at 125 MHz out (5 pF load).
15
65
20
30
80
110
30
30
90
50
40
110
150
45
45
125
85
50
140
190
65
mW
mW
mW
mW
mW
mW
mW
For each divider. No clock.
For each output. No clock.
No clock.
No clock.
Single-ended. At 62.5 MHz out with 5 pF load.
Single-ended. At 125 MHz out with 5 pF load.
Off to 1.5 ns fs, delay word = 60; output clocking at 62.5 MHz.
This is the rise time of the VS supply that is required to ensure that a synchronization of the outputs occurs on power-up. The critical factor is the time it takes the VS to
transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs will not be synchronized.
Rev. 0 | Page 10 of 28
AD9515
TIMING DIAGRAMS
tCLK
CLK
DIFFERENTIAL
80%
tPECL
LVDS
05597-002
tCMOS
tRL
tFL
05597-065
20%
tLVDS
Figure 4. LVDS Timing, Differential
Figure 2. CLK/CLKB to Clock Output Timing, Divide = 1 Mode
SINGLE-ENDED
DIFFERENTIAL
80%
80%
CMOS
3pF LOAD
LVPECL
tFP
05597-064
tRP
tRC
tFC
Figure 5. CMOS Timing, Single-Ended, 3 pF Load
Figure 3. LVPECL Timing, Differential
Rev. 0 | Page 11 of 28
05597-066
20%
20%
AD9515
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter or Pin
VS
RSET
CLK, CLKB
CLK
OUT0, OUT0B, OUT1, OUT1B
Junction Temperature 1
Storage Temperature
Lead Temperature (10 sec)
With
Respect
to
GND
GND
GND
CLKB
GND
Min
−0.3
−0.3
−0.3
−1.2
−0.3
−65
Max
+3.6
VS + 0.3
VS + 0.3
+1.2
VS + 0.3
150
+150
300
Unit
V
V
V
V
V
°C
°C
°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS 2
Thermal Resistance
32-Lead LFCSP 3
θJA = 36.6°C/W
1
See Thermal Characteristics for θJA.
Thermal impedance measurements were taken on a 4-layer board in still air
in accordance with EIA/JESD51-7.
3
The external pad of this package must be soldered to adequate copper land
on board.
2
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 12 of 28
AD9515
25 S0
26 VS
28 DNC
27 DNC
30 VS
29 VS
31 GND
32 RSET
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VS 1
THE EXPOSED PADDLE
IS AN ELECTRICAL AND
THERMAL CONNECTION
24 VS
CLK 2
23 OUT0
CLKB 3
VS 4
1
21 VS
TOP VIEW
(Not to Scale)
SYNCB 5
32
25
24
22 OUT0B
AD9515
20 VS
VREF 6
EXPOSED PAD
(BOTTOM VIEW)
GND
19 OUT1
S10 7
18 OUT1B
S9 8
9
8
05597-006
17
16
05597-005
S2 15
S1 16
S4 13
S3 14
S5 12
S6 11
S8 9
S7 10
17 VS
Figure 7. Exposed Paddle
Figure 6. 32-Lead LFCSP Pin Configuration
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to
function properly, the paddle must be soldered to a PCB land that functions as both a heat dissipation path as well as an electrical
ground (analog).
Table 9. Pin Function Descriptions
Pin No.
1, 4, 17, 20, 21, 24, 26, 29, 30
2
3
5
6
7 to 16, 25
18
19
22
23
27, 28
31, Exposed Paddle
32
Mnemonic
VS
CLK
CLKB
SYNCB
VREF
S0 to S10
OUT1B
OUT1
OUT0B
OUT0
DNC
GND
RSET
Description
Power Supply (3.3 V).
Clock Input.
Complementary Clock Input. Used in conjunction with CLK.
Used to Synchronize the Outputs; Active Low Signal.
Provides 2/3 VS Reference Voltage for Use with Programming Pins S0 to S10.
Programming Pins. These pins determine the operation of the AD9515; 4-state logic.
Complementary LVDS/Inverted CMOS Output. Includes a delay block.
LVDS/CMOS Output. Includes a delay block.
Complementary LVPECL Output.
LVPECL Output.
Do Not Connect.
Ground. The exposed paddle on the back of the chip is also GND.
Current Sets Resistor to Ground. Nominal value = 4.12 kΩ.
Rev. 0 | Page 13 of 28
AD9515
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0 to 360 degrees
for each cycle. Actual signals, however, display a certain amount
of variation from ideal phase progression over time. This
phenomenon is called phase jitter. Although there are many
causes that can contribute to phase jitter, one major component
is due to random noise that is characterized statistically as being
Gaussian (normal) in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as a
series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in dB) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
It is also meaningful to integrate the total power contained
within some interval of offset frequencies (for example, 10 kHz
to 10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency
interval.
Phase noise has a detrimental effect on the performance of
ADCs, DACs, and RF mixers. It lowers the achievable dynamic
range of the converters and mixers, although they are affected
in somewhat different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When
observing a sine wave, the time of successive zero crossings is
seen to vary. For a square wave, the time jitter is seen as a
displacement of the edges from their ideal (regular) times of
occurrence. In both cases, the variations in timing from the
ideal are the time jitter. Since these variations are random in
nature, the time jitter is specified in units of seconds root mean
square (rms) or 1 sigma of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the SNR and dynamic range of the converter. A
sampling clock with the lowest possible jitter provides the
highest performance from a given converter.
Additive Phase Noise
It is the amount of phase noise that is attributable to the device
or subsystem being measured. The phase noise of any external
oscillators or clock sources has been subtracted. This makes it
possible to predict the degree to which the device affects the
total system phase noise when used in conjunction with the
various oscillators and clock sources, each of which contribute
their own phase noise to the total. In many cases, the phase
noise of one element dominates the system phase noise.
Additive Time Jitter
It is the amount of time jitter that is attributable to the device or
subsystem being measured. The time jitter of any external
oscillators or clock sources has been subtracted. This makes it
possible to predict the degree to which the device will affect the
total system time jitter when used in conjunction with the
various oscillators and clock sources, each of which contribute
their own time jitter to the total. In many cases, the time jitter of
the external oscillators and clock sources dominates the system
time jitter.
Rev. 0 | Page 14 of 28
AD9515
TYPICAL PERFORMANCE CHARACTERISTICS
0.3
0.5
LVPECL (DIV ON) + CMOS (DIV ON)
POWER (W)
LVPECL (DIV ON)
0.2
LVPECL (DIV = 1)
0.3
LVDS (DIV ON)
400
800
1200
OUTPUT FREQUENCY (MHz)
1600
Figure 8. Power vs. Frequency—LVPECL, LVDS
START 300kHz
STOP 5GHz
0.2
0
20
40
60
80
OUTPUT FREQUENCY (MHz)
100
Figure 10. Power vs. Frequency—LVPECL, CMOS
Figure 9. CLK Smith Chart (Evaluation Board)
Rev. 0 | Page 15 of 28
120
05597-008
0.1
05597-009
LVPECL (DIV OFF) + CMOS (DIV OFF)
05597-097
POWER (W)
0.4
AD9515
1.8
DIFFERENTIAL SWING (V p-p)
1.7
1.6
1.5
1.4
HORIZ 200ps/DIV
1.2
100
600
1100
05597-012
VERT 500mV/DIV
05597-095
1.3
1600
OUTPUT FREQUENCY (MHz)
Figure 14. LVPECL Differential Output Swing vs. Frequency
Figure 11. LVPECL Differential Output @ 1600 MHz
DIFFERENTIAL SWING (mV p-p)
750
600
550
500
100
300
500
700
OUTPUT FREQUENCY (MHz)
05597-013
HORIZ 500ps/DIV
650
05597-010
VERT 100mV/DIV
700
900
Figure 15. LVDS Differential Output Swing vs. Frequency
Figure 12. LVDS Differential Output @ 800 MHz
3.5
2pF
3.0
2.5
OUTPUT (VPK)
10pF
2.0
1.5
1.0
20pF
HORIZ 1ns/DIV
Figure 13. CMOS Single-Ended Output @ 250 MHz with 10 pF Load
0
0
100
200
300
400
OUTPUT FREQUENCY (MHz)
500
600
Figure 16. CMOS Single-Ended Output Swing vs. Frequency and Load
Rev. 0 | Page 16 of 28
05597-014
VERT 500mV/DIV
05597-011
0.5
–110
–120
–120
–130
–130
–140
–140
–150
–150
–160
–160
1k
10k
100k
1M
10M
OFFSET (Hz)
–170
10
–90
–100
–100
–110
–110
L(f) (dBc/Hz)
–90
–120
–130
–150
–150
–160
–160
100k
1M
10M
OFFSET (Hz)
–170
10
–110
–120
–120
L(f) (dBc/Hz)
–110
–130
–140
–160
–160
100k
1M
10k
100k
1M
10M
–140
–150
10k
1k
–130
–150
10M
OFFSET (Hz)
05597-045
L(f) (dBc/Hz)
–100
1k
100
Figure 21. Additive Phase Noise—LVDS, Divide = 2, 122.88 MHz
–100
100
10M
OFFSET (Hz)
Figure 18. Additive Phase Noise—LVDS, Divide = 1, 245.76 MHz
–170
10
1M
–130
–140
10k
100k
–120
–140
05597-048
L(f) (dBc/Hz)
–80
1k
10k
Figure 20. Additive Phase Noise—LVPECL, Divide = 1, 622.08 MHz
–80
100
1k
OFFSET (Hz)
Figure 17. Additive Phase Noise—LVPECL, Divide = 1, 245.76 MHz
–170
10
100
05597-049
100
–170
10
100
1k
10k
100k
1M
OFFSET (Hz)
Figure 22. Additive Phase Noise—CMOS, Divide = 4, 61.44 MHz
Figure 19. Additive Phase Noise—CMOS, Divide = 1, 245.76 MHz
Rev. 0 | Page 17 of 28
10M
05597-046
–170
10
05597-052
L(f) (dBc/Hz)
–110
05597-051
L(f) (dBc/Hz)
AD9515
AD9515
FUNCTIONAL DESCRIPTION
3.3V
OVERALL
3.1V
OUT1 includes an analog delay block that can be set to add an
additional delay of 1.5 ns, 5 ns, or 10 ns full scale, each with
16 levels of fine adjustment.
2.2V
35ms
MAX
VS
0V
CLK
CLOCK FREQUENCY
IS EXAMPLE ONLY
OUT
DIVIDE = 2
PHASE = 0
< 65ms
05597-094
The AD9515 provides for the distribution of its input clock on
one or both of its outputs. OUT0 is an LVPECL output. OUT1
can be set to either LVDS or CMOS logic levels. Each output
has its own divider that can be set for a divide ratio selected
from a list of integer values from 1 (bypassed) to 32.
INTERNAL SYNC NODE
CLK, CLKB—DIFFERENTIAL CLOCK INPUT
Figure 24. Power-On Sync Timing
The CLK and CLKB pins are differential clock input pins.
This input works up to 1600 MHz. The jitter performance is
degraded by a slew rate below 1 V/ns. The input level should be
between approximately 150 mV p-p to no more than 2 V p-p.
Anything greater can result in turning on the protection diodes
on the input pins.
See Figure 23 for the CLK equivalent input circuit. This
input is fully differential and self-biased. The signal should be
ac-coupled using capacitors. If a single-ended input must be
used, this can be accommodated by ac coupling to one side of
the differential input only. The other side of the input should be
bypassed to a quiet ac ground by a capacitor.
If the setup configuration of the AD9515 is changed during
operation, the outputs can become unsynchronized. The
outputs can be re-synchronized to each other at any time.
Synchronization occurs when the SYNCB pin is pulled low and
released. The clock outputs (except where divide = 1) are forced
into a fixed state (determined by the divide and phase settings)
and held there in a static condition, until the SYNCB pin is
returned to high. Upon release of the SYNCB pin, after four
cycles of the clock signal at CLK, all outputs continue clocking
in synchronicity (except where divide = 1).
When divide = 1 for an output, that output is not affected by
SYNCB.
CLOCK INPUT
STAGE
VS
SYNCB
3 CLK CYCLES
4 CLK CYCLES
OUT
EXAMPLE: DIVIDE ≥ 8
PHASE = 0
EXAMPLE DIVIDE
RATIO PHASE = 0
SYNCB
CLKB
2.5kΩ
Figure 25. SYNCB Timing with Clock Present
5kΩ
05597-021
5kΩ
4 CLK CYCLES
CLK
OUT DEPENDS ON PREVIOUS STATE
§
§
§
EXAMPLE DIVIDE
RATIO PHASE = 0
Figure 23. Clock Input Equivalent Circuit
SYNCB
MIN 5ns
SYNCHRONIZATION
§ DEPENDS ON PREVIOUS STATE AND DIVIDE RATIO
Figure 26. SYNCB Timing with No Clock Present
Power-On SYNC
A power-on sync (POS) is issued when the VS power supply is
turned on to ensure that the outputs start in synchronization.
The power-on sync works only if the VS power supply transitions the region from 2.2 V to 3.1 V within 35 ms. The POS can
occur up to 65 ms after VS crosses 2.2 V. Only outputs which are
not divide = 1 are synchronized.
The outputs of the AD9515 can be synchronized by using the
SYNCB pin. Synchronization aligns the phases of the clock
outputs, respecting any phase offset that has been set on an
output’s divider.
05597-022
SYNCB
Figure 27. SYNCB Equivalent Input Circuit
Rev. 0 | Page 18 of 28
05597-092
2.5kΩ
05597-093
CLK
CLK
AD9515
Synchronization is initiated by pulling the SYNCB pin low for a
minimum of 5 ns. The input clock does not have to be present
at the time the command is issued. The synchronization occurs
after four input clock cycles.
provided by the VREF pin. All setup pins requiring the ⅔VS
level must be tied to the VREF pin.
VS
The synchronization applies to clock outputs:
that are not turned OFF
•
where the divider is not divide = 1 (divider bypassed)
SETUP PIN
S0 TO S10
30kΩ
An output with its divider set to divide = 1 (divider bypassed)
is always synchronized with the input clock, with a propagation
delay.
The SYNCB pin must be pulled up for normal operation. Do
not let the SYNCB pin float.
RSET RESISTOR
The internal bias currents of the AD9515 are set by the
RSET resistor. This resistor should be as close as possible to
the value given as a condition in the Specifications section
(RSET = 4.12 kΩ). This is a standard 1% resistor value and should
be readily obtainable. The bias currents set by this resistor
determine the logic levels and operating conditions of the
internal blocks of the AD9515. The performance figures given
in the Specifications section assume that this resistor value is
used for RSET.
VREF
The VREF pin provides a voltage level of ⅔ VS. This voltage is
one of the four logic levels used by the setup pins (S0 to S10).
These pins set the operation of the AD9515. The VREF pin
provides sufficient drive capability to drive as many of the setup
pins as necessary, up to all on a single part. The VREF pin
should be used for no other purpose.
SETUP CONFIGURATION
The specific operation of the AD9515 is set by the logic levels
applied to the setup pins (S10 to S0). These pins use four-state
logic. The logic levels used are VS and GND, plus ⅓ VS and
⅔ VS. The ⅓ VS level is provided by the internal self-biasing on
each of the setup pins (S10 to S0). This is the level seen by a
setup pin that is left not connected (NC). The ⅔ VS level is
05597-023
•
60kΩ
Figure 28. Setup Pin (S0 to S10) Equivalent Circuit
The AD9515 operation is determined by the combination of
logic levels present at the setup pins. The setup configurations
for the AD9515 are shown in Table 10 to Table 15. The four
logic levels are referred to as 0, ⅓, ⅔, and 1. These numbers
represent the fraction of the VS voltage that defines the logic
levels. See the setup pin thresholds in Table 6.
The meaning of some of the setup pins depends on the logic
level set on other pins. For example, the effect of the S9/S10 pair
of pins depends on the state of S8. S8 selects whether the phase
value selected by S9/S10 affects either OUT0 or OUT1. In
addition, if OUT1 is selected to have its phase controlled, the
effect further depends on the state of S0. If S = 0, the delay block
for OUT1 is bypassed, and the logic levels on S9/S10 set the
phase value of the OUT1 divider. However, if S0 ≠ 0, then the
full-scale delay for OUT1 is set by the logic level on S0, and
S9/S10 set the delay block fine delay (fraction of full scale).
Additionally, if a nonzero phase value is selected by S2/S3/S4
(for OUT0) or S5/S6/S7 (for OUT1), this phase overrides the
phase value selected by S9/S10. This allows a phase delay to be
selected on OUT0 while also selecting a time delay on OUT1.
S1 selects the logic level of each output. OUT0 is LVPECL. The
LVPECL output differential voltage (VOD) can be selected from
two levels: 400 mV or 780 mV. OUT1 can be set to either LVDS
or CMOS levels.
OUT0 can be turned off (powered down) by setting S2/S3/S4 to
0/1/0. OUT1 can be turned off by setting S5/S6/S7 to 0/1/0.
Do not set S2/S3/S4/S5/S6/S7 to 1/1/1/1/1/1.
Rev. 0 | Page 19 of 28
AD9515
PROGRAMMING
Table 10. S0—OUT1 Delay Full Scale
S0
0
1/3
2/3
1
Delay
Bypassed
1.5 ns
5 ns
10 ns
Table 11. S1—Output Logic Configuration
S1
0
1/3
2/3
1
OUT0
LVPECL 790 mV
LVPECL 400 mV
LVPECL 790 mV
LVPECL 400 mV
OUT1
LVDS
LVDS
CMOS
CMOS
Table 12. S2, S3, and S4—OUT0
S2
S3
S4
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
0
0
0
0
1/3
1/3
1/3
1/3
2/3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
OUT0
Divide (Duty Cycle1)
1
2 (50%)
3 (33%)
4 (50%)
5 (40%)
6 (50%)
7 (43%)
8 (50%)
9 (44%)
10 (50%)
11 (45%)
12 (50%)
OUT0 OFF
14 (50%)
15 (47%)
16 (50%)
17 (47%)
18 (50%)
19 (47%)
20 (50%)
21 (48%)
22 (50%)
23 (48%)
24 (50%)
25 (48%)
OUT0
Phase
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S2
S3
S4
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
2/3
2/3
2/3
1
1
1
1
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
1/3
1/3
1/3
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OUT0
Divide (Duty Cycle1)
26 (50%)
27 (48%)
28 (50%)
29 (48%)
30 (50%)
31 (48%)
32 (50%)
2 (50%)
4 (50%)
4 (50%)
4 (50%)
8 (50%)
8 (50%)
8 (50%)
8 (50%)
8 (50%)
8 (50%)
8 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
32 (50%)
32 (50%)
32 (50%)
32 (50%)
32 (50%)
Do not use
OUT0
Phase
0
0
0
0
0
0
0
1
1
2
3
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
3
4
5
Duty cycle is the clock signal high time divided by the total period.
Rev. 0 | Page 20 of 28
AD9515
Table 13. S5, S6, and S7—OUT1
S5
S6
S7
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
2/3
1
OUT1
Divide (Duty Cycle1)
1
2 (50%)
3 (33%)
4 (50%)
5 (40%)
6 (50%)
7 (43%)
8 (50%)
9 (44%)
10 (50%)
11 (45%)
12 (50%)
OUT1 OFF
14 (50%)
15 (47%)
16 (50%)
17 (47%)
18 (50%)
19 (47%)
20 (50%)
21 (48%)
22 (50%)
23 (48%)
24 (50%)
25 (48%)
26 (50%)
27 (48%)
28 (50%)
29 (48%)
30 (50%)
31 (48%)
32 (50%)
2 (50%)
4 (50%)
4 (50%)
4 (50%)
8 (50%)
8 (50%)
8 (50%)
8 (50%)
8 (50%)
8 (50%)
8 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
OUT1
Phase
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
2
3
1
2
3
4
5
6
7
1
2
3
4
5
6
S5
S6
S7
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OUT1
Divide (Duty Cycle1)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
16 (50%)
32 (50%)
32 (50%)
32 (50%)
32 (50%)
32 (50%)
Do not use
OUT1
Phase
7
8
9
10
11
12
13
14
15
1
2
3
4
5
Duty cycle is the clock signal high time divided by the total period.
Table 14. S8—OUT0/OUT1 Phase (Delay) Select
(Used with S9 to S10)
S8
0
1/3
2/3
1
OUT0
No Phase
Phase
No Phase
Phase (Start High)
OUT1 (Delay if S0 ≠ 0)
Phase (Delay)
No Phase
Phase (Delay) (Start High)
No Phase
Table 15. S9 and S10
S9
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
1
S10
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
OUT0 or OUT1 Phase
(Depends on S8)
Phase1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OUT1 Delay (S0 ≠ 0)
(Depends on S8)
Fine Delay
0
1/16
1/8
3/16
1/4
5/16
3/8
7/16
1/2
9/16
5/8
11/16
3/4
13/16
7/8
15/16
A phase > 0 in Table 12 or overrides the phase in Table 15.
Rev. 0 | Page 21 of 28
AD9515
DIVIDER PHASE OFFSET
The phase offset of OUT0 and OUT1 can be selected (see Table 12
to Table 15). This allows the relative phase of OUT0 and OUT1
to be set.
After a SYNC operation (see the Synchronization section), the
phase offset word of each divider determines the number of
input clock (CLK) cycles to wait before initiating a clock output
edge. By giving each divider a different phase offset, output-tooutput delays can be set in increments of the fast clock period, tCLK.
Figure 29 shows four cases, each with the divider set to divide = 4.
By incrementing the phase offset from 0 to 3, the output is
offset from the initial edge by a multiple of tCLK.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DIVIDER OUTPUT
DIV = 4
Phase offsets can be related to degrees by calculating the phase
step for a particular divide ratio:
Phase Step = 360°/Divide Ratio
Using some of the same examples:
Divide = 4
Phase Step = 360°/4 = 90°
Unique Phase Offsets in Degrees Are Phase = 0°, 90°,
180°, 270°
Divide = 9
tCLK
Phase Step = 360°/9 = 40°
PHASE = 0
Unique Phase Offsets in Degrees Are Phase = 0°, 40°, 80°,
120°, 160°, 200°, 240°, 280°, 320°
PHASE = 1
DELAY BLOCK
PHASE = 2
OUT1 includes an analog delay element that gives variable time
delays (ΔT) in the clock signal passing through that output.
PHASE = 3
tCLK
CLOCK INPUT
05597-024
2 × tCLK
3 × tCLK
OUT1 ONLY
÷N
∅SELECT
MUX
Figure 29. Phase Offset—Divider Set for Divide = 4, Phase Set from 0 to 2
For example:
LVDS
CMOS
ΔT
OUTPUT
DRIVER
CLK = 491.52 MHz
FINE DELAY ADJUST
(16 STEPS)
FULL SCALE : 1.5ns, 5ns, 10ns
tCLK = 1/491.52 = 2.0345 ns
05596-025
0
CLOCK INPUT
CLK
The resolution of the phase offset is set by the fast clock period
(tCLK) at CLK. The maximum unique phase offset is less than the
divide ratio, up to a phase offset of 15.
Figure 30. Analog Delay Block
For Divide = 4:
The amount of delay that can be used is determined by the
output frequency. The amount of delay is limited to less than
one-half cycle of the clock period. For example, for a 10 MHz
clock, the delay can extend to the full 10 ns maximum. However,
for a 100 MHz clock, the maximum delay is less than 5 ns (or
half of the period).
Phase Offset 0 = 0 ns
Phase Offset 1 = 2.0345 ns
Phase Offset 2 = 4.069 ns
Phase Offset 3 = 6.104 ns
The AD9515 allows for the selection of three full-scale delays,
1.5 ns, 5 ns, and 10 ns, set by delay full scale (see Table 10). Each
of these full-scale delays can be scaled by 16 fine adjustment
values, which are set by the delay word (see Table 14 and Table 15).
The outputs can also be described as:
Phase Offset 0 = 0°
Phase Offset 1 = 90°
Phase Offset 2 = 180°
Phase Offset 3 = 270°
Setting the phase offset to Phase = 4 results in the same relative
phase as Phase = 0° or 360°.
The delay block adds some jitter to the output. This means that
the delay function should be used primarily for clocking digital
chips, such as FPGA, ASIC, DUC, and DDC, rather than for
supplying a sample clock for data converters. The jitter is higher
for longer full scales because the delay block uses a ramp and
trip points to create the variable delay. A longer ramp means
more noise has a chance of being introduced.
Rev. 0 | Page 22 of 28
AD9515
When the delay block is OFF (bypassed), it is also powered
down.
POWER SUPPLY
OUTPUTS
The AD9515 offers three different output level choices:
LVPECL, LVDS, and CMOS. OUT0/OUT0B offers an LVPECL
differential output. The LVPECL differential voltage swing
(VOD) can be selected as either 400 mV or 790 mV (see Table 11).
OUT1/OUT1B can be selected as either an LVDS differential
output or a pair of CMOS single-ended outputs. If selected as
CMOS, OUT1 is a noninverted, single-ended output, and
OUT1B is an inverted, single-ended output.
3.3V
The AD9515 requires a 3.3 V ± 5% power supply for VS. The
tables in the Specifications section give the performance
expected from the AD9515 with the power supply voltage
within this range. In no case should the absolute maximum
range of −0.3 V to +3.6 V, with respect to GND, be exceeded
on Pin VS.
Good engineering practice should be followed in the layout of
power supply traces and the ground plane of the PCB. The
power supply should be bypassed on the PCB with adequate
capacitance (>10 μF). The AD9515 should be bypassed with
adequate capacitors (0.1 μF) at all power pins as close as
possible to the part. The layout of the AD9515 evaluation
board (AD9515/PCB) is a good example.
OUT
05597-026
OUTB
GND
Figure 31. LVPECL Output Simplified Equivalent Circuit
3.5mA
OUT
05597-027
OUTB
3.5mA
Figure 32. LVDS Output Simplified Equivalent Circuit
VS
05597-028
OUT1/
OUT1B
Figure 33. CMOS Equivalent Output Circuit
Rev. 0 | Page 23 of 28
AD9515
Exposed Metal Paddle
POWER MANAGEMENT
The exposed metal paddle on the AD9515 package is an
electrical connection, as well as a thermal enhancement. For
the device to function properly, the paddle must be properly
attached to ground (GND).
In some cases, the AD9515 can be configured to use less power
by turning off functions that are not being used.
The power-saving options include the following:
The exposed paddle of the AD9515 package must be soldered
down. The AD9515 must dissipate heat through its exposed
paddle. The PCB acts as a heat sink for the AD9515. The PCB
attachment must provide a good thermal path to a larger heat
dissipation area, such as a ground plane on the PCB. This
requires a grid of vias from the top layer down to the ground
plane (see Figure 34). The AD9515 evaluation board
(AD9515/PCB)provides a good example of how the part
should be attached to the PCB.
•
A divider is powered down when set to divide = 1
(bypassed).
•
Adjustable delay block on OUT1 is powered down when in
off mode (S0 = 0).
•
An unneeded output can be powered down (see Table 12
and Table 13). This also powers down the divider for that
output.
05597-035
VIAS TO GND PLANE
Figure 34. PCB Land for Attaching Exposed Paddle
Rev. 0 | Page 24 of 28
AD9515
APPLICATIONS
USING THE AD9515 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed, analog-to-digital converter (ADC) is extremely
sensitive to the quality of the sampling clock provided by the
user. An ADC can be thought of as a sampling mixer, and any
noise, distortion, or timing jitter on the clock is combined with
the desired signal at the A/D output. Clock integrity requirements scale with the analog input frequency and resolution,
with higher analog input frequency applications at ≥14-bit
resolution being the most stringent. The theoretical SNR of an
ADC is limited by the ADC resolution and the jitter on the
sampling clock. Considering an ideal ADC of infinite resolution
where the step size and quantization error can be ignored, the
available SNR can be expressed approximately by
⎡ 1 ⎤
SNR = 20 × log ⎢
⎥
⎣ 2πft J ⎦
where f is the highest analog frequency being digitized.
tj is the rms jitter on the sampling clock.
Figure 35 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
110
LVPECL CLOCK DISTRIBUTION
The low voltage, positive emitter-coupled, logic (LVPECL)
outputs of the AD9515 provide the lowest jitter clock signals
available from the AD9515. The LVPECL outputs (because they
are open emitter) require a dc termination to bias the output
transistors. The simplified equivalent circuit in Figure 31 shows
the LVPECL output stage.
In most applications, a standard LVPECL far-end termination is
recommended, as shown in Figure 36. The resistor network is
designed to match the transmission line impedance (50 Ω) and
the switching threshold (VS − 1.3 V).
18
VS
16
VS
70
400
f
S
2ps
12
LVPECL
127Ω
SINGLE-ENDED
(NOT COUPLED)
10
LVPECL
50Ω
VT = VS – 1.3V
50
10p
s
127Ω
14
fS
1ps
60
VS
50Ω
83Ω
83Ω
05597-030
80
TJ =
100
fS
200
ENOB
SNR (dB)
90
8
40
Figure 36. LVPECL Far-End Termination
100
05597-091
6
30
10
1k
fA FULL-SCALE SINE WAVE ANALOG FREQUENCY (MHz)
VS
VS
0.1nF
Figure 35. ENOB and SNR vs. Analog Input Frequency
See Application Notes AN-756 and AN-501 at www.analog.com.
LVPECL
0.1nF
200Ω
100Ω DIFFERENTIAL 100Ω
(COUPLED)
LVPECL
200Ω
Figure 37. LVPECL with Parallel Transmission Line
Rev. 0 | Page 25 of 28
05597-031
1
SNR = 20log 2πf T
A J
100
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.)
The AD9515 features both LVPECL and LVDS outputs that
provide differential clock outputs, which enable clock solutions
that maximize converter SNR performance. The input
requirements of the ADC (differential or single-ended, logic
level, termination) should be considered when selecting the best
clocking/converter solution.
AD9515
LVDS CLOCK DISTRIBUTION
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9515 do not supply enough
current to provide a full voltage swing with a low impedance
resistive, far-end termination, as shown in Figure 40. The
far-end termination network should match the PCB trace
impedance and provide the desired switching point. The
reduced signal swing may still meet receiver input requirements
in some applications. This can be useful when driving long
trace lengths on less critical nets.
The AD9515 provides one clock output (OUT2) that is
selectable as either CMOS or LVDS levels. Low voltage
differential signaling (LVDS) is a differential output option
for OUT2. LVDS uses a current mode output stage. The
current is 3.5 mA, which yields 350 mV output swing across
a 100 Ω resistor. The LVDS output meets or exceeds all
ANSI/TIA/EIA-644 specifications.
A recommended termination circuit for the LVDS outputs
is shown in Figure 38.
VS
VS
VS
10Ω
50Ω
100Ω
CMOS
OUT1/OUT1B
SELECTED AS CMOS
LVDS
100Ω
3pF
05597-034
100Ω
100Ω
DIFFERENTIAL (COUPLED)
05597-032
LVDS
Figure 40. CMOS Output with Far-End Termination
Figure 38. LVDS Output Termination
See Application Note AN-586 at www.analog.com for more
information on LVDS.
CMOS CLOCK DISTRIBUTION
The AD9515 provides one output (OUT1) that is selectable as
either CMOS or LVDS levels. When selected as CMOS, this
output provides for driving devices requiring CMOS level logic
at their clock inputs.
Whenever single-ended CMOS clocking is used, some of the
following general guidelines should be used.
Point-to-point nets should be designed such that a driver has
only one receiver on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver. The
value of the resistor is dependent on the board design and
timing requirements (typically 10 Ω to 100 Ω is used). CMOS
outputs are also limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
3 inches are recommended to preserve signal rise/fall times and
preserve signal integrity.
10Ω
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9515 offers both LVPECL and
LVDS outputs that are better suited for driving long traces
where the inherent noise immunity of differential signaling
provides superior performance for clocking converters.
SETUP PINS (S0 TO S10)
The setup pins that require a logic level of ⅓ VS (internal selfbias) should be tied together and bypassed to ground via a
capacitor.
The setup pins that require a logic level of ⅔ VS should be tied
together, along with the VREF pin, and bypassed to ground via
a capacitor.
POWER AND GROUNDING CONSIDERATIONS AND
POWER SUPPLY REJECTION
Many applications seek high speed and performance under less
than ideal operating conditions. In these application circuits, the
implementation and construction of the PCB is as important
as the circuit design. Proper RF techniques must be used for
device selection, placement, and routing, as well as power
supply bypassing and grounding to ensure optimum
performance.
60.4Ω
1.0 INCH
CMOS
5pF
GND
05597-033
MICROSTRIP
Figure 39. Series Termination of CMOS Output
Rev. 0 | Page 26 of 28
AD9515
PHASE NOISE AND JITTER MEASUREMENT SETUPS
WENZEL
OSCILLATOR
EVALUATION BOARD
BALUN
SPLITTER
ZESC-2-11
OUT1
TERM
AMP
OUT1B
TERM
+28dB
CLK1
ATTENUATOR
–12dB
SIG IN
ATTENUATOR
–7dB
REF IN
0°
EVALUATION BOARD
ZFL1000VH2
OUT1
TERM
AMP
OUT1B
TERM
+28dB
CLK1
VARIABLE DELAY
COLBY PDL30A
0.01ns STEP
TO 10ns
05597-041
BALUN
AD9515
AGILENT E5500B
PHASE NOISE MEASUREMENT SYSTEM
ZFL1000VH2
AD9515
Figure 41. Additive Phase Noise Measurement Configuration
WENZEL
OSCILLATOR
ANALOG
SOURCE
EVALUATION BOARD
PC
AD9515
BALUN
WENZEL
OSCILLATOR
OUT1
TERM
OUT1B
TERM
CLK
SNR
ADC
CLK1
FFT
05597-042
tJ_RMS
DATA CAPTURE CARD
FIFO
Figure 42. Jitter Determination by Measuring SNR of ADC
2
t J_RMS =
⎡V
⎤
⎢ A_RMS ⎥ − SND × BW 2 − θ QUANTIZATION 2 + θ THERMAL 2 + θ DNL 2
⎢ SNR
⎥
⎣ 10 20 ⎦
2
2π × f A × V A_PK
(
) (
[
]
where:
tj_RMS is the rms time jitter.
SNR is the signal-to-noise ratio.
SND is the source noise density in nV/√Hz.
BW is the SND filter bandwidth.
VA is the analog source voltage.
fA is the analog frequency.
The θ terms are the quantization, thermal, and DNL errors.
Rev. 0 | Page 27 of 28
)
AD9515
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
25
24
PIN 1
INDICATOR
TOP
VIEW
0.50
BSC
4.75
BSC SQ
0.50
0.40
0.30
12° MAX
1.00
0.85
0.80
PIN 1
INDICATOR
32
1
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
17
16
9
8
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 43. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad (CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9515BCPZ 1
AD9515BCPZ-REEL71
AD9515/PCB
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
Z = Pb-free part.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05597–0–7/05(0)
Rev. 0 | Page 28 of 28
Package Option
CP-32-2
CP-32-2