Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/°C On-Chip Reference AD5624R/AD5644R/AD5664R Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD GND VREFIN/VREFOUT AD5624R/AD5644R/AD5664R 1.25V/2.5V REF INPUT REGISTER DAC REGISTER STRING DAC A BUFFER VOUTA INPUT REGISTER DAC REGISTER STRING DAC B BUFFER VOUTB INPUT REGISTER DAC REGISTER STRING DAC C BUFFER VOUTC INPUT REGISTER DAC REGISTER STRING DAC D BUFFER VOUTD SCLK INTERFACE LOGIC SYNC DIN POWER-ON LOGIC APPLICATIONS POWERDOWN LOGIC 05856-001 Low power, smallest pin-compatible, quad nanoDACs AD5664R: 16 bits AD5644R: 14 bits AD5624R: 12 bits User-selectable external or internal reference External reference default On-chip 1.25 V/2.5 V, 5 ppm/°C reference 10-lead MSOP; 10-lead, 3 mm × 3 mm LFCSP_WD; and 12-ball, 1.665 mm × 2.245 mm WLCSP 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale Per channel power-down Serial interface, up to 50 MHz Figure 1. Process controls Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Table 1. Related Devices Part No. AD5624/AD5664 AD5666 Description 2.7 V to 5.5 V quad, 12-/16-bit DACs, external reference 2.7 V to 5.5 V quad, 16-bit DAC, internal reference, LDAC, CLR pins GENERAL DESCRIPTION The AD5624R/AD5644R/AD5664R, members of the nanoDAC® family, are low power, quad, 12-/14-/16-bit buffered voltage-out DACs. All devices operate from a single 2.7 V to 5.5 V supply and are guaranteed monotonic by design. 480 nA at 5 V and provides software-selectable output loads while in power-down mode. The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The AD5624R/AD5644R/AD5664R have an on-chip reference. The AD56x4R-3 has a 1.25 V, 5 ppm/°C reference, giving a fullscale output range of 2.5 V; the AD56x4R-5 has a 2.5 V, 5 ppm/°C reference giving a full-scale output range of 5 V. The on-chip reference is off at power-up, allowing the use of an external reference; all devices can be operated from a single 2.7 V to 5.5 V supply. The internal reference is enabled via a software write. The AD5624R/AD5644R/AD5664R use a versatile 3-wire serial interface that operates at clock rates up to 50 MHz, and is compatible with standard SPI, QSPI™, MICROWIRE™, and DSP interface standards. The on-chip precision output amplifier enables rail-to-rail output swing. The part incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V and remains there until a valid write takes place. The part contains a per-channel power-down feature that reduces the current consumption of the device to Rev. C PRODUCT HIGHLIGHTS 1. 2. 3. 4. Quad 12-/14-/16-bit DACs. On-chip 1.25 V/2.5 V, 5 ppm/°C reference. Available in 10-lead MSOP; 10-lead, 3 mm × 3 mm LFCSP_WD; and 12-ball, 1.665 mm × 2.245 mm WLCSP. Low power, typically consumes 1.32 mW at 3 V and 2.25 mW at 5 V. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2006–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5624R/AD5644R/AD5664R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Internal Reference ...................................................................... 20 Applications ....................................................................................... 1 External Reference ..................................................................... 20 Functional Block Diagram .............................................................. 1 Serial Interface ............................................................................ 20 General Description ......................................................................... 1 Input Shift Register .................................................................... 21 Product Highlights ........................................................................... 1 SYNC Interrupt........................................................................... 21 Revision History ............................................................................... 2 Power-On Reset .......................................................................... 22 Specifications..................................................................................... 3 Software Reset ............................................................................. 22 AD5624R-5/AD5644R-5/AD5664R-5 ...................................... 3 Power-Down Modes .................................................................. 22 AD5624R-3/AD5644R-3/AD5664R-3 ...................................... 4 LDAC Function ........................................................................... 23 AC Characteristics ........................................................................ 6 Internal Reference Setup ........................................................... 23 Timing Characteristics ................................................................ 7 Microprocessor Interfacing ....................................................... 24 Timing Diagram ........................................................................... 7 Applications Information .............................................................. 25 Absolute Maximum Ratings ............................................................ 8 Using a Reference as a Power Supply for the AD5624R/AD5644R/AD5664R ............................................... 25 ESD Caution .................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 18 Theory of Operation ...................................................................... 20 Digital-to-Analog Section ......................................................... 20 Resistor String ............................................................................. 20 Output Amplifier ........................................................................ 20 Bipolar Operation Using the AD5624R/AD5644R/AD5664R ....................................................................................................... 25 Using AD5624R/AD5644R/AD5664R with a Galvanically Isolated Interface ........................................................................ 25 Power Supply Bypassing and Grounding ................................ 26 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 28 REVISION HISTORY 4/13—Rev. B to Rev. C Added 12-Ball WLCSP ...................................................... Universal Changes to Features and Product Highlights Sections ................ 1 Change to Reference TC Parameter, Table 2................................. 3 Added Thermal Impedance, WLCSP Package (4-Layer Board), θJA Parameter, Table 6 ....................................................................... 8 Added Figure 4; Renumbered Sequentially .................................. 9 Changes to Figure 3 Caption and Table 7...................................... 9 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 28 4/08—Rev. A to Rev. B Changes to Figure 50...................................................................... 20 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 28 11/06—Rev. 0 to Rev. A Changes to Reference Output Parameter in Table 2 .....................3 Changes to Reference Output Parameter in Table 3 .....................5 Added Note to Figure 3 ....................................................................9 4/06—Revision 0: Initial Version Rev. C | Page 2 of 28 Data Sheet AD5624R/AD5644R/AD5664R SPECIFICATIONS AD5624R-5/AD5644R-5/AD5664R-5 VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE 2 AD5664R Resolution Relative Accuracy Differential Nonlinearity AD5644R Resolution Relative Accuracy Differential Nonlinearity AD5624R Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Offset Error Full-Scale Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio DC Crosstalk External Reference Min DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUTS Reference Current Reference Input Range Reference Input Impedance REFERENCE OUTPUT Output Voltage Reference TC3 Output Impedance Unit Conditions/Comments ±16 ±1 Bits LSB LSB Guaranteed monotonic by design ±4 ±0.5 Bits LSB LSB Guaranteed monotonic by design 16 ±8 14 ±2 12 ±2 ±2.5 −100 Bits LSB LSB mV mV % of FSR % of FSR µV/°C ppm dB 10 10 5 25 20 10 µV µV/mA µV µV µV/mA µV ±0.5 2 ±1 −0.1 Internal Reference OUTPUT CHARACTERISTICS 3 Output Voltage Range Capacitive Load Stability B Grade 1 Typ Max 0 ±1 ±0.25 10 ±10 ±1 ±1.5 VDD 2 10 0.5 30 4 170 0.75 ±5 ±10 ±15 7.5 All ones loaded to DAC register Of FSR/°C DAC code = midscale; VDD = 5 V ± 10% Due to full-scale output change, RL = 2 kΩ to GND or VDD Due to load current change Due to powering down (per channel) Due to full-scale output change, RL = 2 kΩ to GND or VDD Due to load current change Due to powering down (per channel) RL = ∞ RL = 2 kΩ VDD = 5 V Coming out of power-down mode; VDD = 5 V 200 VDD µA V kΩ VREF = VDD = 5.5 V 2.505 ±10 V ppm/°C ppm/°C ppm/°C kΩ At ambient MSOP package models LFCSP package models WLCSP package models 26 2.495 V nF nF Ω mA µs Guaranteed monotonic by design All zeroes loaded to DAC register Rev. C | Page 3 of 28 AD5624R/AD5644R/AD5664R Parameter LOGIC INPUTS3 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD Normal Mode 4 Min Data Sheet B Grade 1 Typ Max Unit Conditions/Comments ±2 0.8 µA V V pF All digital inputs VDD = 5 V VDD = 5 V 5.5 V 0.9 1.2 1 mA mA µA 2 3 4.5 0.45 0.95 0.48 All Power-Down Modes 5 VIH = VDD, VIL = GND, VDD = 4.5 V to 5.5 V Internal reference off Internal reference on Temperature range: B grade: −40°C to +105°C. Linearity calculated using a reduced code range: AD5664R (Code 512 to Code 65,024); AD5644R (Code 128 to Code 16,256); AD5624R (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All DACs powered down. 1 2 AD5624R-3/AD5644R-3/AD5664R-3 VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter STATIC PERFORMANCE 2 AD5664R Resolution Relative Accuracy Differential Nonlinearity AD5644R Resolution Relative Accuracy Differential Nonlinearity AD5624R Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Offset Error Full-Scale Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio DC Crosstalk External Reference Internal Reference Min B Grade 1 Typ Max Unit Conditions/Comments ±16 ±1 Bits LSB LSB Guaranteed monotonic by design ±4 ±0.5 Bits LSB LSB Guaranteed monotonic by design 16 ±8 14 ±2 12 ±2 ±2.5 −100 Bits LSB LSB mV mV % of FSR % of FSR µV/°C ppm dB 10 10 5 25 20 10 µV µV/mA µV µV µV/mA µV ±0.5 2 ±1 −0.1 ±1 ±0.25 10 ±10 ±1 ±1.5 Rev. C | Page 4 of 28 Guaranteed monotonic by design All zeroes loaded to DAC register All ones loaded to DAC register Of FSR/°C DAC code = midscale; VDD = 3 V ± 10% Due to full-scale output change, RL = 2 kΩ to GND or VDD Due to load current change Due to powering down (per channel) Due to full-scale output change, RL = 2 kΩ to GND or VDD Due to load current change Due to powering down (per channel) Data Sheet Parameter OUTPUT CHARACTERISTICS 3 Output Voltage Range Capacitive Load Stability DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUTS Reference Current Reference Input Range Reference Input Impedance REFERENCE OUTPUT Output Voltage Reference TC3 Output Impedance LOGIC INPUTS3 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD Normal Mode 4 All Power-Down Modes 5 AD5624R/AD5644R/AD5664R Min B Grade 1 Typ Max 0 VDD 2 10 0.5 30 4 170 0 ±5 ±10 7.5 VDD = 3 V Coming out of power-down mode; VDD = 3 V VREF = VDD = 3.6 V 1.253 ±15 V ppm/°C ppm/°C kΩ At ambient MSOP package models LFCSP package models ±2 0.8 µA V V pF All digital inputs VDD = 3 V VDD = 3 V 3.6 V 0.85 1.15 1 mA mA µA 3 0.44 0.95 0.2 RL = ∞ RL = 2 kΩ µA V kΩ 2 2.7 V nF nF Ω mA µs Conditions/Comments 200 VDD 26 1.247 Unit VIH = VDD, VIL = GND, VDD = 2.7 V to 3.6 V Internal reference off Internal reference on Temperature range: B grade: −40°C to +105°C. Linearity calculated using a reduced code range: AD5664R (Code 512 to Code 65,024); AD5644R (Code 128 to Code 16,256); AD5624R (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All DACs powered down. 1 2 Rev. C | Page 5 of 28 AD5624R/AD5644R/AD5664R Data Sheet AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. 1 Table 4. Parameter 2 Output Voltage Settling Time AD5624R AD5644R AD5664R Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Reference Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Output Noise Spectral Density Output Noise 1 2 3 Min Typ Max Unit Conditions/Comments 3 3 3.5 4 1.8 10 0.1 −90 0.1 1 4 1 4 340 −80 120 100 15 4.5 5 7 µs µs µs V/µs nV-s nV-s dB nV-s nV-s nV-s nV-s nV-s kHz dB nV/√Hz nV/√Hz µV p-p ¼ to ¾ scale settling to ±0.5 LSB ¼ to ¾ scale settling to ±0.5 LSB ¼ to ¾ scale settling to ±2 LSB Guaranteed by design and characterization, not production tested. See the Terminology section. Temperature range is −40°C to +105°C, typical at 25°C. Rev. C | Page 6 of 28 1 LSB change around major carry VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz External reference Internal reference External reference Internal reference VREF = 2 V ± 0.1 V p-p VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz DAC code = midscale, 1 kHz DAC code = midscale, 10 kHz 0.1 Hz to 10 Hz Data Sheet AD5624R/AD5644R/AD5664R TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2). VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. 1 Table 5. Limit at TMIN, TMAX VDD = 2.7 V to 5.5 V 20 9 9 13 5 5 0 15 13 0 Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 t9 t10 1 2 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to SCLK fall ignore SCLK falling edge to SYNC fall ignore Guaranteed by design and characterization, not production tested. Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. TIMING DIAGRAM t10 t1 t9 SCLK t8 t3 t4 t2 t7 SYNC DIN DB23 t6 DB0 Figure 2. Serial Write Operation Rev. C | Page 7 of 28 05856-002 t5 AD5624R/AD5644R/AD5664R Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to GND VOUT to GND VREFIN/VREFOUT to GND Digital Input Voltage to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) Power Dissipation Thermal Impedance LFCSP_WD Package (4-Layer Board) θJA MSOP Package (4-Layer Board) θJA θJC WLCSP Package (4-Layer Board) θJA Reflow Soldering Peak Temperature Pb-Free Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +105°C −65°C to +150°C 150°C (TJ max − TA)/θJA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 61°C/W 142°C/W 43.7°C/W 75°C/W 260°C ± 5°C Rev. C | Page 8 of 28 Data Sheet AD5624R/AD5644R/AD5664R PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS BALL A1 INDICATOR 1 2 3 VREFIN/ VREFOUT GND VOUTA VDD GND VOUTB DIN GND VOUTC A GND 3 VOUTC 4 VOUTD 5 AD5624R/ AD5644R/ AD5664R TOP VIEW (Not to Scale) VREFIN/VREFOUT 9 VDD 8 DIN 7 SCLK 6 SYNC B C SCLK SYNC VOUTD D EXPOSED PAD TIED TO GND ON LFCSP PACKAGE TOP VIEW (BALL SIDE DOWN) Not to Scale 05856-104 VOUTB 2 10 05856-003 VOUTA 1 Figure 4. 12-Ball WLCSP Pin Configuration Figure 3. 10-Lead LFCSP and 10-Lead MSOP Pin Configuration Table 7. Pin Function Descriptions LFCSP 1 2 3 Pin No. MSOP 1 2 3 4 5 6 Mnemonic VOUTA VOUTB GND Description Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Ground Reference Point for all Circuitry on the Part. 4 5 6 WLCSP A3 B3 A2, B2, C2 C3 D3 D2 VOUTC VOUTD SYNC 7 7 D1 SCLK 8 8 C1 DIN 9 9 B1 VDD 10 10 A1 VREFIN/VREFOUT N/A N/A EPAD Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. The AD5624R/AD5644R/AD5664R have a common pin for reference input and reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. Exposed Pad. The exposed pad must be tied to GND on the LFCSP package. Rev. C | Page 9 of 28 AD5624R/AD5644R/AD5664R Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 10 VDD = VREF = 5V TA = 25°C VDD = VREF = 5V TA = 25°C 0.8 6 0.6 4 0.4 DNL ERROR (LSB) 2 0 –2 –4 0.2 0 –0.2 –0.4 –0.6 05856-004 –6 –8 –10 0 05856-007 INL ERROR (LSB) 8 –0.8 –1.0 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE 10k 20k 30k CODE 40k 50k 60k Figure 8. AD5664R DNL, External Reference Figure 5. AD5664R INL, External Reference 4 0.5 VDD = VREF = 5V TA = 25°C 3 VDD = VREF = 5V TA = 25°C 0.4 0.3 DNL ERROR (LSB) INL ERROR (LSB) 2 1 0 –1 0.2 0.1 0 –0.1 –0.2 –2 05856-005 –4 0 2500 5000 10000 7500 CODE 12500 05856-008 –0.3 –3 –0.4 –0.5 15000 0 Figure 6. AD5644R INL, External Reference 2500 5000 7500 10000 CODE 12500 15000 Figure 9. AD5644R DNL, External Reference 1.0 0.20 VDD = VREF = 5V 0.8 TA = 25°C VDD = VREF = 5V TA = 25°C 0.15 0.6 0.10 DNL ERROR (LSB) 0.2 0 –0.2 –0.4 0.05 0 –0.05 –0.10 –0.6 05856-006 –0.8 –1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 –0.15 05856-009 INL ERROR (LSB) 0.4 –0.20 4000 0 Figure 7. AD5624R INL, External Reference 500 1000 1500 2000 2500 CODE 3000 3500 Figure 10. AD5624R DNL, External Reference Rev. C | Page 10 of 28 4000 Data Sheet AD5624R/AD5644R/AD5664R 1.0 4 0.4 0 60000 65000 15000 16250 55000 50000 45000 40000 35000 30000 0 65000 CODE 05856-010 60000 55000 50000 45000 40000 –1.0 35000 –0.8 30000 –8 –10 25000 –0.6 20000 –6 10000 –0.4 15000 –4 05856-013 –0.2 25000 0 –2 0.2 20000 2 15000 DNL ERROR (LSB) 0.6 0 VDD = 5V VREFOUT = 2.5V TA = 25°C 0.8 6 5000 INL ERROR (LSB) 8 10000 VDD = 5V VREFOUT = 2.5V TA = 25°C 5000 10 CODE Figure 14. AD5664R-5 DNL, Internal Reference Figure 11. AD5664R-5 INL, Internal Reference 0.5 4 VDD = 5V VREFOUT = 2.5V TA = 25°C 3 VDD = 5V VREFOUT = 2.5V TA = 25°C 0.4 0.3 DNL ERROR (LSB) INL ERROR (LSB) 2 1 0 –1 0.2 0.1 0 –0.1 –0.2 –2 CODE 13750 11250 12500 8750 10000 7500 6250 5000 3750 2500 0 1250 05856-011 15000 16250 13750 11250 12500 8750 10000 7500 6250 5000 3750 2500 –0.5 1250 –4 0 –0.4 05856-014 –0.3 –3 CODE Figure 15. AD5644R-5 DNL, Internal Reference Figure 12. AD5644R-5 INL, Internal Reference 0.20 1.0 VDD = 5V VREFOUT = 2.5V TA = 25°C 0.8 VDD = 5V VREFOUT = 2.5V TA = 25°C 0.15 0.6 DNL ERROR (LSB) 0.2 0 –0.2 0.05 0 –0.05 –0.4 –0.10 –0.6 –0.8 –1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 05856-015 –0.15 05856-012 INL ERROR (LSB) 0.10 0.4 –0.20 0 4000 500 1000 1500 2000 2500 CODE 3000 3500 Figure 16. AD5624R-5 DNL, Internal Reference Figure 13. AD5624R-5 INL, Internal Reference Rev. C | Page 11 of 28 4000 AD5624R/AD5644R/AD5664R Data Sheet 1.0 10 VDD = 3V VREFOUT = 1.25V TA = 25°C 0.6 4 0.4 DNL ERROR (LSB) 6 2 0 –2 0.2 0 –0.2 –4 –0.4 –6 –0.6 65000 16250 CODE CODE Figure 17. AD5664R-3 INL, Internal Reference 05856-019 60000 15000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 –1.0 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 5000 10000 –0.8 0 –8 –10 0 VDD = 3V VREFOUT = 1.25V TA = 25°C 0.8 05856-016 INL ERROR (LSB) 8 Figure 20. AD5664R-3 DNL, Internal Reference 4 0.5 VDD = 3V VREFOUT = 1.25V TA = 25°C 3 VDD = 3V VREFOUT = 1.25V TA = 25°C 0.4 0.3 DNL ERROR (LSB) INL ERROR (LSB) 2 1 0 –1 0.2 0.1 0 –0.1 –0.2 –2 –0.3 05856-017 –0.4 CODE CODE Figure 18. AD5644R-3 INL, Internal Reference 05856-020 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 0 –0.5 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 –4 1250 –3 Figure 21. AD5644R-3 DNL, Internal Reference 1.0 0.20 VDD = 3V VREFOUT = 1.25V TA = 25°C 0.8 0.6 VDD = 3V VREFOUT = 1.25V TA = 25°C 0.15 DNL ERROR (LSB) 0.2 0 –0.2 0.05 0 –0.05 –0.4 –0.10 –0.6 –1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 4000 Figure 19. AD5624R-3 INL, Internal Reference –0.20 0 500 1000 1500 2000 2500 CODE 3000 3500 Figure 22. AD5624R-3 DNL, Internal Reference Rev. C | Page 12 of 28 4000 05856-021 –0.15 –0.8 05856-018 INL ERROR (LSB) 0.10 0.4 Data Sheet AD5624R/AD5644R/AD5664R 8 0 6 VDD = VREF = 5V VDD = 5V –0.02 MAX INL –0.04 GAIN ERROR 4 ERROR (% FSR) 2 MAX DNL 0 MIN DNL –2 –0.08 –0.10 –0.12 –0.14 –4 MIN INL 05856-022 –6 –8 –40 –20 0 20 40 60 TEMPERATURE (°C) FULL-SCALE ERROR –0.16 80 –0.18 –0.20 –40 100 –20 0 20 40 60 TEMPERATURE (°C) 80 100 05856-025 ERROR (LSB) –0.06 Figure 26. Gain Error and Full-Scale Error vs. Temperature Figure 23. INL Error and DNL Error vs. Temperature 10 1.5 MAX INL 8 1.0 ZERO-SCALE ERROR 6 0.5 VDD = 5V TA = 25°C ERROR (mV) ERROR (LSB) 4 2 MAX DNL 0 MIN DNL –2 0 –0.5 –1.0 –4 –1.5 OFFSET ERROR –6 MIN INL 1.75 2.25 2.75 3.25 VREF (V) 3.75 4.25 4.75 –2.5 –40 0 20 40 60 TEMPERATURE (°C) 80 100 Figure 27. Zero-Scale Error and Offset Error vs. Temperature Figure 24. INL Error and DNL Error vs. VREF 1.0 8 6 MAX INL TA = 25°C 0.5 4 ERROR (% FSR) GAIN ERROR 2 MAX DNL 0 MIN DNL –2 0 FULL-SCALE ERROR –0.5 –1.0 –4 –1.5 MIN INL –8 2.7 3.2 3.7 4.2 VDD (V) 4.7 5.2 –2.0 2.7 3.2 3.7 4.2 VDD (V) 4.7 5.2 Figure 28. Gain Error and Full-Scale Error vs. Supply Figure 25. INL Error and DNL Error vs. Supply Rev. C | Page 13 of 28 05856-027 –6 05856-024 ERROR (LSB) –20 05856-026 1.25 05856-023 –8 –10 0.75 –2.0 AD5624R/AD5644R/AD5664R Data Sheet 1.0 8 TA = 25°C 0.5 7 ZERO-SCALE ERROR 6 FREQUENCY 0 –0.5 –1.0 5 4 3 –1.5 2 –2.0 1 OFFSET ERROR 3.7 3.2 4.2 VDD (V) 4.7 5.2 0 05856-028 –2.5 2.7 0.39 0.40 0.41 IDD (mA) 0.42 0.43 Figure 32. IDD Histogram with External Reference, 3.6 V Figure 29. Zero-Scale Error and Offset Error vs. Supply 6 05856-060 ERROR (mV) VDD = 3.6V TA = 25°C 8 VDD = 5.5V TA = 25°C VDD = 3.6V TA = 25°C 7 5 FREQUENCY FREQUENCY 6 4 3 5 4 3 2 2 0 0.41 0.42 0.43 IDD (mA) 0.44 0 0.45 0.96 0.5 VDD = 5.5V TA = 25°C 0.4 DAC LOADED WITH FULL-SCALE SOURCING CURRENT DAC LOADED WITH ZERO-SCALE SINKING CURRENT ERROR VOLTAGE (V) 0.3 3 2 0.2 0.1 VDD = 3V VREFOUT = 1.25V 0 –0.1 –0.2 VDD = 5V VREFOUT = 2.5V –0.3 1 0.92 0.94 0.96 IDD (mA) –0.4 –0.5 –10 0.98 Figure 31. IDD Histogram with Internal Reference, VREFOUT = 2.5 V –8 –6 –4 –2 0 2 CURRENT (mA) 4 6 8 Figure 34. Headroom at Rails vs. Source and Sink Rev. C | Page 14 of 28 10 05856-031 4 05856-030 FREQUENCY 0.94 IDD (mA) Figure 33. IDD Histogram with Internal Reference, VREFOUT = 1.25 V 5 0 0.92 0.90 Figure 30. IDD Histogram with External Reference, 5.5 V 6 05856-061 1 05856-029 1 Data Sheet AD5624R/AD5644R/AD5664R 6 5 VDD = 5V VREFOUT = 2.5V TA = 25°C FULL SCALE 3/4 SCALE VOUT (V) 4 3 VDD = VREF = 5V TA = 25°C FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2kΩ AND 200pF TO GND MIDSCALE 2 1/4 SCALE 1 VOUT = 909mV/DIV –20 –10 0 10 CURRENT (mA) 20 1 30 05856-046 –1 –30 ZERO SCALE 05856-048 0 TIME BASE = 4µs/DIV Figure 38. Full-Scale Settling Time, 5 V Figure 35. AD56x4R-5 Source and Sink Capability 4 3 VDD = VREF = 5V TA = 25°C VDD = 3V VREFOUT = 1.25V TA = 25°C VOUT (V) FULL SCALE 3/4 SCALE 2 MIDSCALE 1 VDD 1 1/4 SCALE 0 MAX(C2) 420.0mV ZERO SCALE 2 –10 0 10 CURRENT (mA) 20 30 CH1 2.0V CH2 500mV M100µs 125MS/s A CH1 1.28V 8.0ns/pt 05856-049 –20 05856-047 VOUT –1 –30 Figure 39. Power-On Reset to 0 V Figure 36. AD56x4R-3 Source and Sink Capability 0.50 SYNC VDD = VREFIN = 5V 0.45 1 0.40 SCLK VDD = VREFIN = 3V 3 0.30 0.25 0.20 0.15 VOUT 0.10 VDD = 5V 0.05 TA = 25°C 0 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 05856-050 2 05856-063 IDD (mA) 0.35 CH1 5.0V CH3 5.0V CH2 500mV M400ns A CH1 Figure 40. Exiting Power-Down to Midscale Figure 37. Supply Current vs. Temperature Rev. C | Page 15 of 28 1.4V VDD = VREF = 5V TA = 25°C DAC LOADED WITH MIDSCALE VDD = VREF = 5V TA = 25°C 5ns/SAMPLE NUMBER GLITCH IMPULSE = 9.494nV 1LSB CHANGE AROUND MIDSCALE (0x8000 TO 0x7FFF) 1 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 Y AXIS = 2µV/DIV X AXIS = 4s/DIV 512 Figure 44. 0.1 Hz to 10 Hz Output Noise Plot, External Reference Figure 41. Digital-to-Analog Glitch Impulse (Negative) 2.498 VDD = 5V VREFOUT = 2.5V TA = 25°C DAC LOADED WITH MIDSCALE VDD = VREF = 5V TA = 25°C 5ns/SAMPLE NUMBER ANALOG CROSSTALK = 0.424nV 2.497 05856-051 2.538 2.537 2.536 2.535 2.534 2.533 2.532 2.531 2.530 2.529 2.528 2.527 2.526 2.525 2.524 2.523 2.522 2.521 Data Sheet 05856-058 VOUT (V) AD5624R/AD5644R/AD5664R 10µV/DIV VOUT (V) 2.496 2.495 2.494 1 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference 5µV/DIV VDD = 3V VREFOUT = 1.25V TA = 25°C DAC LOADED WITH MIDSCALE VDD = 5V VREFOUT = 2.5V TA = 25°C 5ns/SAMPLE NUMBER ANALOG CROSSTALK = 4.462nV 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 Figure 43. Analog Crosstalk, 2.5 V Internal Reference 1 05856-062 VOUT (V) Figure 42. Analog Crosstalk, External Reference 2.496 2.494 2.492 2.490 2.488 2.486 2.484 2.482 2.480 2.478 2.476 2.474 2.472 2.470 2.468 2.466 2.464 2.462 2.460 2.458 2.456 5s/DIV 512 4s/DIV 512 05856-053 2.491 05856-059 2.492 05856-052 2.493 Figure 46. 0.1 Hz to 10 Hz Output Noise Plot, 1.25 V Internal Reference Rev. C | Page 16 of 28 Data Sheet AD5624R/AD5644R/AD5664R 800 16 TA = 25°C MIDSCALE LOADED 700 VREF = VDD TA = 25°C VDD = 3V 12 500 TIME (µs) OUTPUT NOISE (nV/√Hz) 14 600 400 10 300 VDD = 5V 8 VDD = 5V VREFOUT = 2.5V 200 6 1k 10k FREQUENCY (Hz) 100k 1M 4 05856-054 0 100 0 Figure 47. Noise Spectral Density, Internal Reference 3 4 5 6 7 CAPACITANCE (nF) 5 VDD = 5V TA = 25°C DAC LOADED WITH FULL SCALE VREF = 2V ± 0.3V p-p 8 9 10 VDD = 5V TA = 25°C 0 AMPLITUDE (dB) –5 –50 –60 –70 –80 –10 –15 –20 –25 –30 –90 2k 4k 6k FREQUENCY (Hz) 8k 10k Figure 48. Total Harmonic Distortion –40 10k 100k 1M FREQUENCY (Hz) Figure 50. Multiplying Bandwidth Rev. C | Page 17 of 28 10M 05856-057 –35 –100 05856-055 AMPLITUDE (dB) –40 2 Figure 49. Settling Time vs. Capacitive Load –20 –30 1 05856-056 VDD = 3V VREFOUT = 1.25V 100 AD5624R/AD5644R/AD5664R Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 5. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 8. Zero-Code Error Zero-scale error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5664R because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. A plot of zero-code error vs. temperature can be seen in Figure 27. Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD − 1 LSB. Full-scale error is expressed in percent of full-scale range. A plot of full-scale error vs. temperature can be seen in Figure 26. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed as % of FSR. Zero-Code Error Drift This is a measurement of the change in zero-code error with a change in temperature. It is expressed in µV/°C. Gain Temperature Coefficient This is a measurement of the change in gain error with changes in temperature. It is expressed in ppm of FSR/°C. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5664R with code 512 loaded in the DAC register. It can be negative or positive. Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change and is measured from the 24th falling edge of SCLK. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Figure 41). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Reference Feedthrough Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated. It is expressed in dB. Noise Spectral Density This is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/√Hz. A plot of noise spectral density can be seen in Figure 47. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in μV. DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in μV/mA. Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-s. DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V, and VDD is varied by ±10%. Rev. C | Page 18 of 28 Data Sheet AD5624R/AD5644R/AD5664R Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa). Then execute a software LDAC and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s. DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent analog output change of another DAC. It is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa) using the command write to and update while monitoring the output of the victim channel that is at midscale. The energy of the glitch is expressed in nV-s. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. It is measured in dB. Rev. C | Page 19 of 28 AD5624R/AD5644R/AD5664R Data Sheet THEORY OF OPERATION DIGITAL-TO-ANALOG SECTION R The AD5624R/AD5644R/AD5664R DACs are fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Figure 51 shows a block diagram of the DAC architecture. R TO OUTPUT AMPLIFIER R VDD VREFIN OUTPUT AMPLIFIER (GAIN = +2) REF DAC REGISTER VOUT GND R 05856-032 RESISTOR STRING R 05856-033 Figure 51. DAC Architecture Because the input coding to the DAC is straight binary, the ideal output voltage when using an external reference is given by Figure 52. Resistor String INTERNAL REFERENCE D VOUT = VREFIN × N 2 The ideal output voltage when using the internal reference is given by D VOUT = 2 × V REFOUT × N 2 where: D is the decimal equivalent of the binary code that is loaded to the DAC register: 0 to 4095 for AD5624R (12 bit). 0 to 16,383 for AD5644R (14 bit). 0 to 65,535 for AD5664R (16 bit). The AD5624R/AD5644R/AD5664R on-chip reference is off at power-up and is enabled via a write to a control register. See the Internal Reference Setup section for details. The AD56x4R-3 has a 1.25 V, 5 ppm/°C reference giving a fullscale output of 2.5 V. The AD56x4R-5 has a 2.5 V, 5 ppm/°C reference giving a full-scale output of 5 V. The internal reference associated with each part is available at the VREFOUT pin. A buffer is required if the reference output is used to drive external loads. When using the internal reference, it is recommended that a 100 nF capacitor is placed between reference output and GND for reference stability. EXTERNAL REFERENCE N is the DAC resolution. RESISTOR STRING The resistor string is shown in Figure 52. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. OUTPUT AMPLIFIER The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It can drive a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 34 and Figure 35. The slew rate is 1.8 V/µs with a ¼ to ¾ full-scale settling time of 7 µs. The VREFIN pin on the AD56x4R-3 and AD56x4R-5 allows the use of an external reference if the application requires it. The default condition of the on-chip reference is off at power-up. All devices (AD56x4R-3 and the AD56x4R-5) can be operated from a single 2.7 V to 5.5 V supply. SERIAL INTERFACE The AD5624R/AD5644R/AD5664R have a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as with most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 24-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the AD5624R/AD5644R/AD5664R compatible with high speed DSPs. On the 24th falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, a change in DAC register contents and/or a change in the mode of operation. Rev. C | Page 20 of 28 Data Sheet AD5624R/AD5644R/AD5664R At this stage, the SYNC line can be kept low or be brought high. In either case, it must be brought high for a minimum of 15 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Table 8. Command Definition Because the SYNC buffer draws more current when VIN = 2 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation. As mentioned previously, it must, however, be brought high again just before the next write sequence. INPUT SHIFT REGISTER The input shift register is 24 bits wide (see Figure 53). The first two bits are don’t care bits. The next three are the command bits, C2 to C0 (see Table 8), followed by the 3-bit DAC address, A2 to A0 (see Table 9), and then the 16-, 14-, 12-bit data-word. The data-word comprises the 16-, 14-, 12-bit input code followed by 0, 2, or 4 don’t care bits, for the AD5664R, AD5644R, and AD5624R, respectively (see Figure 53, Figure 54, and Figure 55). These data bits are transferred to the DAC register on the 24th falling edge of SCLK. C2 0 0 0 C1 0 0 1 C0 0 1 0 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 Command Write to input register n Update DAC register n Write to input register n, update all (software LDAC) Write to and update DAC channel n Power down DAC (power-up) Reset LDAC register setup Internal reference setup (on/off ) Table 9. Address Command A2 0 0 0 0 1 A1 0 0 1 1 1 A0 0 1 0 1 1 Address (n) DAC A DAC B DAC C DAC D All DACs SYNC INTERRUPT In a normal write sequence, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is updated on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, then this acts as an interrupt to the write sequence. The input shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 56). DB0 (LSB) DB23 (MSB) X C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D5 D4 D3 D2 D4 D3 D2 D1 D0 D2 D1 D0 X X D6 D1 D0 05856-034 X DATA BITS COMMAND BITS ADDRESS BITS Figure 53. AD5664R Input Shift Register Contents DB23 (MSB) X DB0 (LSB) C2 C1 C0 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 X X 05856-035 X DATA BITS COMMAND BITS ADDRESS BITS Figure 54. AD5644R Input Shift Register Contents DB23 (MSB) X DB0 (LSB) C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 DATA BITS COMMAND BITS X X 05856-036 X ADDRESS BITS Figure 55. AD5624R Input Shift Register Contents SCLK SYNC DB23 DB0 DB23 INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 24TH FALLING EDGE DB0 VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 24TH FALLING EDGE Figure 56. SYNC Interrupt Facility Rev. C | Page 21 of 28 05856-037 DIN AD5624R/AD5644R/AD5664R Data Sheet The AD5624R/AD5644R/AD5664R family contains a power-on reset circuit that controls the output voltage during power-up. The output of the AD5624R/AD5644R/AD5664R DACs powers up to 0 V and the output remains there until a valid write sequence is made to the DACs. This is useful in applications where it is important to know the state of the output of the DACs while they are in the process of powering up. SOFTWARE RESET Table 10 shows how the state of the bit corresponds to the software reset modes of operation of the devices. Table 12 shows the contents of the input shift register during the software reset mode of operation. Table 10. Software Reset Modes for the AD5624R/AD5644R/AD5664R Registers Reset to 0 DAC register Input shift register DAC register Input shift register LDAC register Power-down register Internal reference setup register 1 (Power-On Reset) Table 11. Modes of Operation for the AD5624R/AD5644R/ AD5664R DB5 0 0 1 1 The AD5624R/AD5644R/AD5664R contain a software reset function. Command 101 is reserved for the software reset function (see Table 8). The software reset command contains two reset modes that are software programmable by setting bit DB0 in the control register. DB0 0 By executing the same Command 100, any combination of DACs can be powered up by setting the bits (DB5 and DB4) to normal operation mode. To select which combination of DAC channels to power-up, set the corresponding four bits (DB3, DB2, DB1, and DB0) to 1. See Table 13 for contents of the input shift register during power-down/power-up operation. DB4 0 1 0 1 Operating Mode Normal operation Power-down mode: 1 kΩ to GND Power-down mode: 100 kΩ to GND Power-down mode: three-state When Bit DB5 and Bit DB4 are set to 0, the part works normally with its normal power consumption of 450 µA at 5 V. However, for the three power-down modes, the supply current falls to 480 nA at 5 V (200 nA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This allows the output impedance of the part to be known while the part is in power-down mode. The outputs can either be connected internally to GND through a 1 kΩ resistor, or left open-circuited (three-state) as shown in Figure 57. RESISTOR STRING DAC AMPLIFIER POWER-DOWN CIRCUITRY POWER-DOWN MODES The AD5624R/AD5644R/AD5664R contain four separate modes of operation. Command 100 is reserved for the power-down function (see Table 8). These modes are software programmable by setting two bits (DB5 and DB4) in the control register. Table 11 shows how the state of the bits corresponds to the mode of operation of the device. All DACs (DAC D to DAC A) can be powered down to the selected mode by setting the corresponding four bits (DB3, DB2, DB1, and DB0) to 1. VOUT RESISTOR NETWORK 05856-038 POWER-ON RESET Figure 57. Output Stage During Power-Down The bias generator, the output amplifier, the resistor string, and other associated linear circuitry are shutdown when power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 4 µs for VDD = 5 V and for VDD = 3 V (see Figure 40). Table 12. 24-Bit Input Shift Register Contents for Software Reset Command DB23 to DB22 (MSB) x Don’t care DB21 DB20 DB19 1 0 1 Command bits (C2 to C0) DB18 DB17 DB16 x x x Address bits (A2 to A0) DB15 to DB1 x Don’t care DB0 (LSB) 1/0 Determines software reset mode Table 13. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation for the AD5624R/AD5644R/AD5664R DB23 to DB22 (MSB) x Don’t care DB21 1 DB20 0 DB19 0 Command bits (C2 to C0) DB18 x DB17 x DB16 x Address bits (A2 to A0) Don’t care DB15 to DB6 x Don’t care Rev. C | Page 22 of 28 DB5 PD1 DB4 PD0 Power-down mode DB3 DAC D DB2 DAC C DB1 DAC B DB0 (LSB) DAC A Power-down/power-up channel selection, set bit to 1 to select channel Data Sheet AD5624R/AD5644R/AD5664R LDAC FUNCTION The AD5624R/AD5644R/AD5664R DACs have doublebuffered interfaces consisting of two banks of registers: input registers and DAC registers. The input registers are connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC registers contain the digital code used by the resistor strings. The double-buffered interface is useful if the user requires simultaneous updating of all DAC outputs. The user can write to three of the input registers individually and then write to the remaining input register, updating all DAC registers simultaneously. Command 010 is reserved for this software LDAC. Access to the DAC registers is controlled by the LDAC function. The LDAC register contains two modes of operation for each DAC channel. The DAC channels are selected by setting the bits of the 4-bit LDAC register (DB3, DB2, DB1, and DB0). Command 110 is reserved for setting up the LDAC register. When the LDAC bit register is set low, the corresponding DAC registers are latched and the input registers can change state without affecting the contents of the DAC registers. When the LDAC bit register is set high, however, the DAC registers become transparent and the contents of the input registers are transferred to them on the falling edge of the 24th SCLK pulse. This is equivalent to having an LDAC hardware pin tied permanently low for the selected DAC channel, that is, synchronous update mode. See Table 14 for the LDAC register mode of operation. See Table 16 for contents of the input shift register during the LDAC register setup command. This flexibility is useful in applications where the user wants to update select channels simultaneously, while the rest of the channels update synchronously. Table 14. LDAC Register Mode of Operation LDAC Bits (DB3 to DB0) 0 LDAC Mode of Operation Normal operation (default), DAC register update is controlled by write command. The DAC registers are updated after new data is read in on the falling edge of the 24th SCLK pulse. 1 INTERNAL REFERENCE SETUP The on-chip reference is off at power-up by default. This reference can be turned on or off by setting a software programmable bit, DB0, in the control register. Table 15 shows how the state of the bit corresponds to the mode of operation. Command 111 is reserved for setting up the internal reference (see Table 8). Table 16 shows how the state of the bits in the input shift register corresponds to the mode of operation of the device during internal reference setup. Table 15. Reference Setup Register Internal Reference Setup Register (DB0) 0 1 Action Reference off (default) Reference on Table 16. 24-Bit Input Shift Register Contents for LDAC Setup Command for the AD5624R/AD5644R/AD5664R DB23 to DB22 (MSB) x Don’t care DB21 1 DB20 DB19 1 0 Command bits (C2 to C0) DB18 x DB17 DB16 x x Address bits (A2 to A0); don’t care DB15 to DB4 x Don’t care DB3 DB2 DB1 DB0 (LSB) DAC D DAC C DAC B DAC A Set bit to 0 or 1 for required mode of operation on respective channel Table 17. 24-Bit Input Shift Register Contents for Internal Reference Setup Command DB23 to DB22 (MSB) x Don’t care DB21 DB20 DB19 1 1 1 Command bits (C2 to C0) DB18 DB17 DB16 x x x Address bits (A2 to A0) Rev. C | Page 23 of 28 DB15 to DB1 x Don’t care DB0 (LSB) 1/0 Reference setup register AD5624R/AD5644R/AD5664R Data Sheet MICROPROCESSOR INTERFACING AD5624R/AD5644R/AD5664R to 80C51/80L51 Interface AD5624R/AD5644R/AD5664R to Blackfin ADSP-BF53x Interface Figure 60 shows a serial interface between the AD5624R/ AD5644R/AD5664R and the 80C51/80L51 microcontroller. The setup for the interface is that the TxD of the 80C51/80L51 drives SCLK of the AD5624R/AD5644R/AD5664R, while RxD drives the serial data line of the part. The SYNC signal is derived from a bitprogrammable pin on the port. In this case, port line P3.3 is used. When data is transmitted to the AD5624R/AD5644R/AD5664R, P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes only; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in LSB first format. The AD5624R/AD5644R/AD5664R must receive data with the MSB first. The 80C51/80L51 transmit routine should take this into account. SYNC DTOPRI DIN TSCLK0 SCLK 1ADDITIONAL PINS OMITTED FOR CLARITY. 80C51/80L511 Figure 58. Blackfin ADSP-BF53x Interface to AD5624R/AD5644R/AD5664R AD5624R/AD5644R/AD5664R to 68HC11/68L11 Interface Figure 59 shows a serial interface between the AD5624R/ AD5644R/AD5664R and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5624R/ AD5644R/AD5664R, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are that the 68HC11/68L11 is configured with its CPOL bit as 0 and its CPHA bit as 1. When data is transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as described previously, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/ 68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5624R/AD5644R/AD5664R, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC; PC7 is taken high at the end of this procedure. SYNC SCK SCLK MOSI DIN 1ADDITIONAL PINS OMITTED FOR CLARITY. SYNC TxD SCLK RxD DIN Figure 60. 80C51/80L51 Interface to AD5624R/AD5644R/AD5664R AD5624R/AD5644R/AD5664R to MICROWIRE Interface Figure 61 shows an interface between the AD5624R/AD5644R/ AD5664R and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5624R/AD5644R/AD5664R on the rising edge of the SK. AD5624R/ AD5644R/ AD5664R1 PC7 P3.3 1ADDITIONAL PINS OMITTED FOR CLARITY. 05856-040 68HC11/68L111 AD5624R/ AD5644R/ AD5664R1 05856-041 TFS0 AD5624R/ AD5644R/ AD5664R1 05856-039 ADSP-BF53x1 Figure 59. 68HC11/68L11 Interface to AD5624R/AD5644R/AD5664R Rev. C | Page 24 of 28 MICROWIRE1 AD5624R/ AD5644R/ AD5664R1 CS SYNC SK SCLK SO DIN 1ADDITIONAL PINS OMITTED FOR CLARITY. 05856-042 Figure 58 shows a serial interface between the AD5624R/ AD5644R/AD5664R and the Blackfin® ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5624R/AD5644R/AD5664R, the setup for the interface is that the DT0PRI drives the DIN pin of the AD5624R/AD5644R/AD5664R, while TSCLK0 drives the SCLK of the part. The SYNC is driven from TFS0. Figure 61. MICROWIRE Interface to AD5624R/AD5644R/AD5664R Data Sheet AD5624R/AD5644R/AD5664R APPLICATIONS INFORMATION R2 = 10kΩ USING A REFERENCE AS A POWER SUPPLY FOR THE AD5624R/AD5644R/AD5664R +5V 450 µA + (5 V/5 kΩ) = 1.45 mA The load regulation of the REF195 is typically 2 ppm/mA, resulting in a 2.9 ppm (14.5 µV) error for the 1.45 mA current drawn from it. This corresponds to a 0.191 LSB error. 15V SYNC SCLK DIN VDD AD5624R/ AD5644R/ AD5664R VOUT = 0V TO 5V 10µF 0.1µF ±5V VOUT AD5624R/ AD5644R/ AD5664R –5V 3-WIRE SERIAL INTERFACE Figure 63. Bipolar Operation with the AD5624R/AD5644R/AD5664R USING AD5624R/AD5644R/AD5664R WITH A GALVANICALLY ISOLATED INTERFACE In process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous commonmode voltages that might occur in the area where the DAC is functioning. Isocouplers provide isolation in excess of 3 kV. The AD5624R/AD5644R/AD5664R use a 3-wire serial logic interface, so the ADuM130x 3-channel digital isolator provides the required isolation (see Figure 64). The power supply to the part also needs to be isolated, which is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5624R/AD5644R/AD5664R. 5V REGULATOR 05856-043 3-WIRE SERIAL INTERFACE 5V AD820/ OP295 VDD 05856-044 Because the supply current required by the AD5624R/AD5644R/ AD5664R is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the part (see Figure 62). This is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 V or 3 V, for example, 15 V. The voltage reference outputs a steady supply voltage for the AD5624R/AD5644R/AD5664R (see Figure 60). If the low dropout REF195 is used, it must supply 450 µA of current to the AD5624R/AD5644R/AD5664R with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. The total current required (with a 5 kΩ load on the DAC output) is REF195 R1 = 10kΩ +5V 10µF POWER 0.1µF Figure 62. REF195 as Power Supply to the AD5624R/AD5644R/AD5664R BIPOLAR OPERATION USING THE AD5624R/AD5644R/AD5664R SCLK VDD VOA SCLK ADuM1300 SDI DATA VIB VIC VOB VOC VOUT SYNC DIN AD5624R/ AD5644R/ AD5664R GND 05856-045 The AD5624R/AD5644R/AD5664R have been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 63. The circuit gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. The output voltage for any input code can be calculated as follows: VIA Figure 64. AD5624R/AD5644R/AD5664R with a Galvanically Isolated Interface D R1 + R2 R2 VOUT = VDD × × − VDD × R1 65 , 536 R1 where D represents the input code in decimal (0 to 65,536). With VDD = 5 V, R1 = R2 = 10 kΩ, 10 × D VOUT = −5 V 65,536 This is an output voltage range of ±5 V, with 0x0000 corresponding to a −5 V output, and 0xFFFF corresponding to a +5 V output. Rev. C | Page 25 of 28 AD5624R/AD5644R/AD5664R Data Sheet POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5624R/ AD5644R/AD5664R should have separate analog and digital sections, each having its own area of the board. If the AD5624R/ AD5644R/AD5664R are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5624R/AD5644R/AD5664R. The power supply to the AD5624R/AD5644R/AD5664R should be bypassed with 10 µF and 0.1 µF capacitors. The capacitors should be located as close as possible to the device, with the 0.1 µF capacitor ideally right up against the device. The 10 µF capacitor is the tantalum bead type. It is important that the 0.1 µF capacitor have low effective series resistance (ESR) and effective series inductance (ESI), for example, common ceramic types of capacitors. This 0.1 µF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. Rev. C | Page 26 of 28 Data Sheet AD5624R/AD5644R/AD5664R OUTLINE DIMENSIONS 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 PIN 1 INDEX AREA 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 BOTTOM VIEW SEATING PLANE 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.30 0.25 0.20 PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 02-05-2013-C 0.80 0.75 0.70 0.20 MIN 1 5 TOP VIEW 0.20 REF Figure 65. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.23 0.13 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 66. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters Rev. C | Page 27 of 28 0.70 0.55 0.40 091709-A 0.15 0.05 COPLANARITY 0.10 AD5624R/AD5644R/AD5664R Data Sheet 1.705 1.665 1.625 BOTTOM VIEW (BALL SIDE UP) 3 2 1 A BALL A1 IDENTIFIER 2.285 2.245 2.205 1.50 REF B C D 0.50 BSC TOP VIEW (BALL SIDE DOWN) 1.00 REF 0.380 0.355 0.330 END VIEW COPLANARITY 0.05 SEATING PLANE 0.270 0.240 0.210 0.340 0.320 0.300 08-31-2012-A 0.650 0.595 0.540 Figure 67. 12-Ball Wafer Level Chip Scale Package [WLCSP] (CB-12-9) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5624RBCPZ-3R2 AD5624RBCPZ-3REEL7 AD5624RBCPZ-5R2 AD5624RBCPZ-5REEL7 AD5624RBRMZ-3 AD5624RBRMZ-3REEL7 AD5624RBRMZ-5 AD5624RBRMZ-5REEL7 AD5644RBRMZ-3 AD5644RBRMZ-3REEL7 AD5644RBRMZ-5 AD5644RBRMZ-5REEL7 AD5664RBCBZ-3RL7 AD5664RBCPZ-3R2 AD5664RBCPZ-3REEL7 AD5664RBRMZ-3 AD5664RBRMZ-3REEL7 AD5664RBRMZ-5 AD5664RBRMZ-5REEL7 EVAL-AD5664REBZ 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Accuracy ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±4 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL ±16 LSB INL Internal Reference 1.25 V 1.25 V 2.5 V 2.5 V 1.25 V 1.25 V 2.5 V 2.5 V 1.25 V 1.25 V 2.5 V 2.5 V 1.25 V 1.25 V 1.25 V 1.25 V 1.25 V 2.5 V 2.5 V Z = RoHS Compliant Part. ©2006–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05856-0-4/13(C) Rev. C | Page 28 of 28 Package Description 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 12 Ball WLCSP 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board Package Option CP-10-9 CP-10-9 CP-10-9 CP-10-9 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 CB-12-9 CP-10-9 CP-10-9 RM-10 RM-10 RM-10 RM-10 Branding D7L D7L DBZ DBZ D7L D7L D7V D7V D7E D7E D7D D7D D73 D73 D73 D73 D75 D75