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RT9624E
Single Phase Synchronous Rectified Buck MOSFET Driver
General Description
Features
The RT9624E is a high frequency, synchronous rectified,
single phase MOSFET driver designed for normal MOSFET
driving applications and high performance CPU VR driving
capabilities.
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Drive Two N-MOSFETs
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Shoot Through Protection
Embedded Bootstrap Diode
Support High Switching Frequency
Fast Output Rising Time
Tri-State PWM Input for Output Shutdown
Enable Control
8-Lead WDFN Package
RoHS Compliant and Halogen Free
The RT9624E can be supplied from 4.5V to 13.2V. The
applicable power stage VIN range is from 5V to 24V. The
RT9624E also builds in an internal power switch to replace
external bootstrap diode.
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The RT9624E can support switching frequency efficiently
up to 500kHz. The RT9624E has both UGATE and LGATE
driving circuits for synchronous rectified DC/DC converter
applications. The shoot through protection mechanism is
designed to prevent shoot through between high-side and
low-side power MOSFETs. The RT9624E has tri-state
PWM input with shutdown and EN input shutdown
functions, which can force driver to output low UGATE
and LGATE signals.
Applications
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Core Voltage Supplies for Desktop, Motherboard CPU
High Frequency Low Profile DC/DC Converters
High Current Low Voltage DC/DC Converters
Core Voltage Supplies for GFX Card
Marking Information
4Q= : Product Code
The RT9624E is available in a small footprint WDFN-8L
3x3 package.
YMDNN : Date Code
4Q=YM
DNN
Simplified Application Circuit
RT9624E
12V
R1
VCC
BOOT
UGATE
EN
PWM
R3
Q1
L1
VOUT
PHASE
R4
LGATE
GND
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS9624E-00 January 2014
C6
R5
Q2
+
PWM
Controller
C5
CBOOT
C1
Chip Enable
VIN
R2
C3
C4
C2
is a registered trademark of Richtek Technology Corporation.
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1
RT9624E
Ordering Information
Pin Configurations
(TOP VIEW)
Package Type
QW : WDFN-8L 3x3 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
PWM
GND
EN
VCC
8
1
3
GND
RT9624E
6
4
9
5
2
7
BOOT
UGATE
PHASE
LGATE
WDFN-8L 3x3
Richtek products are :
`
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS9624E-00 January 2014
RT9624E
Function Pin Description
Pin No.
1
Pin Name
PWM
2, 9 (Exposed Pad) GND
3
EN
4
VCC
5
LGATE
6
PHASE
7
UGATE
8
BOOT
Pin Function
PWM Signal Input. Connect this pin to the PWM output of the controller.
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
Enable Control Input (Active High). When this pin is low, both UGATE and
LGATE are driven to low.
Supply Voltage Input.
Low-Side Gate Driver Output. Connect this pin to the Gate of low-side power
N-MOSFET.
Connect this pin to the Source of the high-side N-MOSFET and the Drain of the
low side N-MOSFET.
High-Side Gate Drive Output. Connect this pin to the Gate of high-side power
N-MOSFET.
Bootstrap Supply for High-Side Gate Drive.
Function Block Diagram
Internal
VDD
PWM
EN
VCC
Enable
Detect
POR
Bootstrap
Control
BOOT
Tri-State
Detect
Shoot-Through
Protection
UGATE
Turn Off
Detection
PHASE
VCC
Shoot-Through
Protection
LGATE
GND
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS9624E-00 January 2014
is a registered trademark of Richtek Technology Corporation.
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3
RT9624E
Operation
POR (Power On Reset)
Bootstrap Control
The POR block detects the voltage the VCC pin. When
the VCC pin voltage is higher than POR rising threshold,
the POR block output is high. The POR output is low
when VCC is less than POR rising threshold. When the
POR block output is high, UGATE and LGATE can be
controlled by PWM input voltage. If the POR block output
is low, both UGATE and LGATE will be pulled to low.
The Bootstrap control block controls the integrated
bootstrap switch. When LGATE is high (low-side MOSFET
is turned on), the bootstrap switch is turned on to charge
the bootstrap capacitor connected to BOOT pin. When
LGATE is low (low-side MOSFET is turned off), the
bootstrap switch is turned off to disconnect VCC pin and
BOOT pin.
Enable Detect
Turn-Off Detection
When EN pin input voltage is higher/lower than EN rising
threshold, MOSFET driver is enabled/disabled. When the
EN input and POR output are high, UGATE and LGATE
can be controlled by PWM input voltage. When EN input
is low, both UGATE and LGATE are pulled to low.
The turn-off detection block detects whether high-side
MOSFET is turned off by monitoring the PHASE pin
voltage. To avoid shoot through between high-side and
low-side MOSFETs, low-side MOSFET can be turned on
only after high-side MOSFET is effectively turned off.
Tri-State Detect
Shoot-Through Protection
When both POR block output and EN pin voltages are
high, UGATE and LGATE can be controlled by PWM input.
There are three PWM input modes, which are high, low,
and shutdown state. If PWM input is within the shutdown
window, both UGATE and LGATE output are low. When
PWM input is higher than its rising threshold, UGATE is
high and LGATE is low. When PWM input is lower than
its falling threshold, UGATE is low and LGATE is high.
The shoot-through protection block implements the dead
time when both high-side and low-side MOSFETs are
turned off. With shoot-through protection block, high-side
and low-side MOSFET are never turned on simultaneously.
Thus, shoot through between high-side and low-side
MOSFETs is prevented.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS9624E-00 January 2014
RT9624E
Absolute Maximum Ratings
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(Note 1)
Supply Voltage, VCC -------------------------------------------------------------------------------- −0.3V to 15V
BOOT to PHASE ------------------------------------------------------------------------------------- −0.3V to 15V
PHASE to GND
DC -------------------------------------------------------------------------------------------------------- −0.3V to 30V
< 20ns --------------------------------------------------------------------------------------------------- −10V to 35V
LGATE to GND
DC -------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)
< 20ns --------------------------------------------------------------------------------------------------- −2V to (VCC + 0.3V)
UGATE to GND
DC -------------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V)
< 20ns --------------------------------------------------------------------------------------------------- (VPHASE − 2V) to (VBOOT + 0.3V)
EN, PWM to GND ------------------------------------------------------------------------------------ −0.3V to 7V
Power Dissipation, PD @ TA = 25°C
WDFN-8L 3x3 ----------------------------------------------------------------------------------------- 3.22W
Package Thermal Resistance (Note 2)
WDFN-8L 3x3, θJA ------------------------------------------------------------------------------------ 31°C/W
WDFN-8L 3x3, θJC ------------------------------------------------------------------------------------ 8°C/W
Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------- 260°C
Junction Temperature -------------------------------------------------------------------------------- 150°C
Storage Temperature Range ----------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) ------------------------------------------------------------------------- 2kV
Recommended Operating Conditions
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(Note 4)
Supply Voltage, VCC -------------------------------------------------------------------------------- 4.5V to 13.2V
Input Voltage, (VIN + VCC) ------------------------------------------------------------------------- < 35V
Junction Temperature Range ----------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ----------------------------------------------------------------------- −40°C to 85°C
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS9624E-00 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT9624E
Electrical Characteristics
(VCC = 12V, TA = 25°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
4.5
--
13.2
V
Power Supply
Power Supply Voltage
VCC
Power Supply Current
IVCC
VBOOT = 12V, PWM Input Floating
--
120
--
μA
POR Rising Threshold
VPOR_r
VCC Rising
--
4
4.4
V
POR Falling Threshold
VPOR_ f
VCC Falling
3
3.5
--
V
Power On Reset (POR)
EN Input
EN Rising Threshold
VENH
--
1.3
1.6
V
EN Falling Threshold
VENL
0.7
1
--
V
PWM Input
Maximum Input Current
IPWM
PWM = 0V or 5V
--
160
--
μA
PWM Floating Voltage
VPWM_fl
PWM = Open
--
1.8
--
V
PWM Rising Threshold
VPWM_rth
2.3
2.8
3.2
V
PWM Falling Threshold
VPWM_fth
0.7
1.1
1.4
V
Timing
UGATE Rising Time
tUGATEr
3nF Load
--
25
--
ns
UGATE Falling Time
tUGATEf
3nF Load
--
12
--
ns
LGATE Rising Time
tLGATEr
3nF Load
--
24
--
ns
LGATE Falling Time
tLGATEf
3nF Load
--
10
--
ns
tUGATEpdh
--
60
--
tUGATEpdl
VBOOT − VPHASE = 12V
See Timing Diagram
--
22
--
tLGATEpdh
See Timing Diagram
--
30
--
tLGATEpdl
See Timing Diagram
--
8
--
UGATE Drive Source
RUGATE_sr
VBOOT − VPHASE = 12V, ISource = 100mA
--
1.7
--
Ω
UGATE Drive Sink
RUGATE_sk
VBOOT − VPHASE = 12V, ISink = 100mA
--
1.4
--
Ω
LGATE Drive Source
RLGATE_sr
ISource = 100mA
--
1.6
--
Ω
LGATE Drive Sink
RLGATE_sk
ISink = 100mA
--
1.1
--
Ω
UGATE Propagation Delay
LGATE Propagation Delay
ns
ns
Output
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS9624E-00 January 2014
RT9624E
Typical Application Circuit
12V
VIN
12V
RT9624E
R1
2.2
R2
1
8
BOOT
4 VCC
C1
1µF
Enable
3
1
EN
PWM
PHASE
7
Q1
6
5
LGATE
GND
2, 9 (Exposed Pad)
C6
10µF
x4
C5
1000µF
x3
L1
1µH
VOUT
R4
0
+
PWM
Controller
UGATE
CBOOT
1µF R3
2.2
R5
2.2
Q2
C3
2200µF
x2
C2
3.3nF
C4
10µF
x2
Timing Diagram
PWM
tLGATEpdl
LGATE
90%
tUGATEpdl
1.5V
1.5V
1.5V
90%
1.5V
UGATE
tUGATEpdh
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS9624E-00 January 2014
tLGATEpdh
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RT9624E
Typical Operating Characteristics
Drive Enable
Drive Disable
UGATE
(50V/Div)
UGATE
(50V/Div)
PHASE
(20V/Div)
PHASE
(20V/Div)
LGATE
(20V/Div)
LGATE
(20V/Div)
EN
(10V/Div)
EN
(10V/Div)
VIN = 12V, No Load
VIN = 12V, No Load
Time (1μs/Div)
Time (1μs/Div)
PWM Rising Edge
PWM Falling Edge
PWM
(10V/Div)
PWM
(10V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
LGATE
(10V/Div)
PHASE
(10V/Div)
PHASE
(10V/Div)
Time (20ns/Div)
Time (20ns/Div)
Dead Time
Dead Time
UGATE
UGATE
PHASE
PHASE
LGATE
LGATE
(5V/Div)
(5V/Div)
Full Load
Full Load
Time (20ns/Div)
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Time (20ns/Div)
is a registered trademark of Richtek Technology Corporation.
DS9624E-00 January 2014
RT9624E
Dead Time
Dead Time
UGATE
UGATE
PHASE
PHASE
LGATE
(5V/Div)
LGATE
(5V/Div)
No Load
Time (20ns/Div)
No Load
Time (20ns/Div)
Short Pulse
UGATE
LGATE
PHASE
(5V/Div)
UGATE − PHASE
No Load
Time (20ns/Div)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS9624E-00 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
9
RT9624E
Application Information
The RT9624E is a high frequency, synchronous rectified,
single phase dual MOSFET driver containing Richtek's
advanced MOSFET driver technologies. The RT9624E is
designed to be able to adapt from normal MOSFET driving
applications to high performance CPU VR driving
capabilities.
Supply Voltage and Power On Reset
The RT9624E can be utilized under both VCC = 5V or VCC
= 12V applications which may happen in different fields of
electronics application circuits. In terms of efficiency,
higher VCC equals higher driving voltage of UGATE/LGATE
which may result in higher switching loss and lower
conduction loss of power MOSFETs. The choice of VCC =
12V or VCC = 5V can be a tradeoff to optimize system
efficiency.
The RT9624E is designed to drive both high-side and lowside N-MOSFET through external input PWM control
signal. It has power on protection function which held
UGATE and LGATE low before the VCC voltage rises to
higher than rising threshold voltage.
Enable and Disable
The RT9624E includes an EN pin for sequence control.
When the EN pin rises above the VENH trip point, the
RT9624E begins a new initialization and follows the PWM
command to control the UGATE and LGATE. When the
EN pin falls below the VENL trip point, the RT9624E shuts
down and keeps UGATE and LGATE low.
are disabled and both MOSFET gates are pulled and held
low. If the PWM signal is left floating, the pin will be kept
around 1.8V by the internal divider and provide the PWM
controller with a recognizable level.
Internal Bootstrap Power Switch
The RT9624E builds in an internal bootstrap power switch
to replace external bootstrap diode, and this can facilitate
PCB design and reduce total BOM cost of the system.
Hence, no external bootstrap diode is required in real
applications.
Non-overlap Control
To prevent the overlap of the gate drivers during the UGATE
pull low and the LGATE pull high, the non-overlap circuit
monitors the voltages at the PHASE node and high-side
gate drive (UGATE-PHASE). When the PWM input signal
goes low, UGATE begins to pull low (after propagation
delay). Before LGATE is pulled high, the non-overlap
protection circuit ensures that the monitored voltages have
gone below 1.1V. Once the monitored voltages fall below
1.1V, LGATE begins to turn high. By waiting for the
voltages of the PHASE pin and high-side gate driver to fall
below 1.1V, the non-overlap protection circuit ensures that
UGATE is low before LGATE pulls high.
Also to prevent the overlap of the gate drivers during
LGATE pull low and UGATE pull high, the non-overlap
circuit monitors the LGATE voltage. When LGATE goes
below 1.1V, UGATE goes high after propagation delay.
Tri-state PWM Input
Driving Power MOSFETs
After the initialization, the PWM signal takes the control.
The rising PWM signal first forces the LGATE signal to
turn low then UGATE signal is allowed to go high just
after a non-overlapping time to avoid shoot through current.
The falling of PWM signal first forces UGATE to go low.
When UGATE and PHASE signal reach a predetermined
low level, LGATE signal is allowed to turn high.
The DC input impedance of the power MOSFET is
extremely high. When Vgs1 or Vgs2 is at 12V or 5V, the
gate draws the current only for few nano-amperes. Thus
once the gate has been driven up to “ ON” level, the
current could be negligible.
The PWM signal is acted as “High” if the signal is above
the rising threshold and acted as “Low” if the signal is
below the falling threshold. When PWM signal level enters
and remains within the shutdown window, the output drivers
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10
However, the capacitance at the gate to source terminal
should be considered. It requires relatively large currents
to drive the gate up and down 12V (or 5V) rapidly. It is
also required to switch drain current on and off with the
required speed. The required gate drive currents are
calculated as follows.
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DS9624E-00 January 2014
RT9624E
D1
d1
s1
VPHASE
VIN
Igd1 = Cgd1
L
VOUT
Cgs1
Cgd1
Cgd2
Igs1
Igd1
Ig1
g1
D2
Igs2
s2
GND
Vg1
VPHASE +12V
VIN + 12
dV
= Cgd2
dt
tr2
12V
Igs2 =
t
1660 x 10-12 x 12
14 x 10-9
2200 x 10-12 x 12
30 x 10-9
Figure 1. Equivalent Circuit and Waveforms (VCC = 12V)
from equation. (3) and (4)
In Figure 1, the current Ig1 and Ig2 are required to move the
Igd1 =
gate up to 12V. The operation consists of charging Cgd1,
Cgd2 , Cgs1 and Cgs2. Cgs1 and Cgs2 are the capacitors from
gate to source of the high-side and the low-side power
MOSFETs, respectively. In general data sheets, the Cgs1
and C gs2 are referred as “Ciss” which are the input
capacitors. Cgd1 and Cgd2 are the capacitors from gate to
drain of the high-side and the low-side power MOSFETs,
respectively and referred to the data sheets as “Crss” the
reverse transfer capacitance. For example, tr1 and tr2 are
the rising time of the high-side and the low-side power
MOSFETs respectively, the required current Igs1 and Igs2,
are shown as below :
Igs1 = Cgs1
Igs2 = Cgs1
dVg1
dt
dVg2
=
=
Cgs1 x 12
(1)
tr1
Cgs1 x 12
(2)
dt
tr2
Before driving the gate of the high-side MOSFET up to
12V, the low-side MOSFET has to be off; and the highside MOSFET will be turned off before the low-side is
turned on. From Figure 1, the body diode “D2” will be
turned on before high-side MOSFETs turn on.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS9624E-00 January 2014
(4)
It is helpful to calculate these currents in a typical case.
Assume a synchronous rectified Buck converter, input
voltage VIN = 12V, Vgs1 = 12V, Vgs2 = 12V. The high-side
MOSFET is PHB83N03LT whose C iss = 1660pF,
Crss = 380pF, and tr = 14ns. The low-side MOSFET is
PHB95N03LT whose Ciss = 2200pF, Crss = 500pF and
tr = 30ns, from the equation (1) and (2) we can obtain
Igs1 =
t
Vg2
Before the low-side MOSFET is turned on, the Cgd2 have
Igd2 = Cgd2
Ig2 Igd2
Cgs2
(3)
been charged to VIN. Thus, as Cgd2 reverses its polarity
and g2 is charged up to 12V, the required current is
d2
g2
dV
12
= Cgd1
dt
tr1
Igd2 =
380 x 10-12 x 12
14 x 10-9
= 1.428
= 0.88
(A)
(6)
= 0.326 (A)
500 x 10-12 x (12+12 )
30 x 10-9
(5)
(A)
(7)
= 0.4 (A)
(8)
the total current required from the gate driving source can
be calculated as the following equations.
Ig1 = Igs1 + Igd1 = (1.428 + 0.326 ) = 1.754 (A)
Ig2 = Igs2 + Igd2 = ( 0.88 + 0.4 ) = 1.28 (A)
(9)
(10)
By a similar calculation, we can also get the sink current
required from the turned off MOSFET.
Select the Bootstrap Capacitor
Figure 2 shows part of the bootstrap circuit of the
RT9624E. The VCB (the voltage difference between BOOT
and PHASE on RT9624E) provides a voltage to the gate
of the high-side power MOSFET. This supply needs to be
ensured that the MOSFET can be driven. For this, the
capacitance CBOOT has to be selected properly. It is
determined by the following constraints.
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11
RT9624E
Figure 4 shows the power dissipation of the RT9624E as
a function of frequency and load capacitance when VCC =
VIN
BOOT
UGATE
PHASE
CBOOT
12V. The value of CU and CL are the same and the frequency
is varied from 100kHz to 1MHz.
+
VCB
-
Power Dissipation vs. Frequency
1000
VCC
GND
Figure 2. Part of Bootstrap Circuit of RT9624E
In practice, a low value capacitor CBOOT will lead to the
over charging that could damage the IC. Therefore, to
minimize the risk of overcharging and to reduce the ripple
on VCB, the bootstrap capacitor should not be smaller than
0.1μF, and the larger the better. In general design, using
1μF can provide better performance. At least one low-ESR
capacitor should be used to provide good local de-coupling.
It is recommended to adopt a ceramic or tantalum
capacitor.
Power Dissipation
To prevent driving the IC beyond the maximum
recommended operating junction temperature of 125°C,
it is necessary to calculate the power dissipation
appropriately. This dissipation is a function of switching
frequency and total gate charge of the selected MOSFET.
Figure 3 shows the power dissipation test circuit. CL and
C U are the UGATE and LGATE load capacitors,
respectively. The bootstrap capacitor value is 1μF.
CBOOT
1µF
12V
BOOT
10
12V
VCC
2N7002
UGATE
1µF
CU
3nF
RT9624E
PHASE
Enable
PWM
EN
LGATE
PWN
GND
20
Figure 3. Power Dissipation Test Circuit
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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12
800
CU = CL = 3nF
700
600
CU = CL = 2nF
500
400
300
CU = CL = 1nF
200
100
VCC = 12V
0
0
200
400
600
800
1000
Frequency (kHz)
Figure 4. Power Dissipation vs. Frequency
The operating junction temperature can be calculated from
the power dissipation curves (Figure 4). Assume VCC =
12V, operating frequency is 200kHz and CU = CL = 1nF
which emulate the input capacitances of the high-side and
low-side power MOSFETs. From Figure 4, the power
dissipation is 100mW. Thus, for example, the package
thermal resistance θJA is 120°C/W. The operating junction
temperature is then calculated as :
TJ = (120°C/W x 100mW) + 25°C = 37°C
(11)
where the ambient temperature is 25°C.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
2N7002
CL
3nF
Power Dissipation (mW)
900
LGATE
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
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DS9624E-00 January 2014
RT9624E
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WDFN-8L 3x3 package, the thermal resistance, θJA, is
31°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formulas :
P D(MAX) = (125°C − 25°C) / (31°C/W) = 3.22W for
WDFN-8L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 5 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Four-Layer PCB
3.0
Figure 6 shows the schematic circuit of a synchronous
buck converter to implement the RT9624E. The converter
operates from 5V to 12V of input Voltage.
For the PCB layout, it should be very careful. The power
circuit section is the most critical one. If not configured
properly, it will generate a large amount of EMI. The location
of Q1, Q2, L1 should be very close.
Next, the trace from UGATE, and LGATE should also be
short to decrease the noise of the driver output signals.
PHASE signals from the junction of the power MOSFET,
carrying the large gate drive current pulses, should be as
heavy as the gate drive trace. The bypass capacitor C1
should be connected to GND directly. Furthermore, the
bootstrap capacitors (CBOOT) should always be placed as
close to the pins of the IC as possible.
VIN
12V
2.5
L2
12V
2.0
+
C5
1.5
C6
R1
BOOT
VCC
CBOOT
1.0
C1
Q1
L1
VCORE
0.5
PHB83N03LT
+
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
UGATE
PHASE
C3
Q2
PHB95N03LT
LGATE
RT9624E
Maximum Power Dissipation (W)1
3.5
Layout Consideration
PWM
EN
PWM
EN
GND
Figure 5. Derating Curve of Maximum Power Dissipation
Figure 6. Synchronous Buck Converter Circuit
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS9624E-00 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT9624E
Outline Dimension
D2
D
L
E
E2
1
e
SEE DETAIL A
b
2
1
2
1
A
A1
A3
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.200
0.300
0.008
0.012
D
2.950
3.050
0.116
0.120
D2
2.100
2.350
0.083
0.093
E
2.950
3.050
0.116
0.120
E2
1.350
1.600
0.053
0.063
e
L
0.650
0.425
0.026
0.525
0.017
0.021
W-Type 8L DFN 3x3 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
www.richtek.com
14
DS9624E-00 January 2014