® RT9624C Single Phase Synchronous Rectified Buck MOSFET Driver General Description Features The RT9624C is a high frequency, synchronous rectified, single phase MOSFET driver designed for normal MOSFET driving applications and high performance CPU VR driving capabilities. Drive Two N-MOSFETs Shoot-Through Protection Embedded Bootstrap Switch Support High Switching Frequency Fast Output Rising Time Tri-State PWM Input for Output Shutdown Enable Control Small 8-Lead WDFN Package RoHS Compliant and Halogen Free The RT9624C can be supplied from 4.5V to 13.2V. The applicable power stage VIN range is from 5V to 24V. The RT9624C also builds in an internal power switch to replace external bootstrap diode. The RT9624C can support switching frequency efficiently up to 500kHz. The RT9624C has both the UGATE and LGATE driving circuits for synchronous rectified DC/DC converter applications. The shoot through protection mechanism is designed to prevent shoot through between high side and low side power MOSFETs. The RT9624C has tri-state PWM input with shutdown and EN input shutdown functions, which can force driver to output low UGATE and LGATE signals. The RT9624C comes in a small footprint with WDFN-8SL 2x2 package. Applications Core Voltage Supplies for Desktop, Motherboard CPU High Frequency Low Profile DC/DC Converters High Current Low Voltage DC/DC Converters Core Voltage Supplies for GFX Card Marking Information 1C : Product Code 1CW W : Date Code Simplified Application Circuit RT9624C 12V R1 VCC BOOT UGATE EN PWM R3 Q1 L1 VOUT PHASE R4 LGATE GND Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9624C-03 April 2014 C6 R5 Q2 + PWM Controller C5 CBOOT C1 Chip Enable VIN R2 C3 C4 C2 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT9624C Ordering Information Pin Configurations Package Type QWA : WDFN-8SL 2x2 (W-Type) (Exposed Pad-Option 1) Lead Plating System G : Green (Halogen Free and Pb Free) BOOT PWM EN VCC 1 2 3 4 GND (TOP VIEW) RT9624C 9 8 7 6 5 UGATE PHASE GND LGATE WDFN-8SL 2x2 Note : Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Function Pin Description Pin No. Pin Name Pin Function 1 BOOT Bootstrap Supply for High Side Gate Driver. 2 PWM PWM Signal Input. Connect this pin to the PWM output of the controller. 3 EN Chip Enable (Active High). When this pin is low, both UGATE and LGATE are driven to low. 4 VCC Supply Voltage Input. 5 LGATE 6, GND 9 (Exposed Pad) 7 PHASE 8 UGATE Low Side Gate Driver Output. Connect this pin to the Gate of low side power N-MOSFET. Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Connect this pin to the Source of the high side N-MOSFET and the Drain of the low side N-MOSFET. High Side Gate Driver Output. Connect this pin to the Gate of high side power N-MOSFET. Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS9624C-03 April 2014 RT9624C Function Block Diagram Internal VDD PWM EN VCC Enable Detect POR Bootstrap Control BOOT Tri-State Detect Shoot-Through Protection UGATE Turn Off Detection PHASE VCC Shoot-Through Protection LGATE GND Operation POR (Power On Reset) Bootstrap Control POR block detects the voltage at the VCC pin. When the VCC pin voltage is higher than POR rising threshold, POR block output is high. POR output is low when VCC is not higher than POR rising threshold. When the POR block output is high, UGATE and LGATE can be controlled by PWM input voltage. If the POR block output is low, both UGATE and LGATE will be pulled to low. Bootstrap control block controls the integrated bootstrap switch. When LGATE is high (low side MOSFET is turned on), the bootstrap switch is turned on to charge the bootstrap capacitor connected to BOOT pin. When LGATE is low (low side MOSFET is turned off), the bootstrap switch is turned off to disconnect VCC pin and BOOT pin. Turn-Off Detection Enable Detect When EN pin input voltage is higher than EN rising threshold, MOSFET driver is enabled. When the EN input and POR output are high, UGATE and LGATE can be controlled by PWM input voltage. When EN input is low, both UGATE and LGATE are pulled to low. Turn-off detection block detects whether high side MOSFET is turned off by monitoring PHASE pin voltage. To avoid shoot-through between high side and low side MOSFETs, low side MOSFET can be turned on only after high side MOSFET is effectively turned off. Shoot-Through Protection Tri-State Detect When both POR block output and EN pin voltages are high, UGATE and LGATE can be controlled by PWM input. There are three PWM input modes, which are high, low, and shutdown state. If PWM input is within the shutdown window, both UGATE and LGATE output are low. When PWM input is higher than its rising threshold, UGATE is high and LGATE is low. When PWM input is lower than its falling threshold, UGATE is low and LGATE is high. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9624C-03 April 2014 Shoot-through protection block implements the dead time when both high side and low side MOSFETs are turned off. With shoot-through protection block, high side and low side MOSFET are never turned on simultaneously. Thus, shoot-through between high side and low side MOSFETs is prevented. is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT9624C Absolute Maximum Ratings (Note 1) Supply Voltage, VCC -------------------------------------------------------------------------------- −0.3V to 15V BOOT to PHASE ------------------------------------------------------------------------------------- −0.3V to 15V PHASE to GND DC -------------------------------------------------------------------------------------------------------- −0.3V to 30V < 20ns --------------------------------------------------------------------------------------------------- −10V to 35V LGATE to GND DC -------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V) < 20ns --------------------------------------------------------------------------------------------------- −2V to (VCC + 0.3V) UGATE to GND DC -------------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V) < 20ns --------------------------------------------------------------------------------------------------- (VPHASE − 2V) to (VBOOT + 0.3V) EN, PWM to GND ------------------------------------------------------------------------------------ −0.3V to 7V Power Dissipation, PD @ TA = 25°C WDFN-8SL 2x2 --------------------------------------------------------------------------------------- 2.17W Package Thermal Resistance (Note 2) WDFN-8SL 2x2, θJA ---------------------------------------------------------------------------------- 46°C/W WDFN-8SL 2x2, θJC --------------------------------------------------------------------------------- 11.5°C/W Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------- 260°C Junction Temperature -------------------------------------------------------------------------------- 150°C Storage Temperature Range ----------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Model) ------------------------------------------------------------------------- 2kV Recommended Operating Conditions (Note 4) Supply Voltage, VCC -------------------------------------------------------------------------------- 4.5V to 13.2V Input Voltage, (VIN + VCC) ------------------------------------------------------------------------- < 35V Junction Temperature Range ----------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ----------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VCC = 12V, TA = 25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 4.5 -- 13.2 V Power Supply Power Supply Voltage VCC Power Supply Current IVCC VBOOT = 12V, PWM Input Floating -- 120 -- A POR Rising Threshold VPOR_r VCC Rising -- 4 4.4 V POR Falling Threshold VPOR_ f VCC Falling 3 3.5 -- V Power On Reset (POR) EN Input EN Rising Threshold VENH -- 1.3 1.6 V EN Falling Threshold VENL 0.7 1 -- V Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS9624C-03 April 2014 RT9624C Parameter Symbol Test Conditions Min Typ Max Unit PWM Input Maximum Input Current IPWM PWM = 0V or 5V -- 160 -- A PWM Floating Voltage VPWM_fl PWM = Open -- 1.8 -- V PWM Rising Threshold VPWM_rth 2.3 2.8 3.2 V PWM Falling Threshold VPWM_fth 0.7 1.1 1.4 V Timing UGATE Rising Time tUGATEr 3nF Load -- 25 -- ns UGATE Falling Time tUGATEf 3nF Load -- 12 -- ns LGATE Rising Time tLGATEr 3nF Load -- 24 -- ns LGATE Falling Time tLGATEf 3nF Load -- 10 -- ns tUGATEpdh -- 60 -- tUGATEpdl VBOOT VPHASE = 12V See Timing Diagram -- 22 -- tLGATEpdh See Timing Diagram -- 30 -- tLGATEpdl See Timing Diagram -- 8 -- UGATE Drive Source RUGATEsr VBOOT VPHASE = 12V, I Source = 100mA -- 1.7 -- UGATE Drive Sink RUGATEsk VBOOT VPHASE = 12V, I Sink = 100mA -- 1.4 -- LGATE Drive Source RLGATEsr ISource = 100mA -- 1.6 -- LGATE Drive Sink RLGATEsk ISink = 100mA -- 1.1 -- UGATE Propagation Delay LGATE Propagation Delay ns ns Output Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9624C-03 April 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT9624C Typical Application Circuit RT9624C R1 2.2 12V VCC C1 1µF Chip Enable CBOOT 1µF R3 2.2 Q1 UGATE EN PWM VIN 12V C6 10µF x4 C5 1000µF x3 L1 1µH VOUT PHASE R4 0 LGATE GND + PWM Controller BOOT R2 1 R5 2.2 Q2 C3 2200µF x2 C2 3.3nF C4 10µF x2 Timing Diagram PWM LGATE tLGATEpdl 90% tUGATEpdl 1.5V 1.5V 1.5V 90% 1.5V UGATE tUGATEpdh Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 tLGATEpdh is a registered trademark of Richtek Technology Corporation. DS9624C-03 April 2014 RT9624C Typical Operating Characteristics Drive Enable Drive Disable UGATE (50V/Div) UGATE (50V/Div) PHASE (20V/Div) PHASE (20V/Div) LGATE (20V/Div) LGATE (20V/Div) EN (10V/Div) EN (10V/Div) VIN = 12V, No Load VIN = 12V, No Load Time (1μs/Div) Time (1μs/Div) PWM Rising Edge PWM Falling Edge PWM (10V/Div) PWM (10V/Div) UGATE (20V/Div) UGATE (20V/Div) LGATE (10V/Div) LGATE (10V/Div) PHASE (10V/Div) PHASE (10V/Div) Time (20ns/Div) Time (20ns/Div) Dead Time Dead Time UGATE UGATE PHASE PHASE LGATE LGATE (5V/Div) (5V/Div) Full Load Time (20ns/Div) Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9624C-03 April 2014 Full Load Time (20ns/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT9624C Dead Time Dead Time UGATE UGATE PHASE PHASE LGATE (5V/Div) LGATE (5V/Div) No Load Time (20ns/Div) No Load Time (20ns/Div) Short Pulse UGATE LGATE PHASE (5V/Div) UGATE − PHASE No Load Time (20ns/Div) Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS9624C-03 April 2014 RT9624C Application Information The RT9624C is a high frequency, synchronous rectified, single phase dual MOSFET driver containing Richtek's advanced MOSFET driver technologies. The RT9624C is designed to be able to adapt from normal MOSFET driving applications to high performance CPU VR driving capabilities. Supply Voltage and Power On Reset The RT9624C can be utilized under both VCC = 5V or VCC = 12V applications which may happen in different fields of electronics application circuits. In terms of efficiency, higher VCC equals higher driving voltage of UGATE/LGATE which may result in higher switching loss and lower conduction loss of power MOSFETs. The choice of VCC = 12V or VCC = 5V can be a tradeoff to optimize system efficiency. The RT9624C is designed to drive both high side and low side N-MOSFET through external input PWM control signal. It has power on protection function which held UGATE and LGATE low before the VCC voltage rises to higher than rising threshold voltage. Enable and Disable The RT9624C includes an EN pin for sequence control. When the EN pin rises above the VENH trip point, the RT9624C begins a new initialization and follows the PWM command to control the UGATE and LGATE. When the EN pin falls below the VENL trip point, the RT9624C shuts down and keeps UGATE and LGATE low. are disabled and both MOSFET gates are pulled and held low. If the PWM signal is left floating, the pin will be kept around 1.8V by the internal divider and provide the PWM controller with a recognizable level. Internal Bootstrap Power Switch The RT9624C builds in an internal bootstrap power switch to replace external bootstrap diode, and this can facilitate PCB design and reduce total BOM cost of the system. Hence, no external bootstrap diode is required in real applications. Non-overlap Control To prevent the overlap of the gate drivers during the UGATE pull low and the LGATE pull high, the non-overlap circuit monitors the voltages at the PHASE node and high side gate drive (UGATE-PHASE). When the PWM input signal goes low, UGATE begins to pull low (after propagation delay). Before LGATE is pulled high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.1V. Once the monitored voltages fall below 1.1V, LGATE begins to turn high. By waiting for the voltages of the PHASE pin and high side gate driver to fall below 1.1V, the non-overlap protection circuit ensures that UGATE is low before LGATE pulls high. Also to prevent the overlap of the gate drivers during LGATE pull low and UGATE pull high, the non-overlap circuit monitors the LGATE voltage. When LGATE goes below 1.1V, UGATE goes high after propagation delay. Tri-state PWM Input Driving Power MOSFETs After the initialization, the PWM signal takes the control. The rising PWM signal first forces the LGATE signal to turn low then UGATE signal is allowed to go high just after a non-overlapping time to avoid shoot through current. The falling of PWM signal first forces UGATE to go low. When UGATE and PHASE signal reach a predetermined low level, LGATE signal is allowed to turn high. The DC input impedance of the power MOSFET is extremely high. When Vgs1 or Vgs2 is at 12V or 5V, the gate draws the current only for few nano-amperes. Thus once the gate has been driven up to “ ON” level, the current could be negligible. The PWM signal is acted as “ High” if the signal is above the rising threshold and acted as “ Low” if the signal is below the falling threshold. When PWM signal level enters and remains within the shutdown window, the output drivers Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9624C-03 April 2014 However, the capacitance at the gate to source terminal should be considered. It requires relatively large currents to drive the gate up and down 12V (or 5V) rapidly. It is also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows. is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT9624C d1 s1 VPHASE VIN L VOUT Cgs1 Cgd1 g1 Ig2 Igd2 g2 D2 Cgs2 Igd2 Cgd2 s2 GND Vg1 VPHASE +12V Igs1 12V Igs2 t Figure 1. Equivalent Circuit and Waveforms (VCC = 12V) In Figure 1, the current Ig1 and Ig2 are required to move the gate up to 12V. The operation consists of charging Cgd1, Cgd2 , Cgs1 and Cgs2. Cgs1 and Cgs2 are the capacitors from gate to source of the high side and the low side power MOSFETs, respectively. In general data sheets, the Cgs1 and C gs2 are referred as “ Ciss” which are the input capacitors. Cgd1 and Cgd2 are the capacitors from gate to drain of the high side and the low side power MOSFETs, respectively and referred to the data sheets as “ Crss” the reverse transfer capacitance. For example, tr1 and tr2 are the rising time of the high side and the low side power MOSFETs respectively, the required current Igs1 and Igs2, are shown as below : dVg1 Cgs1 x 12 (1) Igs1 Cgs1 dt tr1 dVg2 dt Cgs1 x 12 (2) tr2 Before driving the gate of the high side MOSFET up to 12V, the low side MOSFET has to be off; and the high side MOSFET will be turned off before the low side is turned on. From Figure 1, the body diode “ D2” will be turned on before high side MOSFETs turn on. Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 VIN 12 dV Cgd2 dt tr2 (4) It is helpful to calculate these currents in a typical case. Assume a synchronous rectified Buck converter, input voltage VIN = 12V, Vgs1 = 12V, Vgs2 = 12V. The high side MOSFET is PHB83N03LT whose C iss = 1660pF, Crss = 380pF, and tr = 14ns. The low side MOSFET is PHB95N03LT whose Ciss = 2200pF, Crss = 500pF and tr = 30ns, from the equation (1) and (2) we can obtain t Igs2 Cgs1 (3) been charged to VIN. Thus, as Cgd2 reverses its polarity and g2 is charged up to 12V, the required current is d2 Igs2 Vg2 dV 12 = Cgd1 dt tr1 Before the low side MOSFET is turned on, the Cgd2 have Cgd2 Igs1 Igd1 Ig1 Igd1 = Cgd1 1660 x 10-12 x 12 14 x 10-9 2200 x 10-12 x 12 30 x 10-9 1.428 0.88 (A) (A) (5) (6) from equation. (3) and (4) Igd1 Igd2 380 x 10-12 x 12 14 x 10-9 0.326 (A) 500 x 10-12 x 12+12 30 x 10-9 0.4 (A) (7) (8) the total current required from the gate driving source can be calculated as the following equations. Ig1 Igs1 Igd1 1.428 0.326 1.754 (A) Ig2 Igs2 Igd2 0.88 0.4 1.28 (A) (9) (10) By a similar calculation, we can also get the sink current required from the turned off MOSFET. Select the Bootstrap Capacitor Figure 2 shows part of the bootstrap circuit of the RT9624C. The VCB (the voltage difference between BOOT and PHASE on RT9624C) provides a voltage to the gate of the high side power MOSFET. This supply needs to be ensured that the MOSFET can be driven. For this, the capacitance CBOOT has to be selected properly. It is determined by the following constraints. is a registered trademark of Richtek Technology Corporation. DS9624C-03 April 2014 RT9624C Figure 4 shows the power dissipation of the RT9624C as a function of frequency and load capacitance when VCC = VIN BOOT UGATE CBOOT PHASE 12V. The value of CU and CL are the same and the frequency is varied from 100kHz to 1MHz. + VCB - Power Dissipation vs. Frequency 1000 VCC GND Figure 2. Part of Bootstrap Circuit of RT9624C In practice, a low value capacitor CBOOT will lead to the over charging that could damage the IC. Therefore, to minimize the risk of overcharging and to reduce the ripple on VCB, the bootstrap capacitor should not be smaller than 0.1μF, and the larger the better. In general design, using 1μF can provide better performance. At least one low-ESR capacitor should be used to provide good local de-coupling. It is recommended to adopt a ceramic or tantalum capacitor. Power Dissipation To prevent driving the IC beyond the maximum recommended operating junction temperature of 125°C, it is necessary to calculate the power dissipation appropriately. This dissipation is a function of switching frequency and total gate charge of the selected MOSFET. Figure 3 shows the power dissipation test circuit. CL and C U are the UGATE and LGATE load capacitors, respectively. The bootstrap capacitor value is 1μF. 12V BOOT 10 VCC 2N7002 UGATE 1µF CU 3nF RT9624C Chip Enable PWM PHASE EN PWN 2N7002 LGATE GND 20 CL 3nF Figure 3. Power Dissipation Test Circuit Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS9624C-03 April 2014 CU = CL = 3nF 800 700 600 CU = CL = 2nF 500 400 300 CU = CL = 1nF 200 100 VCC = 12V 0 0 200 400 600 800 1000 Frequency (kHz) Figure 4. Power Dissipation vs. Frequency The operating junction temperature can be calculated from the power dissipation curves (Figure 4). Assume VCC = 12V, operating frequency is 200kHz and CU = CL = 1nF which emulate the input capacitances of the high side and low side power MOSFETs. From Figure 4, the power dissipation is 100mW. Thus, for example, with the WDFN8SL 2x2 package, the package thermal resistance θJA is 46°C/W. The operating junction temperature is then calculated as : TJ = (46°C/W x 100mW) + 25°C = 29.6°C (11) where the ambient temperature is 25°C. Thermal Considerations CBOOT 1µF 12V Power Dissipation (mW) 900 LGATE For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT9624C For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For WDFN-8SL 2x2 package, the thermal resistance, θJA, is 46°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formulas : P D(MAX) = (125°C − 25°C) / (46°C/W) = 2.17W for WDFN-8SL 2x2 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curve in Figure 5 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. Four-Layer PCB 2.4 Figure 6 shows the schematic circuit of a synchronous buck converter to implement the RT9624C. The converter operates from 5V to 12V of input Voltage. For the PCB layout, it should be very careful. The power circuit section is the most critical one. If not configured properly, it will generate a large amount of EMI. The location of Q1, Q2, L1 should be very close. Next, the trace from UGATE, and LGATE should also be short to decrease the noise of the driver output signals. PHASE signals from the junction of the power MOSFET, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. The bypass capacitor C1 should be connected to GND directly. Furthermore, the bootstrap capacitors (CBOOT) should always be placed as close to the pins of the IC as possible. VIN 12V 2.0 L2 12V + 1.6 C5 C6 R1 BOOT 1.2 VCC CBOOT Q1 L1 VCORE 0.4 UGATE PHB83N03LT PHASE C3 0.0 0 25 50 75 100 125 Q2 PHB95N03LT LGATE RT9624C C1 0.8 + Maximum Power Dissipation (W) 2.8 Layout Consideration PWM EN PWM EN GND Ambient Temperature (°C) Figure 5. Derating Curve of Maximum Power Dissipation Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 Figure 6. Synchronous Buck Converter Circuit is a registered trademark of Richtek Technology Corporation. DS9624C-03 April 2014 RT9624C Outline Dimension 2 1 2 1 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min. Max. Min. Max. A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 D 1.900 2.100 0.075 0.083 Option1 1.150 1.250 0.045 0.049 Option2 1.550 1.650 0.061 0.065 E 1.900 2.100 0.075 0.083 Option1 0.750 0.850 0.030 0.033 Option2 0.850 0.950 0.033 0.037 D2 E2 e L 0.500 0.250 0.020 0.350 0.010 0.014 W-Type 8SL DFN 2x2 Package Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS9624C-03 April 2014 www.richtek.com 13