Evaluation Board User Guide UG-472 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluating the AD5142A Digital Potentiometer FEATURES GENERAL DESCRIPTION Full featured evaluation board in conjunction with low voltage digiPOT motherboard (EVAL-MB-LV-SDZ) Various test circuits Various ac/dc input signals PC control via a separately purchased system demonstration platform (SDP-B or SDP-S) PC software for control This user guide describes the evaluation board for evaluating the AD5142A—a quad-channel, 256-position, nonvolatile memory, digital potentiometer. With versatile programmability, the AD5142A allows multiple modes of operation, including read/write access in the RDAC and EEMEM registers, increment/decrement of resistance, resistance changes in ±6 dB scales, wiper setting readback, and extra EEMEM for storing user-defined information, such as memory data for other components or a lookup table. PACKAGE CONTENTS EVAL-AD5142ADBZ board EVAL-MB-LV-SDZ motherboard CD that includes Self-installing software that allows users to control the board and exercise all functions of the device Electronic version of the AD5142A data sheet Electronic version of the UG-472 user guide The AD5142A supports a dual-supply ±2.25 V to ±2.75 V operation and a single-supply 2.3 V to 5.5 V operation, making the device suitable for battery-powered applications and many other applications. In addition, the AD5142A uses a versatile I2C-compatible serial interface that operates in fast mode, allowing speeds of up to 400 kbps and supporting the selection of up to nine different I2C addresses. The EVAL-AD5142DBZ can operate in single-supply or dual-supply mode and incorporates an internal power supply from the USB. Complete specifications for the AD5142A part can be found in the AD5142A data sheet, which is available from Analog Devices, Inc., and should be consulted in conjunction with this user guide when using the evaluation board. 11009-001 EVAL-AD5142ADBZ WITH MOTHERBOARD AND SDP-S Figure 1. Digital Picture of Evaluation Board with Low Voltage DigiPOT Motherboard and System Demonstration Platform PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 20 UG-472 Evaluation Board User Guide TABLE OF CONTENTS Features .............................................................................................. 1 Evaluation Board Software ...............................................................8 Package Contents .............................................................................. 1 Installing the Software ..................................................................8 General Description ......................................................................... 1 Software Operation .................................................................... 10 EVAL-AD5142ADBZ with Motherboard and SDP-S .................. 1 Evaluation Board Schematics and Artwork ................................ 11 Revision History ............................................................................... 2 Motherboard ............................................................................... 11 Evaluation Board Hardware ............................................................ 3 Daughter Board .......................................................................... 15 Power Supplies .............................................................................. 3 Ordering Information .................................................................... 18 Test Circuits................................................................................... 4 Bill of Materials ........................................................................... 18 REVISION HISTORY 11/12—Revision 0: Initial Version Rev. 0 | Page 2 of 20 Evaluation Board User Guide UG-472 EVALUATION BOARD HARDWARE functions of these link options are described in detail in Table 4 through Table 7. POWER SUPPLIES The EVAL-MB-LV-SDZ motherboard supports using single and dual power supplies. The EVAL-AD5142ADBZ evaluation board can be powered either from the SDP port or externally by the J1 and J2 connectors, as described in Table 1. All supplies are decoupled to ground using 10 µF tantalum and 0.1 µF ceramic capacitors. Table 1. Maximum and Minimum Voltages of the Connectors Connector No. J1-1 Label VDD J1-2 J1-3 AGND VSS J2-1 J2-2 VLOGIC DGND Voltage Analog positive power supply, VDD. Single supply from 2.3 V to 5.5 V. Dual supply from 2.25 V to 2.75 V. Analog ground. Analog negative power supply, VSS. Dual supply from −2.25 V to −2.75 V. Digital supply, from 1.8 V to VDD. Digital ground. Table 2. Link Options Setup for SDP Control (Default) Link No. A5 A11 A12 Option +3V3 3.3 V AGND Linear Gain Setting Mode The linear gain setting mode pin is controlled directly by Jumper A1. If the jumper is placed in DEPEN, the AD5142A powers up in potentiometer mode, and the linear gain setting mode can be controlled by software. If the jumper is placed in INDEP, the part powers up in linear gain setting mode, loading independent values for each resistor string—RAW1, RWB1, RAW2, and RWB2. The part cannot be placed in potentiometer mode again unless the jumper is manually placed in DEPEN. I2C Address Selection The I2C address can be selected by using Link A1 and Link A2 as described in Table 3. Table 3. I2C Address Selection Link Options Several link and switch options are incorporated in the EVALMB-LV-SDZ motherboard and should be set up before using the board. Table 2 describes the positions of the links to control the evaluation board via the SDP board using a PC. The Link A1 Position A Position B Link A2 Position A Position B Position A Position B I2C Address 0101111 0100011 0101100 0100000 Table 4. Link Functions Link No. A5 Power Supply VLOGIC A11 VDD A12 VSS Options This link selects one of the following as the digital supply: +3V3 (3.3 V from SDP). VLOGIC EXT (external supply from the J2 connector). This link selects one of the following as the positive power supply: +5 V (5 V from SDP). 3V3 (3.3 V from SDP). VDD (external supply from the J1 connector). This link selects one of the following as the negative power supply: AGND. EXTVSS (external supply from the J1 connector). Rev. 0 | Page 3 of 20 UG-472 Evaluation Board User Guide TEST CIRCUITS However, by using the R34 and R35 external resistors, the user can reduce the voltage of the voltage references. In this case, use the A1 and B1 test points to measure the voltage applied to the A and B terminals and to recalculate VA and VB in Equation 1. The EVAL-AD5142ADBZ and EVAL-MB-LV-SDZ incorporate several test circuits to evaluate the performance of the AD5142A. DAC Table 5. DAC Voltage References The digiPOT can be operated as a digital-to-analog converter (DAC), as shown in Figure 2. Table 5 describes the options available for the voltage references. The output voltage is defined in Equation 1. VOUT RDAC1 = (VA − VB ) × 256 (1) Terminal A1 Link A9 Options AC+ VDD W1 BUF-W1 B1 A10 BIAS VSS AGND where: RDAC1 is the code loaded in the RDAC1 register. VA is the voltage applied to the A terminal (A9 link). VB is the voltage applied to the B terminal (A10 link). VDD 2 AC+ VDD VDD R34 RDAC1 A1 A1 W1 W1 VOUT1 BUF-W1 B1 B1 R35 VDD 2 BIAS VSS VSS 11009-002 AGND Figure 2. DAC Rev. 0 | Page 4 of 20 Description Connects Terminal A1 to VDD/2 Connects Terminal A1 to VDD Connects Terminal W1 to an output buffer Connects Terminal B1 to VDD/2 Connects Terminal B1 to VSS Connects Terminal B1 to analog ground Evaluation Board User Guide UG-472 AC Signal Attenuation Table 6. AC Signal Attenuation Link Options The RDAC can be used to attenuate an ac signal, which must be provided externally using the AC_INPUT connector, as shown in Figure 3. Voltage Supply Single Depending on the voltage supply rails and the dc offset voltage of the ac signal, various configurations can be used as described in Table 6. Maximum AC Signal Amplitude VDD Link A9 Options AC+ A10 AC BIAS A9 GND AC+ A10 AC GND The signal attenuation is defined in Equation 2. R + RW Attenuation (dB) = 20 × log WB1 R AB (2) where: RW is the wiper resistance. RAB is the end-to-end resistance value. RWB1 is the resistor between the W1 and B1 terminals. Dual VDD/VSS VSS 1 1kHz Recommended to ensure optimal total harmonic distortion (THD) performance. VDD 2 HPF AC+ AC AC_INPUT R34 RDAC1 A1 A1 W1 W1 VOUT1 BUF-W1 B1 B1 R35 VDD BIAS 2 VSS Conditions No dc offset voltage; the ac signal is outside the voltage supply rails due to the dc offset voltage; or the dc offset voltage ≠ VDD/2.1 All other conditions. Use in conjunction with the AC+ link. All other conditions. The ac signal is outside the voltage supply rails due to the dc offset voltage; the dc offset voltage ≠ 0 V.1 All other conditions. Use in conjunction with the AC+ link. All other conditions. AGND Figure 3. AC Signal Attenuator Rev. 0 | Page 5 of 20 11009-003 VSS UG-472 Evaluation Board User Guide Signal Amplifier The inverting amplifier with linear gain is shown in Figure 6, and the gain is defined in Equation 5. The RDAC can be operated as an inverting or noninverting signal amplifier supporting linear or pseudologarithmic gains. Table 7 shows the available configurations. Note that the input signal, VIN, must be negative. The noninverting amplifier with linear gain is shown in Figure 4, and the gain is defined in Equation 3. RWB2 R AW2 (3) RWB2 R AW2 (5) where: RWB2 is the code loaded for the RWB2 resistance. RAW2 is the code loaded for the RAW2 resistance. where: RWB2 is the code loaded for the RWB2 resistance. RAW2 is the code loaded for the RAW2 resistance. R41 1.7kΩ VOUT2 C1 10nF W2 R41 1.7kΩ VIN VOUT2 A2 VIN C1 10nF W2 R43 W2 A2 RDAC2 B2 11009-006 G =1+ G=− R42 B2 Figure 6. Linear Inverting Amplifier A2 R42 B2 RDAC2 R43 and R42 can be used to set the maximum and minimum gain limits. Figure 4. Linear Noninverting Amplifier The inverting amplifier with pseudologarithmic gain is shown in Figure 7, and the gain is defined in Equation 6. R43 and R42 can be used to set the maximum and minimum gain limits. G=− The noninverting amplifier with pseudologarithmic gain is shown in Figure 5, and the gain is defined in Equation 4. RDAC2 G =1+ 256 − RDAC2 (4) RDAC2 256 − RDAC2 (6) where: RDAC2 is the code loaded in the RDAC2. R41 1.7kΩ where: RDAC2 is the code loaded in the RDAC2. VOUT2 A2 VIN C1 10nF W2 A2 RDAC2 B2 R42 R43 W2 A2 RDAC2 B2 B2 R42 Figure 7. Pseudologarithmic Inverting Amplifier B2 W2 R43 and R42 can be used to set the maximum and minimum gain limits. 11009-005 A2 C1 10nF W2 R41 1.7kΩ VIN R43 VOUT2 11009-007 R43 B2 W2 11009-004 A2 Figure 5. Pseudologarithmic Noninverting Amplifier R43 and R42 can be used to set the maximum and minimum gain limits. Rev. 0 | Page 6 of 20 Evaluation Board User Guide UG-472 Table 7. Amplifier Selection Link Options Amplifier Noninverting Inverting Gain Linear Linear Setting Gain Mode Enabled Yes Pseudologarithmic No Linear Yes Pseudologarithmic No Rev. 0 | Page 7 of 20 Link A7 A6 A8 A7 A6 A8 A7 A6 A8 A7 A6 A8 Label LIN N-INV N-INV LOG N-INV N-INV LIN INV INV LOG INV INV UG-472 Evaluation Board User Guide EVALUATION BOARD SOFTWARE INSTALLING THE SOFTWARE The EVAL-AD5142ADBZ kit includes a CD containing the evaluation board software. The software is compatible with Windows® XP, Windows Vista, and Windows 7 (both 32 bits and 64 bits). 2. Install the software before connecting the SDP board to the USB port of the PC to ensure that the SDP board is recognized when it is connected to the PC. Start > Control Panel > Add or Remove Programs > AD5142A Eval Board. If the SDP board is not connected to the USB port when the software is launched, a connectivity error displays (see Figure 8). Simply connect the evaluation board to the USB port of the PC, wait a few seconds, click Rescan, and follow the instructions. 1. 2. 3. 4. 5. Start the Windows operating system and insert the CD into the CD-ROM drive. The installation software opens automatically. If it does not open automatically, run the setup.exe file from the CD. After the installation is complete, power up the evaluation board as described in the Power Supplies section. Connect the EVAL-AD5142ADBZ and EVAL-MB-LV-SDZ to the SDP board, and then connect the SDP board to the PC using the USB cable included with the SDP board. When the software detects the evaluation board, follow the instructions that appear to finalize the installation. 11009-008 To install the software, Figure 8. Pop-Up Window Error The main window of the EVAL-AD5142ADBZ software then opens, as shown in Figure 9. To run the program, do the following: 1. Click Start > All Programs > Analog Devices > AD5142A > AD5142A Eval Board. To uninstall the program, click Rev. 0 | Page 8 of 20 UG-472 11009-020 Evaluation Board User Guide Figure 9. EVAL-AD5142ADBZ Software Main Window Rev. 0 | Page 9 of 20 UG-472 Evaluation Board User Guide SOFTWARE OPERATION value in its respective block within the diagram. In addition, buttons are available that allow you to change the level of some hardware pins. The main window of the EVAL-AD5142ADBZ software has two tabs, Visual Mode and Manual Control. Manual Mode Visual Mode The Visual Mode tab is divided into the following sections: ALL CHANNELS COMMANDS, INDIVIDUAL CHANNEL COMMANDS, and a block diagram that contains boxes for changing the control register values and buttons and for controlling the hardware pins. The Manual Mode tab, as shown in Figure 10, allows you to customize an I2C data-word by manually switching the scroll bars from 0 to 1 or from 1 to 0, as desired, and then clicking SEND DATA. The INDIVIDUAL CHANNEL COMMANDS section allows you to send quick commands to only specific channels of the AD5142A. The block diagram allows you to update the control register status. Each register value can be easily updated by changing the Rev. 0 | Page 10 of 20 11009-021 The ALL CHANNELS COMMANDS section allows you to send quick commands directly to the AD5142A. Figure 10. Manual Mode Evaluation Board User Guide UG-472 EVALUATION BOARD SCHEMATICS AND ARTWORK 11009-010 MOTHERBOARD Figure 11. SDP Connector and Power Supply Rev. 0 | Page 11 of 20 UG-472 Evaluation Board User Guide 11009-011 Figure 12. Schematic of Test Circuits Rev. 0 | Page 12 of 20 UG-472 11009-012 Evaluation Board User Guide Figure 13. Schematic of Connectors to Daughter Board Rev. 0 | Page 13 of 20 Evaluation Board User Guide 11009-013 UG-472 11009-014 Figure 14. Component Side View of Motherboard 11009-015 Figure 15. Component Placement Drawing of Motherboard Figure 16. Layer 2 Side PCB Drawing of Motherboard Rev. 0 | Page 14 of 20 INDEP B2 W2 A2 B1 W1 INDEP ADDR1 ADDR0 U1 15 A3 A2 A1 10 9 INDEP 5 1 16 DEPEN VSS GND RESET 14 ADDR0 ADDR1 13 SDA 12 SCL 11 VLOGIC VDD AD5142A INDEP 8 B2 7 W2 6 A2 4 B1 3 W1 2 A1 B A B A B Figure 17. Schematic of Daughter Board A RESET ADDR0 ADDR1 SDA SCL VLOGIC DGND VLOGIC DGND VLOGIC DGND VLOGIC VSS DGND VDD VLOGIC VSS 10uF + C4 VDD 10uF + C2 0.1uF C3 0.1uF C1 SCLK J1-8 SDO J1-6 SDI SYNC J1-5 J1-7 SDA SCL J1-4 ADDR1 J1-2 J1-3 ADDR0 J1-1 DGND RESET J3-1 J4-1 WP J3-2 J4-2 VLOGIC LRDAC AGND DIS J3-4 W2 J2-11 B2 B2 A2 J2-10 J2-9 W2 J2-12 B1 J2-8 J2-7 A2 W1 J2-6 A1 J2-4 J2-5 B1 J2-2 J2-1 J2-3 A1 W1 J4-4 J3-3 J4-3 INDEP J3-5 J4-5 VSS Rev. 0 | Page 15 of 20 VDD A1 Evaluation Board User Guide UG-472 DAUGHTER BOARD 11009-016 Evaluation Board User Guide 11009-017 UG-472 11009-018 Figure 18. Component Side View of Daughter Board Figure 19. Component Placement Drawing of Daughter Board Rev. 0 | Page 16 of 20 UG-472 11009-019 Evaluation Board User Guide Figure 20. Layer 2 Side PCB Drawing of Daughter Board Rev. 0 | Page 17 of 20 UG-472 Evaluation Board User Guide ORDERING INFORMATION BILL OF MATERIALS Table 8. Motherboard Qty 3 3 5 1 2 1 1 1 2 17 1 1 1 1 1 1 3 5 1 8 4 2 4 2 1 1 1 1 1 1 1 1 1 18 5 1 Reference Designator BUF-3, BUF-4, BUF-W1 A6, A7, A8 A5, A9, A10, A11, A12 J1 J7, J8 J4 J10 J5 J2, J3 R1, R3, R6, R7, R8, R9, R10, R11, R12, R13, R20, R22, R23, R34, R35, R42, R43 R2 R41 R21 R38 R14 R4 R5, R25, R26 R15, R16, R17, R18, R19 C1 C4, C9, C10, C11, C12, C17, C19, C21 C2, C6, C7, C14 C8, C13 C18, C20, C22, C5 C3, C15 C16 C34 L2 D1 U1 U2 U3 U4 U5 LRDAC, RESET, SYNC, WP, A1, A2, A3, A4, AGND, B1, VOUT_C1, VOUT_C2, VOUT3, VOUT4, W1, W2, W3, W4 +3.3V , +5V, EXT_VDD, VLOGIC, EXT_VSS Description 2-pin (0.1" pitch) header and shorting shunt 3-pin SIL header and shorting link 6-pin (3 × 2), 0.1" header and shorting block 3-pin terminal block (5 mm pitch) 4-pin SIL header Receptacle, 0.6 mm, 120-way 8-pin in-line header; 100 mil centers 12-pin (2 × 6), 0.1" pitch header 2-pin terminal block (5 mm pitch) SMD resistor, 0 Ω, 0.01, 0603 Supplier 1/Part Number FEC 1022247 and 150411 FEC 1022248 and 150410 FEC 672014 and 150411 (36-pin strip) FEC 151790 FEC 1098035 Digi-Key H1219-ND FEC 1098038 FEC 1098051 FEC 151789 FEC 9331662 SMD resistor, 2.2 kΩ, 0.01, 0603 SMD resistor, 1.7 kΩ, 1% ,0603 Resistor, surge, 1.6 Ω, 1%, 0603 SMD resistor, 2.7 kΩ, 1%, 0603 SMD resistor, 100 Ω, 1%, 0603 SMD resistor, 1 kΩ, 0.01, 0603 SMD resistor, 100 kΩ, 1%, 0603 SMD resistor, 33 kΩ, 1%, 0603 SMD capacitor, 100 nF, 10%, 0805 SMD capacitor, 0.1 µF, ±10%, 0603 SMD capacitor, 0.1 µF, ±10%, 0603 SMD capacitor, 10 µF, ±10% Capacitor, 10 µF, ±20% Capacitor, 470 nF, ±10%, 0603 Capacitor, 4.7 nF, ±10%, 0603 Capacitor, 4.7 nF, ±20% Inductor, SMD, 600Z Green SMD LED Two-port level translating bus switch Dual op amp Precision low dropout voltage regulator Operational amplifier I2C serial EEPROM 64k 2.5 V MSOP-8 Terminal, PCB, black, PK100, test point FEC 1750676 FEC 1170811 FEC 1627674 FEC 1750678 FEC 9330364 FEC 9330380 FEC 9330402 FEC 9331034 FEC 1650863 FEC 1759122 FEC 3019482 FEC 197130 FEC 1190107 FEC 1414037 FEC 1414642 FEC 1432350 FEC 9526862 FEC 5790852 ADG3247BCPZ AD8652ARZ ADP3303ARZ-3.3 AD8618ARZ FEC 1331335 FEC 8731128 Terminal, PCB, red, PK100, test point FEC 8731144 FEC refers to Farnell Electronic Component Distributors; Digi-Key refers to Digi-Key Corporation. Rev. 0 | Page 18 of 20 Evaluation Board User Guide UG-472 Table 9. Daughter Board Qty 1 3 2 2 1 1 2 1 Reference Designator U1 A1, A2, A3 C2, C4 C1, C3 J1 J2 J3, J4 Description 256-position digital potentiometer 3-pin SIL header and shorting link 6.3 V tantalum capacitor (Case A), 10 µF, ±20% 50 V, X7R ceramic capacitor, 0.1 µF, ±10% Header, 2.54 mm, PCB, 1 × 8-way 12-pin (2 × 6), 0.1" pitch header 5-pin SIL header FEC refers to Farnell Electronic Component Distributors. Rev. 0 | Page 19 of 20 Supplier 1/Part Number AD5142ABCPZ10 FEC 1022248 and 150410 FEC 1190107 FEC 1759122 FEC 1766172 FEC 1804099 FEC 1929016 UG-472 Evaluation Board User Guide NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. 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Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG11009-0-11/12(0) Rev. 0 | Page 20 of 20