PDF Data Sheet Rev. B

Quad Channel, 128-/256-Position, I2C,
Nonvolatile Digital Potentiometer
AD5123/AD5143
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VDD
10 kΩ and 100 kΩ resistance options
Resistor tolerance: 8% maximum
Wiper current: ±6 mA
Low temperature coefficient: 35 ppm/°C
Wide bandwidth: 3 MHz
Fast start-up time < 75 μs
Linear gain setting mode
Single- and dual-supply operation
Wide operating temperature: −40°C to +125°C
3 mm × 3 mm package
AD5123/AD5143
POWER-ON
RESET
RDAC1
A1
INPUT
REGISTER 1
W1
B1
RDAC2
INPUT
REGISTER 2
SCL
A2
W2
B2
SDA
SERIAL
INTERFACE
RDAC3
7/8
INPUT
REGISTER 3
ADDR
W3
B3
APPLICATIONS
RDAC4
Portable electronics level adjustment
LCD panel brightness and contrast controls
Programmable filters, delays, and time constants
Programmable power supplies
INPUT
REGISTER 4
W4
B4
GND
10878-001
EEPROM
MEMORY
VSS
Figure 1.
GENERAL DESCRIPTION
Table 1. Family Models
The AD5123/AD5143 potentiometers provide a nonvolatile
solution for 128-/256-position adjustment applications, offering
guaranteed low resistor tolerance errors of ±8% and up to ±6 mA
current density in the Ax, Bx, and Wx pins.
Model
AD51231
AD5124
AD5124
AD5143
AD5144
AD5144
AD5144A
AD5122
AD5122A
AD5142
AD5142A
AD5121
AD5141
The low resistor tolerance and low nominal temperature coefficient
simplify open-loop applications as well as applications requiring
tolerance matching.
The linear gain setting mode allows independent programming
of the resistance between the digital potentiometer terminals,
through the RAW and RWB string resistors, allowing very accurate
resistor matching.
The high bandwidth and low total harmonic distortion (THD)
ensure optimal performance for ac signals, making the devices
suitable for filter design.
1
The low wiper resistance of only 40 Ω at the ends of the resistor
array allows for pin to pin connection.
Channel
Quad
Quad
Quad
Quad
Quad
Quad
Quad
Dual
Dual
Dual
Dual
Single
Single
Position
128
128
128
256
256
256
256
128
128
256
256
128
256
Interface
I2C
SPI/I2C
SPI
I2C
SPI/I2C
SPI
I2C
SPI
I2C
SPI
I2C
SPI/I2C
SPI/I2C
Package
LFCSP
LFCSP
TSSOP
LFCSP
LFCSP
TSSOP
TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP
LFCSP
Two potentiometers and two rheostats.
The wiper values can be set through an I2C-compatible digital
interface that also reads back the wiper register and EEPROM
contents.
The AD5123/AD5143 are available in a compact, 16-lead, 3 mm ×
3 mm LFCSP. The devices are guaranteed to operate over the
extended industrial temperature range of −40°C to +125°C.
Rev. B
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AD5123/AD5143
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Theory of Operation ...................................................................... 19 Applications ....................................................................................... 1 RDAC Register and EEPROM .................................................. 19 Functional Block Diagram .............................................................. 1 Input Shift Register .................................................................... 19 General Description ......................................................................... 1 I2C Serial Data Interface ............................................................ 19 Revision History ............................................................................... 2 I2C Address .................................................................................. 19 Specifications..................................................................................... 3 Advanced Control Modes ......................................................... 21 Electrical Characteristics—AD5123 .......................................... 3 EEPROM or RDAC Register Protection ................................. 22 Electrical Characteristics—AD5143 .......................................... 6 RDAC Architecture .................................................................... 25 Interface Timing Specifications .................................................. 9 Programming the Variable Resistor ......................................... 25 Shift Register and Timing Diagrams ....................................... 10 Programming the Potentiometer Divider ............................... 26 Absolute Maximum Ratings.......................................................... 11 Terminal Voltage Operating Range ......................................... 26 Thermal Resistance .................................................................... 11 Power-Up Sequence ................................................................... 26 ESD Caution ................................................................................ 11 Layout and Power Supply Biasing ............................................ 26 Pin Configuration and Function Descriptions ........................... 12 Outline Dimensions ....................................................................... 27 Typical Performance Characteristics ........................................... 13 Ordering Guide .......................................................................... 27 Test Circuits ..................................................................................... 18 REVISION HISTORY
2/16—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Added Endnote, Table 2 ................................................................... 5
Added Endnote, Table 3 ................................................................... 8
Changes to Table 5 .......................................................................... 11
Changes to Figure 4 ........................................................................ 12
Change to Table 9 ........................................................................... 20
3/13—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
10/12—Revision 0: Initial Version
Rev. B | Page 2 of 28
Data Sheet
AD5123/AD5143
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5123
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution
Resistor Integral Nonlinearity 2
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance3
Bottom Scale or Top Scale
Nominal Resistance Match
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity 4
Differential Nonlinearity4
Full-Scale Error
Zero-Scale Error
Voltage Divider Temperature
Coefficient3
Symbol
Test Conditions/Comments
N
R-INL
Min
Typ 1
Max
7
RAB = 10 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
RAB = 100 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
R-DNL
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
Unit
Bits
−1
−2.5
±0.1
±1
+1
+2.5
LSB
LSB
−0.5
−1
−0.5
−8
±0.1
±0.25
±0.1
±1
35
+0.5
+1
+0.5
+8
LSB
LSB
LSB
%
ppm/°C
55
130
125
400
Ω
Ω
−1
40
60
±0.2
80
230
+1
Ω
Ω
%
RAB = 10 kΩ
RAB = 100 kΩ
−0.5
−0.25
−0.25
±0.1
±0.1
±0.1
+0.5
+0.25
+0.25
LSB
LSB
LSB
RAB = 10 kΩ
RAB = 100 kΩ
−1.5
−0.5
−0.1
±0.1
+0.5
LSB
LSB
Code = full scale
Code = zero scale
RAB = 10 kΩ
RAB = 100 kΩ
RBS or RTS
RAB = 10 kΩ
RAB = 100 kΩ
Code = 0xFF
RAB1/RAB2
INL
DNL
VWFSE
VWZSE
(ΔVW/VW)/ΔT × 106
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale
Rev. B | Page 3 of 28
1
0.25
±5
1.5
0.5
LSB
LSB
ppm/°C
AD5123/AD5143
Parameter
RESISTOR TERMINALS
Maximum Continuous Current
Terminal Voltage Range 5
Capacitance A, Capacitance B3
Capacitance W3
Common-Mode Leakage Current3
DIGITAL INPUTS
Input Logic3
High
Low
Input Hysteresis3
Input Current3
Input Capacitance3
DIGITAL OUTPUTS
Output High Voltage3
Output Low Voltage3
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
EEPROM Store Current3, 6
EEPROM Read Current3, 7
Power Dissipation 8
Power Supply Rejection Ratio
Data Sheet
Symbol
Test Conditions/Comments
Min
RAB = 10 kΩ
RAB = 100 kΩ
−6
−1.5
VSS
Typ 1
Max
Unit
+6
+1.5
VDD
mA
mA
V
IA, IB, and IW
CA, CB
CW
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
VA = V W = V B
VINH
VINL
VHYST
IIN
CIN
VOH
VOL
−500
25
12
pF
pF
12
5
±15
pF
pF
nA
+500
0.7 × VDD
0.2 × VDD
0.1 × VDD
±1
5
RPULL-UP = 2.2 kΩ to VDD
ISINK = 3 mA
ISINK = 6 mA
VDD
−1
0.4
0.6
+1
V
V
V
µA
pF
5.5
±2.75
V
V
5.5
µA
nA
µA
mA
µA
µW
dB
2
VSS = GND
IDD
ISS
IDD_EEPROM_STORE
IDD_EEPROM_READ
PDISS
PSRR
VIH = VDD or VIL = GND
VDD = 5.5 V
VDD = 2.3 V
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
∆VDD/∆VSS = VDD ± 10%,
code = full scale
Rev. B | Page 4 of 28
2.3
±2.25
−5.5
0.7
400
−0.7
2
320
3.5
−66
V
V
V
µA
pF
−60
Data Sheet
Parameter
DYNAMIC CHARACTERISTICS 9
Bandwidth
Total Harmonic Distortion
Resistor Noise Density
VW Settling Time
AD5123/AD5143
Symbol
Test Conditions/Comments
BW
−3 dB
RAB = 10 kΩ
RAB = 100 kΩ
VDD/VSS = ±2.5 V, VA = 1 V rms,
VB = 0 V, f = 1 kHz
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale, TA = 25°C,
f = 10 kHz
RAB = 10 kΩ
RAB = 100 kΩ
VA = 5 V, VB = 0 V, from
zero scale to full scale,
±0.5 LSB error band
RAB = 10 kΩ
RAB = 100 kΩ
RAB = 10 kΩ
RAB = 100 kΩ
THD
eN_WB
tS
Crosstalk (CW1/CW2)
CT
Analog Crosstalk
Endurance 10
CTA
Min
TA = 25°C
Typ 1
Unit
3
0.43
MHz
MHz
−80
−90
dB
dB
7
20
nV/√Hz
nV/√Hz
2
12
10
25
−90
1
µs
µs
nV-sec
nV-sec
dB
Mcycles
kcycles
Years
100
Data Retention 11, 12
Max
50
Typical values represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.
Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB.
3
Guaranteed by design and characterization, not subject to production test.
4
INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6
Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7
Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8
PDISS is calculated from (IDD × VDD).
9
All dynamic characteristics use VDD/VSS = ±2.5 V.
10
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11
Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
12
50 years applies to an endurance of 1k cycles. An endurance of 100k cycles will have an equivalent retention lifetime of 5 years.
1
2
Rev. B | Page 5 of 28
AD5123/AD5143
Data Sheet
ELECTRICAL CHARACTERISTICS—AD5143
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution
Resistor Integral Nonlinearity 2
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance3
Bottom Scale or Top Scale
Nominal Resistance Match
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity 4
Differential Nonlinearity4
Full-Scale Error
Zero-Scale Error
Voltage Divider Temperature
Coefficient3
Symbol
Test Conditions/Comments
N
R-INL
Min
Typ 1
Max
8
RAB = 10 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
RAB = 100 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
R-DNL
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
Unit
Bits
−2
−5
±0.2
±1.5
+2
+5
LSB
LSB
−1
−2
−0.5
−8
±0.1
±0.5
±0.2
±1
35
+1
+2
+0.5
+8
LSB
LSB
LSB
%
ppm/°C
55
130
125
400
Ω
Ω
−1
40
60
±0.2
80
230
+1
Ω
Ω
%
RAB = 10 kΩ
RAB = 100 kΩ
−1
−0.5
−0.5
±0.2
±0.1
±0.2
+1
+0.5
+0.5
LSB
LSB
LSB
RAB = 10 kΩ
RAB = 100 kΩ
−2.5
−1
−0.1
±0.2
+1
LSB
LSB
Code = full scale
Code = zero scale
RAB = 10 kΩ
RAB = 100 kΩ
RBS or RTS
RAB = 10 kΩ
RAB = 100 kΩ
Code = 0xFF
RAB1/RAB2
INL
DNL
VWFSE
VWZSE
(ΔVW/VW)/ΔT × 106
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale
Rev. B | Page 6 of 28
1.2
0.5
±5
3
1
LSB
LSB
ppm/°C
Data Sheet
Parameter
RESISTOR TERMINALS
Maximum Continuous Current
Terminal Voltage Range 5
Capacitance A, Capacitance B3
Capacitance W3
Common-Mode Leakage Current3
DIGITAL INPUTS
Input Logic3
High
Low
Input Hysteresis3
Input Current3
Input Capacitance3
DIGITAL OUTPUTS
Output High Voltage3
Output Low Voltage3
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
EEPROM Store Current3, 6
EEPROM Read Current3, 7
Power Dissipation 8
Power Supply Rejection Ratio
AD5123/AD5143
Symbol
Test Conditions/Comments
Min
RAB = 10 kΩ
RAB = 100 kΩ
−6
−1.5
VSS
Typ 1
Max
Unit
+6
+1.5
VDD
mA
mA
V
IA, IB, and IW
CA, CB
CW
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ
RAB = 100 kΩ
VA = V W = V B
VINH
VINL
VHYST
IIN
CIN
VOH
VOL
−500
25
12
pF
pF
12
5
±15
pF
pF
nA
+500
0.7 × VDD
0.2 × VDD
0.1 × VDD
±1
5
RPULL-UP = 2.2 kΩ to VDD
ISINK = 3 mA
ISINK = 6 mA
VDD
−1
0.4
0.6
+1
V
V
V
µA
pF
5.5
±2.75
V
V
5.5
µA
nA
µA
mA
µA
µW
dB
2
VSS = GND
IDD
ISS
IDD_EEPROM_STORE
IDD_EEPROM_READ
PDISS
PSRR
VIH = VDD or VIL = GND
VDD = 5.5 V
VDD = 2.3 V
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
∆VDD/∆VSS = VDD ± 10%,
code = full scale
Rev. B | Page 7 of 28
2.3
±2.25
−5.5
0.7
400
−0.7
2
320
3.5
−66
V
V
V
µA
pF
−60
AD5123/AD5143
Parameter
DYNAMIC CHARACTERISTICS 9
Bandwidth
Total Harmonic Distortion
Resistor Noise Density
VW Settling Time
Data Sheet
Symbol
Test Conditions/Comments
BW
−3 dB
RAB = 10 kΩ
RAB = 100 kΩ
VDD/VSS = ±2.5 V, VA = 1 V rms,
VB = 0 V, f = 1 kHz
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale, TA = 25°C,
f = 10 kHz
RAB = 10 kΩ
RAB = 100 kΩ
VA = 5 V, VB = 0 V, from
zero scale to full scale,
±0.5 LSB error band
RAB = 10 kΩ
RAB = 100 kΩ
RAB = 10 kΩ
RAB = 100 kΩ
THD
eN_WB
tS
Crosstalk (CW1/CW2)
CT
Analog Crosstalk
Endurance 10
CTA
Min
TA = 25°C
Typ 1
Unit
3
0.43
MHz
MHz
−80
−90
dB
dB
7
20
nV/√Hz
nV/√Hz
2
12
10
25
−90
1
µs
µs
nV-sec
nV-sec
dB
Mcycles
kcycles
Years
100
Data Retention 11,12
Max
50
Typical values represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.
Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB.
3
Guaranteed by design and characterization, not subject to production test.
4
INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6
Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7
Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8
PDISS is calculated from (IDD × VDD).
9
All dynamic characteristics use VDD/VSS = ±2.5 V.
10
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11
Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
12
50 years applies to an endurance of 1k cycles. An endurance of 100k cycles will have an equivalent retention lifetime of 5 years.
1
2
Rev. B | Page 8 of 28
Data Sheet
AD5123/AD5143
INTERFACE TIMING SPECIFICATIONS
VDD = 2.3 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. I2C Interface
Parameter 1
fSCL 2
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t11A
t12
tSP 3
tEEPROM_PROGRAM 4
tEEPROM_READBACK
tPOWER_UP 5
tRESET
Test Conditions/Comments
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Min
Fast mode
Standard mode
Fast mode
Fast mode
20 + 0.1 CL
Typ
4.0
0.6
4.7
1.3
250
100
0
0
4.7
0.6
4
0.6
4.7
1.3
4
0.6
Max
100
400
3.45
0.9
1000
300
300
300
1000
300
1000
20 + 0.1 CL
20 + 0.1 CL
20 + 0.1 CL
20 + 0.1 CL
0
15
7
30
300
300
300
50
50
30
75
Unit
kHz
kHz
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
µs
µs
Description
Serial clock frequency
SCL high time, tHIGH
SCL low time, tLOW
Data setup time, tSU; DAT
Data hold time, tHD; DAT
Setup time for a repeated start condition, tSU; STA
Hold time (repeated) for a start condition, tHD; STA
Bus free time between a stop and a start condition, tBUF
Setup time for a stop condition, tSU; STO
Rise time of SDA signal, tRDA
Fall time of SDA signal, tFDA
Rise time of SCL signal, tRCL
Rise time of SCL signal after a repeated start condition
and after an acknowledge bit, tRCL1 (not shown in Figure 3)
Fall time of SCL signal, tFCL
Pulse width of suppressed spike (not shown in Figure 3)
Memory program time (not shown in Figure 3)
Memory readback time (not shown in Figure 3)
Power-on EEPROM restore time (not shown in Figure 3)
Reset EEPROM restore time (not shown in Figure 3)
Maximum bus capacitance is limited to 400 pF.
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the
EMC behavior of the device.
3
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
4
EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
5
Maximum time after VDD − VSS is equal to 2.3 V.
1
2
Rev. B | Page 9 of 28
AD5123/AD5143
Data Sheet
SHIFT REGISTER AND TIMING DIAGRAMS
C3
C2
C1
C0
A3
A2
A1
DB8
DB7
A0
D7
DB0 (LSB)
D6
D5
D4
D3
D2
D1
D0
10878-002
DB15 (MSB)
DATA BITS
CONTROL BITS
ADDRESS BITS
Figure 2. Input Shift Register Contents
t11
t12
t6
t8
t2
SCL
t5
t1
t6
t4
t10
t3
t9
t7
P
S
S
Figure 3. I2C Serial Interface Timing Diagram (Typical Write Sequence)
Rev. B | Page 10 of 28
P
10878-003
SDA
Data Sheet
AD5123/AD5143
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to GND
VSS to GND
VDD to VSS
VA, VW, VB to GND
Rating
−0.3 V to +7.0 V
+0.3 V to −7.0 V
7V
VSS − 0.3 V, VDD + 0.3 V or
+7.0 V (whichever is less)
IA, IW, IB
Pulsed1
Frequency > 10 kHz
RAW = 10 kΩ
RAW = 100 kΩ
Frequency ≤ 10 kHz
RAW = 10 kΩ
RAW = 100 kΩ
Digital Inputs
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is defined by the JEDEC JESD51 standard, and the value is
dependent on the test board and test environment.
±6 mA/d2
±1.5 mA/d2
3
A
Operating Temperature Range, T
Maximum Junction Temperature,
TJ Maximum
Storage Temperature Range
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Package Power Dissipation
FICDM
Table 6. Thermal Resistance
Package Type
16-Lead LFCSP
±6 mA/√d2
±1.5 mA/√d2
−0.3 V to VDD + 0.3 V or
+7 V (whichever is less)
−40°C to +125°C
150°C
1
θJA
89.51
JEDEC 2S2P test board, still air (0 m/sec airflow).
ESD CAUTION
−65°C to +150°C
260°C
20 sec to 40 sec
(TJ max − TA)/θJA
1.5 kV
1
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
d = pulse duty factor.
3
Includes programming of EEPROM memory.
Rev. B | Page 11 of 28
θJC
3
Unit
°C/W
AD5123/AD5143
Data Sheet
13 SCL
A2 7
10 W4
9 B2
W2 8
B3 5
TOP VIEW
(Not to Scale)
12 VDD
11 B4
NOTES
1. INTERNALLY CONNECT THE
EXPOSED PAD TO VSS.
10878-004
14 SDA
16 GND
B1 3
W3 4
AD5123/
AD5143
VSS 6
A1 1
W1 2
15 ADDR
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
A1
W1
B1
W3
B3
VSS
A2
W2
B2
W4
B4
VDD
SCL
SDA
ADDR
GND
EPAD
Description
Terminal A of RDAC1. VSS ≤ VA ≤ VDD.
Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD.
Terminal B of RDAC1. VSS ≤ VB ≤ VDD.
Wiper Terminal of RDAC3. VSS ≤ VW ≤ VDD.
Terminal B of RDAC3. VSS ≤ VB ≤ VDD.
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Terminal A of RDAC2. VSS ≤ VA ≤ VDD.
Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD.
Terminal B of RDAC2. VSS ≤ VB ≤ VDD.
Wiper Terminal of RDAC4. VSS ≤ VW ≤ VDD.
Terminal B of RDAC4. VSS ≤ VB ≤ VDD.
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Serial Clock Line. Data is clocked in at the logic low transition.
Serial Data Input/Output.
Programmable Address for Multiple Package Decoding.
Ground Pin, Logic Ground Reference.
Internally Connect the Exposed Paddle to VSS.
Rev. B | Page 12 of 28
Data Sheet
AD5123/AD5143
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.4
0.3
0.1
0
R-DNL (LSB)
0.2
R-INL (LSB)
0.2
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
0.1
0
–0.1
–0.1
–0.2
–0.3
–0.2
–0.4
–0.5
–0.4
0
100
200
CODE (Decimal)
–0.6
10878-005
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
0
0.20
0.10
0.15
0.05
0
R-DNL (LSB)
0.05
0
–0.05
–0.10
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
–0.20
0
–0.10
–0.15
–0.20
–0.25
50
–0.30
10878-006
–0.15
–0.05
100
CODE (Decimal)
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
0
100
Figure 9. R-DNL vs. Code (AD5123)
0.10
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
0.2
50
CODE (Decimal)
Figure 6. R-INL vs. Code (AD5123)
0.3
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
0.05
0
DNL (LSB)
0.1
0
–0.1
–0.05
–0.10
–0.15
–0.20
–0.2
0
100
CODE (Decimal)
200
10878-007
–0.3
–0.25
Figure 7. INL vs. Code (AD5143)
–0.30
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
0
100
CODE (Decimal)
Figure 10. DNL vs. Code (AD5143)
Rev. B | Page 13 of 28
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
200
10878-010
R-INL (LSB)
200
Figure 8. R-DNL vs. Code (AD5143)
0.10
INL (LSB)
100
CODE (Decimal)
Figure 5. R-INL vs. Code (AD5143)
–0.25
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
10878-009
–0.5
10878-008
–0.3
AD5123/AD5143
Data Sheet
0.15
0.06
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
0.10
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
0.02
0
0.05
–0.02
DNL (LSB)
INL (LSB)
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
0.04
0
–0.04
–0.06
–0.05
–0.08
–0.10
–0.10
50
0
–0.14
10878-011
–0.15
100
CODE (Decimal)
0
50
450
10kΩ
100kΩ
400
RHEOSTAT MODE TEMPERATURE
COEFFICIENT (ppm/°C)
350
300
250
200
150
100
50
350
300
250
200
150
100
50
0
50
100
150
200
255
AD5143
25
50
75
CODE (Decimal)
100
127
AD5123
–50
10878-012
0
0
Figure 12. Potentiometer Mode Temperature Coefficient ((ΔVW/VW)/ΔT × 106) vs.
Code
800
700
IDD,
IDD,
IDD,
VDD = 2.3V
VDD = 3.3V
VDD = 5V
0
50
100
150
200
255
AD5142A
0
25
50
75
CODE (Decimal)
100
127
AD5122A
Figure 15. Rheostat Mode Temperature Coefficient ((ΔRWB/RWB)/ΔT × 106)
vs. Code
1200
VSS = GND
VDD
VDD
VDD
VDD
1000
= 2.3V
= 3.3V
= 5V
= 5.5V
IDD CURRENT (µA)
500
400
300
800
600
400
200
200
100
0
–40
10
60
TEMPERATURE (°C)
110
125
10878-013
CURRENT (nA)
600
Figure 13. Supply Current vs. Temperature
0
0
1
2
3
4
INPUT VOLTAGE (V)
Figure 16. IDD Current vs. Digital Input Voltage
Rev. B | Page 14 of 28
5
10878-015
0
–50
10878-016
POTENTIOMETER MODE TEMPERATURE
COEFFICIENT (ppm/°C)
Figure 14. DNL vs. Code (AD5123)
100kΩ
10kΩ
400
100
CODE (Decimal)
Figure 11. INL vs. Code (AD5123)
450
10878-014
–0.12
Data Sheet
AD5123/AD5143
10
0
0x80 (0x40)
0
–10 0x40 (0x20)
0x20 (0x10)
0x20 (0x10)
–20 0x10 (0x08)
0x8 (0x04)
GAIN (dB)
GAIN (dB)
–20 0x10 (0x08)
0x8 (0x04)
–30
0x80 (0x40)
–10 0x40 (0x20)
0x4 (0x02)
0x2 (0x01)
–40 0x1 (0x00)
–30 0x4 (0x02)
–40
–50
0x2 (0x01)
0x1 (0x00)
0x00
–60
0x00
–70
–50
–80
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
–90
10
10878-017
–60
10
100
–50
0
10M
10kΩ
100kΩ
–10
–20
–60
–30
THD + N (dB)
THD + N (dB)
1M
Figure 20. 100 kΩ Gain vs. Frequency and Code
10kΩ
100kΩ
VDD/VSS = ±2.5V
VA = 1V rms
VB = GND
CODE = HALF SCALE
NOISE FILTER = 22kHz
100k
FREQUENCY (Hz)
Figure 17. 10 kΩ Gain vs. Frequency and Code
–40
10k
1k
10878-020
AD5143 (AD5123)
AD5143 (AD5123)
–70
–80
–40
–50
–60
–70
VDD/VSS = ±2.5V
–100
20
200
2k
20k
200k
FREQUENCY (Hz)
10878-018
–80
Figure 18. Total Harmonic Distortion Plus Noise (THD + N) vs. Frequency
CODE = HALF SCALE
NOISE FILTER = 22kHz
–90
0.001
0.01
1
Figure 21. Total Harmonic Distortion Plus Noise (THD + N) vs. Amplitude
10
VDD/VSS = ±2.5V
RAB = 10kΩ
0
0
–10
–20
PHASE (Degrees)
–20
–40
–60
–30
–40
–50
–60
–70
QUARTER SCALE
MIDSCALE
FULL-SCALE
100
1k
–80
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 19. Normalized Phase Flatness vs. Frequency, RAB = 10 kΩ
–90
10
QUARTER SCALE
MIDSCALE
FULL-SCALE
100
VDD/VSS = ±2.5V
RAB = 100kΩ
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 22. Normalized Phase Flatness vs. Frequency, RAB = 100 kΩ
Rev. B | Page 15 of 28
10878-022
–80
10878-019
PHASE (Degrees)
0.1
VOLTAGE (V rms)
20
–100
10
fIN = 1kHz
10878-021
–90
AD5123/AD5143
Data Sheet
300
200
0.8
0.0015
0.6
0.0010
0.4
0.0005
0.2
100
0
0
0
1
2
3
4
–600 –500 –400 –300 –200 –100
10878-023
0
5
VOLTAGE (V)
0
10kΩ + 0pF
10kΩ + 75pF
10kΩ + 150pF
10kΩ + 250pF
100kΩ + 0pF
100kΩ + 75pF
100kΩ + 150pF
100kΩ + 250pF
200
300
400
500
600
VDD = 5V ±10% AC
VSS = GND, VA = 4V, VB = GND
CODE = MIDSCALE
–20
–30
6
5
4
–40
–50
2
–70
1
–80
20
40
0
10
20
80
100
120 AD5143
40
30
CODE (Decimal)
50
60
60
AD5123
–90
10
10878-024
0
100k
1M
10M
0.020
0.015
RELATIVE VOLTAGE (V)
0.6
0.5
0.4
0.3
0.2
0.1
0.010
0.005
0
–0.005
–0.010
5
10
TIME (µs)
15
10878-025
0
Figure 25. Maximum Transition Glitch
–0.020
0
500
1000
1500
TIME (ns)
Figure 28. Digital Feedthrough
Rev. B | Page 16 of 28
2000
10878-028
–0.015
0
–0.1
10k
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency
0x80 TO 0x7F 100kΩ
0x80 TO 0x7F 10kΩ
0.7
1k
FREQUENCY (Hz)
Figure 24. Maximum Bandwidth vs. Code and Net Capacitance
0.8
100
10878-027
–60
3
0
RELATIVE VOLTAGE (V)
10kΩ, RDAC1
100kΩ, RDAC1
–10
PSRR (dB)
BANDWIDTH (MHz)
7
100
Figure 26. Resistor Lifetime Drift
10
8
0
RESISTOR DRIFT (ppm)
Figure 23. Incremental Wiper On Resistance vs. Positive Power Supply (VDD)
9
CUMULATIVE PROBABILITY
400
1.0
0.0020
PROBABILITY DENSITY
WIPER ON RESISTANCE (Ω)
500
1.2
0.0025
100kΩ, V DD = 2.3V
100kΩ, V DD = 2.7V
100kΩ, V DD = 3V
100kΩ, V DD = 3.6V
100kΩ, V DD = 5V
100kΩ, V DD = 5.5V
10kΩ, VDD = 2.3V
10kΩ, VDD = 2.7V
10kΩ, VDD = 3V
10kΩ, VDD = 3.6V
10kΩ, VDD = 5V
10kΩ, VDD = 5.5V
10878-026
600
Data Sheet
0
AD5123/AD5143
7
10kΩ
100kΩ
SHUTDOWN MODE ENABLED
6
THEORETICAL IMAX (mA)
–20
–60
–80
5
4
3
2
10kΩ
–100
1
100kΩ
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 29. Shutdown Isolation vs. Frequency
0
0
0
50
25
150
100
50
75
CODE (Decimal)
200
100
250 AD5143
125 AD5123
Figure 30. Theoretical Maximum Current vs. Code
Rev. B | Page 17 of 28
10878-030
–120
10
10878-029
GAIN (dB)
–40
AD5123/AD5143
Data Sheet
TEST CIRCUITS
Figure 31 to Figure 35 define the test conditions used in the Specifications section.
NC
VA
IW
V+ = VDD ±10%
V+
VMS
Figure 31. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
PSRR (dB) = 20 LOG
W
B
10878-031
NC = NO CONNECT
~
A
VMS
0.1V
ISW
CODE = 0x00
RSW =
W
V+
W
B
VMS
B
A = NC
10878-032
A
V+ = VDD
1LSB = V+/2N
Figure 32. Potentiometer Divider Nonlinearity Error (INL, DNL)
W
VW
B
RW = VMS1/IW
NC = NO CONNECT
10878-033
VMS1
+
ISW
–
VSS TO VDD
0.1V
Figure 35. Incremental On Resistance
IW = VDD/RNOMINAL
DUT
A
∆VDD%
Figure 34. Power Supply Sensitivity and
Power Supply Rejection Ratio (PSS, PSRR)
DUT
DUT
PSS (%/%) =
Figure 33. Wiper Resistance
Rev. B | Page 18 of 28
(
∆VMS
∆VDD
)
∆VMS%
10878-035
B
VDD
10878-034
DUT
A
W
Data Sheet
AD5123/AD5143
THEORY OF OPERATION
The AD5123/AD5143 digital programmable potentiometers are
designed to operate as true variable resistors for analog signals
within the terminal voltage range of VSS < VTERM < VDD. The resistor
wiper position is determined by the RDAC register contents. The
RDAC register acts as a scratchpad register that allows unlimited
changes of resistance settings. A secondary register (the input
register) can preload the RDAC register data.
The RDAC register can be programmed with any position setting
using the I2C interface (depending on the model). When a desirable
wiper position is found, this value can be stored in the EEPROM
memory. Thereafter, the wiper position is always restored to
that position for subsequent power-ups. The storing of EEPROM
data takes approximately 15 ms; during this time, the device is
locked and does not acknowledge any new command, preventing
any changes from taking place.
I2C SERIAL DATA INTERFACE
The AD5123/AD5143 has 2-wire, I2C-compatible serial interfaces.
These devices can be connected to an I2C bus as a slave device,
under the control of a master device. See Figure 3 for a timing
diagram of a typical write sequence.
The AD5123/AD5143 supports standard (100 kHz) and fast
(400 kHz) data transfer modes. Support is not provided for
10-bit addressing and general call addressing.
The 2-wire serial bus protocol operates as follows:
1.
RDAC REGISTER AND EEPROM
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with 0x80 (AD5143, 256 taps), the wiper is connected to
half scale of the variable resistor. The RDAC register is a standard
logic register; there is no restriction on the number of changes
allowed.
It is possible to both write to and read from the RDAC register
using the digital interface (see Table 9).
2.
The contents of the RDAC register can be stored to the EEPROM
using Command 9 (see Table 9). Thereafter, the RDAC register
always sets at that position for any future on off on power supply
sequence. It is possible to read back data saved into the EEPROM
with Command 3 (see Table 9).
3.
Alternatively, the EEPROM can be written to independently
using Command 11 (see Table 15).
INPUT SHIFT REGISTER
For the AD5123/AD5143, the input shift register is 16 bits wide,
as shown in Figure 2. The 16-bit word consists of four control
bits, followed by four address bits and by eight data bits.
If the AD5143 RDAC or EEPROM registers are read from or
written to, the lowest data bit (Bit 0) is ignored.
Data is loaded MSB first (Bit 15). The four control bits determine
the function of the software command, as listed in Table 9 and
Table 15.
The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte, which consists of the 7-bit slave address
and an R/W bit. The slave device corresponding to the
transmitted address responds by pulling SDA low during
the ninth clock pulse (this is called the acknowledge bit).
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
from, the shift register.
If the R/W bit is set high, the master reads from the slave
device. However, if the R/W bit is set low, the master writes
to the slave device.
Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL.
When all data bits have been read from or written to, a stop
condition is established. In write mode, the master pulls the
SDA line high during the tenth clock pulse to establish a stop
condition. In read mode, the master issues a no acknowledge
for the ninth clock pulse (that is, the SDA line remains high).
The master then brings the SDA line low before the tenth
clock pulse, and then high again during the tenth clock pulse
to establish a stop condition.
I2C ADDRESS
The facility to make hardwired changes to ADDR allows the
user to incorporate up to three of these devices on one bus as
outlined in Table 8.
Table 8. I2C Address Selection
ADDR Pin
VDD
No connect1
GND
1
7-Bit I2C Device Address
0101000
0101010
0101011
Not available in bipolar mode ( VSS < 0 V).
Rev. B | Page 19 of 28
AD5123/AD5143
Data Sheet
Table 9. Reduced Commands Operation Truth Table
Command
Number
0
1
Control
Bits[DB15:DB12]
C3 C2 C1 C0
0
0
0
0
0
0
0
1
Address
Bits[DB11:DB8]1
A3 A2 A1 A0
X
X
X
X
0
0
A1 A0
2
0
0
1
0
0
0
A1
3
0
0
1
1
0
0
9
10
14
15
0
0
1
1
1
1
0
1
1
1
1
0
1
1
1
0
0
0
X
A3
0
0
X
A2
1
D7
X
D7
Data Bits[DB7:DB0]1
D6 D5 D4 D3 D2 D1
X
X
X
X
X
X
D6 D5 D4 D3 D2 D1
D0
X
D0
A0
D7
D6
D5
D4
D3
D2
D1
D0
A1
A0
X
X
X
X
X
X
D1
D0
A1
A1
X
A1
A0
A0
X
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
X
D0
Operation
NOP: do nothing
Write contents of serial register
data to RDAC
Write contents of serial register
data to input register
Read back contents
D1
D0
Data
0
1
EEPROM
1
1
RDAC
Copy RDAC register to EEPROM
Copy EEPROM into RDAC
Software reset
Software shutdown
D0
Condition
0
Normal mode
1
Shutdown mode
X means don’t care.
Table 10. Reduced Address Bits Table
A3
1
0
0
0
0
1
A2
X1
0
0
0
0
A1
X1
0
0
1
1
A0
X1
0
1
0
1
Channel
All channels
RDAC1
RDAC2
RDAC3
RDAC4
X means don’t care.
Rev. B | Page 20 of 28
Stored Channel Memory
Not applicable
RDAC1
RDAC2
RDAC3
RDAC4
Data Sheet
AD5123/AD5143
ADVANCED CONTROL MODES
Low Wiper Resistance Feature
The AD5123/AD5143 digital potentiometers include a set of user
programming features to address the wide number of applications
for these universal adjustment devices (see Table 15 and Table 17).
The AD5123/AD5143 include two commands to reduce the wiper
resistance between the terminals when the devices achieve full scale
or zero scale. These extra positions are called bottom scale, BS, and
top scale, TS. The resistance between Terminal A and Terminal W
at top scale is specified as RTS. Similarly, the bottom scale resistance
between Terminal B and Terminal W is specified as RBS.
Key programming features include the following:
•
•
•
•
•
•
•
•
Input register
Linear gain setting mode
Low wiper resistance feature
Linear increment and decrement instructions
±6 dB increment and decrement instructions
Burst mode (I2C only)
Reset
Shutdown mode
The contents of the RDAC registers are unchanged by entering
in these positions. There are three ways to exit from top scale
and bottom scale: by using Command 12 or Command 13
(see Table 15); by loading new data in an RDAC register, which
includes increment/decrement operations; or by entering
shutdown mode, Command 15 (see Table 15).
Input Register
The AD5123/AD5143 include one input register per RDAC
register. These registers allow preloading of the value for the
associated RDAC register. These registers can be written to using
Command 2 and read back using Command 3 (see Table 15).
This feature allows a synchronous and asynchronous update of
one or all of the RDAC registers at the same time.
The transfer from the input register to the RDAC register is
done synchronously by Command 8 (see Table 15).
If new data is loaded in an RDAC register, this RDAC register
automatically overwrites the associated input register.
Table 11 and Table 12 show the truth tables for the top scale
position and the bottom scale position, respectively, when the
potentiometer or linear gain setting mode is enabled.
Table 11. Top Scale Truth Table
Linear Gain Setting Mode
RAW
RWB
RAB
RAB
RAW
RTS
Potentiometer Mode
RWB
RAB
Table 12. Bottom Scale Truth Table
Linear Gain Setting Mode
RAW
RWB
RTS
RBS
RAW
RAB
Potentiometer Mode
RWB
RBS
Linear Gain Setting Mode
Linear Increment and Decrement Instructions
The patented architecture of the AD5123/AD5143 allows the
independent control of each string resistor, RAW, and RWB. To enable
linear gain setting mode, use Command 16 (see Table 15) to set
Bit D2 of the control register (see Table 17).
The increment and decrement commands (Command 4 and
Command 5 in Table 15) are useful for linear step adjustment
applications. These commands simplify microcontroller software
coding by allowing the controller to send an increment or
decrement command to the device. The adjustment can be
individual or in a ganged potentiometer arrangement, where all
wiper positions are changed at the same time.
This mode of operation can control the potentiometer as two
independent rheostats connected at a single point, W terminal,
as opposed to potentiometer mode where each resistor is
complementary, RAW = RAB − RWB.
This mode enables a second input and an RDAC register per
channel, as shown in Table 16; however, the actual RDAC
contents remain unchanged. The same operations are valid
for potentiometer and linear setting gain modes. The devices
restore in potentiometer mode after a reset or power-up.
For an increment command, executing Command 4 automatically
moves the wiper to the next resistance RDAC position. This
command can be executed in a single channel or multiple channels.
Rev. B | Page 21 of 28
AD5123/AD5143
Data Sheet
±6 dB Increment and Decrement Instructions
Reset
Two programming instructions produce logarithmic taper
increment or decrement of the wiper position control by
an individual potentiometer or by a ganged potentiometer
arrangement where all RDAC register positions are changed
simultaneously. The +6 dB increment is activated by Command 6,
and the −6 dB decrement is activated by Command 7 (see Table 15).
For example, starting with the zero-scale position and executing
Command 6 ten times moves the wiper in 6 dB steps to the fullscale position. When the wiper position is near the maximum
setting, the last 6 dB increment instruction causes the wiper to
go to the full-scale position (see Table 13).
The AD5123/AD5143 can be reset through software by executing
Command 14 (see Table 15). The reset command loads the
RDAC registers with the contents of the EEPROM and takes
approximately 30 µs. The EEPROM is preloaded to midscale at
the factory, and initial power-up is, accordingly, at midscale.
Incrementing the wiper position by +6 dB essentially doubles
the RDAC register value, whereas decrementing the wiper
position by −6 dB halves the register value. Internally, the
AD5123/AD5143 use shift registers to shift the bits left and
right to achieve a ±6 dB increment or decrement. These
functions are useful for various audio/video level adjustments,
especially for white LED brightness settings in which human
visual responses are more sensitive to large adjustments than to
small adjustments.
Table 13. Detailed Left Shift and Right Shift Functions for
the ±6 dB Step Increment and Decrement
Left Shift (+6 dB/Step)
0000 0000
0000 0001
0000 0010
0000 0100
0000 1000
0001 0000
0010 0000
0100 0000
1000 0000
1111 1111
Right Shift (−6 dB/Step)
1111 1111
0111 1111
0011 1111
0001 1111
0000 1111
0000 0111
0000 0011
0000 0001
0000 0000
0000 0000
Shutdown Mode
The AD5123/AD5143 can be placed in shutdown mode by
executing the software shutdown command, Command 15
(see Table 15), and setting the LSB (D0) to 1. This feature places
the RDAC in a zero power consumption state where the device
operates in potentiometer mode, Terminal A is open-circuited,
and the wiper, Terminal W, is connected to Terminal B; however, a
finite wiper resistance of 40 Ω is present. When the device is
configured in linear gain setting mode, the resistor addressed,
RAW or RWB, is internally place at high impedance. Table 14
shows the truth table depending on the device operating mode.
The contents of the RDAC register are unchanged by entering
shutdown mode. However, all commands listed in Table 15 are
supported while in shutdown mode. Execute Command 15 (see
Table 15) and set the LSB (D0) to 0 to exit shutdown mode.
Table 14. Truth Table for Shutdown Mode
Linear Gain Setting Mode
RAW
RWB
High impedance High impedance
Potentiometer Mode
RAW
RWB
High impedance RBS
EEPROM OR RDAC REGISTER PROTECTION
The EEPROM and RDAC registers can be protected by disabling
any update to these registers. This can be done by using software or
by using hardware. If these registers are protected by software,
set Bit D0 and/or Bit D1 (see Table 17), which protects the RDAC
and EEPROM registers independently.
When RDAC is protected, the only operation allowed is to copy
the EEPROM into the RDAC register.
Burst Mode
By enabling the burst mode, multiple data bytes can be sent to
the device consecutively. After the command byte, the device
interprets the consecutive bytes as data bytes for the command.
A new command can be sent by generating a repeat start or by a
stop and start condition.
The burst mode is activated by setting Bit D3 of the control
register (see Table 17).
Rev. B | Page 22 of 28
Data Sheet
AD5123/AD5143
Table 15. Advance Commands Operation Truth Table
Command
Number
0
1
Control
Bits[DB15:DB12]
C3
C2
C1
C0
0
0
0
0
0
0
0
1
Address
Bits[DB11:DB8]1
A3 A2 A1 A0
X
X
X
X
A3 A2 A1 A0
D7
X
D7
2
0
0
1
0
A3
A2
A1
A0
3
0
0
1
1
X
A2
A1
4
5
6
7
8
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2
9
0
1
1
1
0
10
11
0
1
1
0
1
0
1
0
12
1
0
0
13
1
0
14
15
1
1
16
1
1
D6
X
D6
Data Bits[DB7:DB0]1
D5 D4 D3 D2 D1
X
X
X
X
X
D5 D4 D3 D2 D1
D0
X
D0
D7
D6
D5
D4
D3
D2
D1
D0
A0
X
X
X
X
X
X
D1
D0
A1
A1
A1
A1
A1
A0
A0
A0
A0
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
0
X
0
A1
A0
X
X
X
X
X
X
X
1
0
0
0
0
A1
A1
A0
A0
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
0
D0
1
A3
A2
A1
A0
1
X
X
X
X
X
X
D0
0
1
A3
A2
A1
A0
0
X
X
X
X
X
X
D0
0
1
1
0
1
0
X
A3
X
A2
X
A1
X
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D0
1
0
1
X
X
X
X
X
X
X
X
D3
D2
D1
D0
Operation
NOP: do nothing
Write contents of serial
register data to RDAC
Write contents of serial
register data to input register
Read back contents
D1
D0
Data
0
0
Input register
0
1
EEPROM
1
0
Control
register
1
1
RDAC
Linear RDAC increment
Linear RDAC decrement
+6 dB RDAC increment
−6 dB RDAC decrement
Copy input register to RDAC
(software LRDAC)
Copy RDAC register to
EEPROM
Copy EEPROM into RDAC
Write contents of serial
register data to EEPROM
Top scale
D0 = 0; normal mode
D0 = 1; shutdown mode
Bottom scale
D0 = 1; enter
D0 = 0; exit
Software reset
Software shutdown
D0 = 0; normal mode
D0 = 1; device placed in
shutdown mode
Copy serial register data to
control register
X means don’t care.
Table 16. Address Bits
A3
1
0
0
0
0
0
0
0
0
1
A2
X1
0
1
0
1
0
1
0
1
A1
X1
0
0
0
0
1
1
1
1
A0
X1
0
0
1
1
0
0
1
1
Potentiometer Mode
Input Register
RDAC Register
All channels
All channels
RDAC1
RDAC1
Not applicable
Not applicable
RDAC2
RDAC2
Not applicable
Not applicable
RDAC3
RDAC3
Not applicable
Not applicable
RDAC4
RDAC4
Not applicable
Not applicable
Linear Gain Setting Mode
Input Register
RDAC Register
All channels
All channels
RWB1
RWB1
RAW1
RAW1
RWB2
RWB2
RAW2
RAW2
RWB3
RWB3
RAW3
RAW3
RWB4
RWB4
RAW4
RAW4
X means don’t care.
Rev. B | Page 23 of 28
Stored RDAC
Memory
Not applicable
RDAC1
Not applicable
RDAC2
Not applicable
RDAC3
Not applicable
RDAC4
Not applicable
AD5123/AD5143
Data Sheet
Table 17. Control Register Bit Descriptions
Bit Name
D0
D1
D2
D3
Description
RDAC register write protect
0 = wiper position frozen to value in EEPROM memory
1 = allows update of wiper position through digital interface (default)
EEPROM program enable
0 = EEPROM program disabled
1 = enables device for EEPROM program (default)
Linear setting mode/potentiometer mode
0 = potentiometer mode (default)
1 = linear gain setting mode
Burst mode
0 = disabled (default)
1 = enabled (no disable after stop or repeat start condition)
Rev. B | Page 24 of 28
Data Sheet
AD5123/AD5143
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5123/AD5143 employ a
three-stage segmentation approach, as shown in Figure 36. The
AD5123/AD5143 wiper switch is designed with the transmission
gate CMOS topology and with the gate voltage derived from
VDD and VSS.
A
The nominal resistance between Terminal A and Terminal B,
RAB, is 10 kΩ or 100 kΩ, and has 128/256 tap points accessed by
the wiper terminal. The 7-bit/8-bit data in the RDAC latch is
decoded to select one of the 128/256 possible wiper settings. The
general equations for determining the digitally programmed
output resistance between Terminal W and Terminal B are
AD5123:
RWB (D ) 
STS
D
 R AB  RW
128
From 0x00 to 0x7F
(1)
D
 R AB  RW
256
From 0x00 to 0xFF
(2)
AD5143:
RH
RWB (D ) 
RM
RH
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
RAB is the end to end resistance.
RW is the wiper resistance.
RM
RL
W
In potentiometer mode, similar to the mechanical potentiometer,
the resistance between Terminal W and Terminal A also produces
a digitally controlled complementary resistance, RWA. RWA also
gives a maximum of 8% absolute. RWA starts at the maximum
resistance value and decreases as the data loaded into the latch
increases. The general equations for this operation are
RL
7-BIT/8-BIT
ADDRESS
DECODER
RM
RH
RM
RH
SBS
AD5123:
10878-036
B
Figure 36. AD5123/AD5143 Simplified RDAC Circuit
RAW (D ) 
R AW (D ) 
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—±8% Resistor Tolerance
The AD5123/AD5143 operate in rheostat mode when only two
terminals are used as a variable resistor. The unused terminal can
be floating, or it can be tied to Terminal W, as shown in Figure 37.
A
W
B
A
W
B
Figure 37. Rheostat Mode Configuration
From 0x00 to 0xFF (4)
If the device is configured in linear gain setting mode, the
resistance between Terminal W and Terminal A is directly
proportional to the code loaded in the associate RDAC register.
The general equations for this operation are
AD5123:
R AW (D ) 
D
 R AB  RW
128
From 0x00 to 0x7F (5)
D
 R AB  RW
256
From 0x00 to 0xFF (6)
AD5143:
W
B
256  D
 RAB  RW
256
(3)
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
RAB is the end to end resistance.
RW is the wiper resistance.
R AW (D ) 
10878-037
A
From 0x00 to 0x7F
AD5143:
Top Scale/Bottom Scale Architecture
In addition, the AD5123/AD5143 include new positions to
reduce the resistance between terminals. These positions are
called bottom scale and top scale. At bottom scale, the typical
wiper resistance decreases from 130 Ω to 60 Ω (RAB = 100 kΩ).
At top scale, the resistance between Terminal A and Terminal W is
decreased by 1 LSB, and the total resistance is reduced to 60 Ω
(RAB = 100 kΩ).
128  D
 RAB  RW
128
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
RAB is the end to end resistance.
RW is the wiper resistance.
Rev. B | Page 25 of 28
AD5123/AD5143
Data Sheet
VDD
In the bottom scale condition or top scale condition, a finite total
wiper resistance of 40 Ω is present. Regardless of which setting
the device is operating in, limit the current between Terminal A
to Terminal B, Terminal W to Terminal A, and Terminal W to
Terminal B, to the maximum continuous current of ±6 mA or
to the pulse current specified in Table 5. Otherwise, degradation
or possible destruction of the internal switch contact can occur.
A
W
PROGRAMMING THE POTENTIOMETER DIVIDER
VSS
Voltage Output Operation
Figure 39. Maximum Terminal Voltages Set by VDD and VSS
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A that is proportional to the input voltage
at A to B, as shown in Figure 38.
A
VB
VOUT
B
Figure 38. Potentiometer Mode Configuration
Connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 5 V. The general equation defining the
output voltage at VW with respect to ground for any valid
input voltage applied to Terminal A and Terminal B is
VW (D) 
R (D)
RWB (D)
 VA  AW
 VB
RAB
RAB
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 39), it is
important to power up VDD first before applying any voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that VDD is powered unintentionally. The
ideal power-up sequence is VSS, VDD, digital inputs, and VA, VB,
and VW. The order of powering VA, VB, VW, and digital inputs is
not important as long as they are powered after VSS and VDD.
Regardless of the power-up sequence and the ramp rates of the
power supplies, once VDD is powered, the power-on preset
activates, which restores EEPROM values to the RDAC registers.
LAYOUT AND POWER SUPPLY BIASING
(7)
where:
RWB(D) can be obtained from Equation 1 and Equation 2.
RAW(D) can be obtained from Equation 3 and Equation 4.
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, RAW and RWB, and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
It is always a good practice to use a compact, minimum lead
length layout design. Ensure that the leads to the input are as
direct as possible with a minimum conductor length. Ground
paths must have low resistance and low inductance. It is also
good practice to bypass the power supplies with quality capacitors.
Apply low equivalent series resistance (ESR) 1 μF to 10 μF
tantalum or electrolytic capacitors at the supplies to minimize
any transient disturbance and to filter low frequency ripple.
Figure 40 illustrates the basic supply bypassing configuration
for the AD5123/AD5143.
VDD
TERMINAL VOLTAGE OPERATING RANGE
The AD5123/AD5143 are designed with internal ESD diodes for
protection. These diodes also set the voltage boundary of the
terminal operating voltages. Positive signals present on Terminal A,
Terminal B, or Terminal W that exceed VDD are clamped by the
forward-biased diode. There is no polarity constraint between VA,
VW, and VB, but they cannot be higher than VDD or lower than VSS.
Rev. B | Page 26 of 28
VSS
+
C3
10µF
C1
0.1µF
+
C4
10µF
C2
0.1µF
VDD
AD5123/
AD5143
VSS
GND
10878-040
W
10878-038
VA
10878-039
B
Figure 40. Power Supply Bypassing
Data Sheet
AD5123/AD5143
OUTLINE DIMENSIONS
PIN 1
INDICATOR
0.30
0.23
0.18
0.50
BSC
13
PIN 1
INDICATOR
16
1
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
4
8
0.25 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
08-16-2010-E
3.10
3.00 SQ
2.90
Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
AD5123BCPZ10-RL7
AD5123BCPZ100-RL7
AD5143BCPZ10-RL7
AD5143BCPZ100-RL7
EVAL-AD5143DBZ
1
2
RAB (kΩ)
10
100
10
100
Resolution
128
128
256
256
Interface
I2 C
I2 C
I2 C
I2 C
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
Evaluation Board
Package Option
CP-16-22
CP-16-22
CP-16-22
CP-16-22
Z = RoHS Compliant Part.
The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all of the available resistor value options.
Rev. B | Page 27 of 28
Branding
DGZ
DH0
DH1
DH2
AD5123/AD5143
Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2012–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10878-0-2/16(B)
Rev. B | Page 28 of 28