REVISIONS LTR DESCRIPTION DATE Prepared in accordance with ASME Y14.24 APPROVED Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV 1 PAGE 2 3 PMIC N/A PREPARED BY Phu H. Nguyen Original date of drawing YY MM DD CHECKED BY 12-04-09 4 Phu H. Nguyen APPROVED BY Thomas M. Hess SIZE A REV AMSC N/A CODE IDENT. NO. 5 6 7 8 9 10 11 12 13 14 15 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil TITLE MICROCIRCUIT, DIGITAL, 1024-POSITION, DIGITAL POTENTIOMETER WITH MAXIMUM ±1% R-TOLERANCE ERROR AND 20-TP MEMORY, MONOLITHIC SILICON DWG NO. V62/12616 16236 PAGE 1 OF 15 5962-V048-12 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 1024-position, digital potential meter with maximum ±1% R-tolerance error and 20-TP memory microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12616 - Drawing number 01 X B Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 Circuit function AD5292-EP 1024-position, digital potential meter with maximum ±1% R-tolerance error and 20-TP memory 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 14 JEDEC MO-153-AB X Package style Lead thin Shrink Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z DLA LAND AND MARITIME COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12616 PAGE 2 1.3 Absolute maximum ratings. 1/ VDD to GND ............................................................................................. VSS to GND .............................................................................................. VLOGIC to GND ......................................................................................... VDD to VSS ................................................................................................ VA, VB, VW to GND ................................................................................... Digital input and output voltage to GND .................................................. EXT_CAP voltage to GND ...................................................................... IA, IB, IW Continuous ....................................................................................... Pulsed 2/ Frequency > 10 kHz .................................................................. Frequency ≤ 10 kHz ................................................................. Operating temperature range 4/ ............................................................ Maximum Junction Temperature Range (TJ max) ................................... Storage temperature range ..................................................................... Reflow soldering Peak temperature ................................................................................ Time at peak temperature ................................................................... Package power dissipation ..................................................................... Thermal resistance Case outline Case X θJA 93 5/ θJA 20 -0.3 V to +35 V +0.3 V to -25 V -0.3 V to +7 V 35 V VSS -0.3 V, VDD + 0.3 V -0.3 V to VLOGIC + 0.3 V -0.3 V to +7 V ±3 mA ±3/d 3/ ±3/√d 3/ -55C to +125C 150C -65C to 150C 260C 20 sec to 40 sec (TJ max – TA)/θJA Unit C/W 2. APPLICABLE DOCUMENTS JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 JESD51-7 – – Registered and Standard Outlines for Semiconductor Devices High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103 North 10th Street, Suite 240–S, Arlington, VA 22201.) 1/ 2/ 3/ 4/ 5/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Maximum terminal current is bounded by the maximum current handling of the switches, maximum poser dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. Pulse duty factor. Includes programming of OTP memory. JEDEC 2S2P test board, still air (0 m/sec to 1 m/sec air flow). DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12616 PAGE 3 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.5.4 Functional block diagram. The functional block diagram shall be as shown in figure 4. 3.5.5 Shift register content. The shift register content shall be as shown in figure 5. 3.5.6 Write timing diagram. The write timing diagram shall be as shown in figure 6. 3.5.7 Read timing diagram. The read timing diagram shall be as shown in figure 7. 3.5.8 Resistor position nonlinearity error. The resistor position nonlinearity error shall be as shown in figure 8. 3.5.9 Potentiometer divider nonlinearity error. The potentiometer divider nonlinearity error shall be as shown in figure 9. 3.5.10 Wiper resistance. The wiper resistance shall be as shown in figure 10. 3.5.11 Power supply sensitivity. The power supply sensitivity shall be as shown in figure 11. 3.5.12 Gain vs frequency. The gain vs frequency shall be as shown in figure 12. 3.5.13 Common mode leakage current. The common mode leakage current shall be as shown in figure 13. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12616 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Limits Min Unit Max DC characteristics – Rheostat mode Resolution N Resistor differential nonlinearity 4/ R-DNL Resistor integral nonlinearity 4/ R-INL Nominal resistor tolerance (R-Perf mode) 5/ ∆RAB/RAB Nominal resistor tolerance (Normal mode) 6/ Resistance temperature coefficient 10 RWB, VA = NC RAB = 20 kΩ, |VDD – VSS| = 26 V to 33 V RAB = 20 kΩ, |VDD – VSS| = 26 V to 33 V 7/ Bits -1 +1 -2 +2 -3 +3 -1 +1 ∆RAB/RAB ±7 TYP 3/ (∆RAB/RAB)∆T x106 35 TYP 3/ Wiper resistance RW LSB % 100 ppm/C Ω LSB DC characteristics – Potentiometer divider mode Resolution Differential nonlinearity 8/ Integral nonlinearity 8/ Voltage divider temperature coefficient 6/ N 10 DNL -1 +1 -2.5 +2.5 INL (∆VW/VW)∆T x106 Bits Code = half scale; 5 TYP 3/ Full scale error VWFSE Code = full scale -8 +1 Zero scale error VWZSE Code = zero scale 0 10 VSS VDD ppm/C LSB Resistor terminals Terminal voltage range 9/ VA, VB, VW Capacitance A, Capacitance B 6/ Capacitance W 6/ CA, CB CW f = 1 MHz, measured to GND, code = half scale Common mode leakage current 6/ ICM VA = VB = VW V 85 TYP 3/ pF 65 TYP 3/ -120 +120 nA Digital inputs Input logic high 6/ VIH VLOGIC = 2.7 V to 5.5 V Input logic low VIL VLOGIC = 2.7 V to 5.5 V Input current IIL VIN = 0 V or VLOGIC Input capacitance 6/ CIL 6/ 2.0 V 0.8 ±1 µA 5 TYP 3/ pF See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12616 PAGE 5 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Limits Conditions 2/ Unit Min Max Digital output (SDO and RDY) Output high voltage Output low voltage 6/ VOH 6/ RPULL_UP = 2.2 kΩ to VLOGIC VLOGIC – 0.4 VOL GND + 0.4 Three state leakage current Output capacitance V -1 6/ +1 COL µA 5 TYP 3/ pF Power supplies Single supply power range VDD Dual supply power range VSS = 0 V VDD/VSS Positive supply current IDD VDD/VSS = ±16.5 V Negative supply current ISS VDD/VSS = ±16.5 V Logic supply range VLOGIC Logic supply current ILOGIC 9 33 V ±9 ±16.5 V 2 µA -2 µA 2.7 VLOGIC =5 V, VIH = 5 V or VIL = GND 5.5 V 10 µA OTP store current 6/ 10/ ILOGC_PROG VIH = 5 V or VIL = GND 25 TYP 3/ mA OTP read current 6/ 11/ ILOGIC_FUSE_READ VIH = 5 V or VIL = GND 25 TYP 3/ mA Power dissipation 12/ Power supply rejection ratio Dynamic characteristics PDISS VIH = 5 V or VIL = GND PSSR ∆VDD/∆VSS = ±15 V ±10% 110 µW 0.103 TYP 3/ %/% 8/ 13/ Bandwidth BW Total harmonic distortion VW setting time THDW ts Resistor noise density eN_WB -3 dB 520 TYP 3/ VA = 1Vrms, VB = 0, f = 1 kHz -93 TYP 3/ VA = 30 V, VB = 0 V, ±0.5 LSB error band, initial code = zero scale, board capacitance = 170 pF Code = full scale, normal mode Code = full scale, R-perf mode Code = half scale, normal mode Code = half scale, R-Perf mode Code = half scale 750 TYP 3/ 2.5 TYP 3/ 2.5 TYP 3/ 5 TYP 3/ 10 TYP 3/ ns µs µs µs nV/√Hz See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12616 PAGE 6 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Limits 15/ Conditions 14/ Min Unit Max Interface timing specifications SCLK cycle time t1 16/ 20 SCLK high time t2 10 SCLK low time t3 10 SYNC to SCLK falling edge setup time t4 10 Data setup time t5 5 Data hold timw t6 5 SCLK falling edge to SYNC rising edge t7 1 Minimum SYNC high time t8 400 17/ t9 14 t10 18/ 1 SYNC rising edge to next SCLK fall ignore RDY rising edge to SYNC falling edge SYNC rising edge to RDY fall time RDY low time, RDAC register write command execute time (R-Perf mode) RDY low time, RDAC register write command execute time (normal mode) RDY low time, memory program execute time ns t11 18/ 40 t12 18/ 2.4 µs 419 ns 8 ms Software/hardware reset 1.5 ms RDY low time, RDAC register readback execute time RDY low time, memory readback execute time t13 18/ 450 ns 1.3 ms SCLK rising edge to SDO valid t14 18/ 450 ns Minimum RESET pulse width (asynchronous) Power on OTP restore time tRESET 20 tPOWER-UP 19/ ns 2ms See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12616 PAGE 7 TABLE I. Electrical performance characteristics – Continued. 1/ 1/ 2/ 3/ 4/ 5/ 6/ 7/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. VDD = 21 V to 33 V, VSS = 0V; VDD = 10.5 V to 16.5 V, VSS = -10.5 V to -16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS, -55C < TA < +125C, unless otherwise noted. Typical values represent average readings at 25C, VDD = 15 V, VSS = -15 V, and VLOGIC = 5V. Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between RWB at code 0x00B and code 0x3FF or between RWA at code 0x3F3 and code 0x000. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V. Resistor performance mode. The terms resistor performance mode and R-Perf mode are used interchangeably. Guaranteed by design and characterization, not subject to production test. Resistor performance mode code range Resistor Tolerance per Code |VDD –VSS| = 30 V to 33V RWB RWA 1% R-Tolerance From 0x1EF to 0x3FF 2% R-Tolerance From 0x0C3 to 0x3FF 3% R-Tolerance From 0x073 to 0x3FF 8/ 9/ 10/ 11/ 12/ 13/ 14/ 15/ 16/ 17/ 18/ 19/ -55C < TA < +125C |VDD –VSS| = 26 V to 30V |VDD –VSS| = 22 V to 26V RWB RWA RWB RWA |VDD –VSS| = 21 V to 22V RWB RWA From 0x000 From 0x1F4 From 0x000 From 0x1F4 From 0x000 N/A N/A to 0x210 to 0x3FF to 0x20B to 0x3FF to 0x20B From 0x000 From 0x0E6 From 0x000 From 0x131 From 0x000 From 0x131 From 0x000 to 0x33C to 0x3FF to 0x319 to 0x3FF to 0x2CE to 0x3FF to 0x2CE From 0x000 From 0x087 From 0x000 From 0x0AF From 0x000 From 0x0AF From 0x000 to 0x38C to 0x3FF to 0x378 to 0x3FF to 0x350 to 0x3FF to 0x350 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0V. DNL specification limits of ±1 LSB maximum guaranteed monotonic operating conditions. Resistor terminal A, Resistor terminal B, and Resistor terminal W, have no limitations on polarity with respect to each other. Dual supply operation enables ground referenced bipolar signal adjustment. Different from operating current; supply current for fuse program lasts approximately 550 µs. Different from operating current; supply current for fuse read lasts approximately 550 µs. PDISS is calculated from (IDD x VDD) + (ILOGIC x VLOGIC). All dynamic characteristics use VDD = 15 V, VSS = -15 V, and VLOGIC = 5 V. VDD/VSS = ±15 V, VLOGIC = 2.7 V to 5.5 V, -55C < TA < +125C. All specifications TMIN to TMAX, unless otherwise noted. All input signal are specified with tR = tF = 1ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2. Maximum SCLK frequency is 50 MHz. Refer to t12 and t13 for RDAC register and memory commands operations. RPULL-UP = 2.2 kΩ to VLOGIC, with a capacitance load of 186 pF. Maximum time after VLOGIC is equal to 2.5 V. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12616 PAGE 8 Case X Symbol A A1 b c D Dimensions Millimeters Symbol Min Max 0.05 0.19 0.09 4.90 1.20 0.15 0.30 0.20 5.10 E E1 e L Millimeters Min Max 4.30 4.50 6.40 BSC 0.65 BSC 0.45 0.75 NOTES: 1. All linear dimensions are in millimeters. 2. Falls within JEDEC MO-153-AB-1. FIGURE 1. Case outline. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12616 PAGE 9 Case outline X Terminal Terminal symbol number 8 RESET Terminal number 1 Terminal symbol VLOGIC 2 3 VSS A 9 10 GND 4 5 W B 11 12 SCLK 6 7 VDD EXT_CAP 13 14 SDO RDY DIN SYNC FIGURE 2. Terminal connections. Terminal Number Mnemonic 1 RESET 2 VSS 3 4 5 6 7 A W B VDD EXT_CAP VLOGIC 8 9 10 GND 11 SCLK 12 SYNC DIN Case outline X Description Hardware reset pin. Refreshes the RDAC register with the contents of the 20-TP memory register. Factory default loads midscale until the first 20-TP wiper memory location programmed. RESET is activated at the logic high transition. Tie RESET to VLOGIC if not used. Negative supply. Connect to 0 V for single supply applications. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors. Terminal A of RDAC. VSS ≤ VA ≤ VDD. Wiper terminal of RDAC. VSS ≤ VW ≤ VDD. Terminal B of RDAC. VSS ≤ VB ≤ VDD. Positive power supply. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors. External Capacitor. Connect a 1 µF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥ 7 V. Logic power supply; 2.7 V to 5.5 V. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors. Ground pin, Logic ground reference. Serial data input. The AD5292-EP has a 16 bit shift register. Data is clocked into register on the falling edge of the serial clock input. Serial clock input. data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. Falling edge synchronization signal. This is the fram synchronization signal for the input data. When SYNC goes low, it enables the shift register and data is transferred in on the falling edges of the following clocks. The selected register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken high before 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. 13 SDO 14 RDY Serial data output. This open drain output requires an external pull up resistor. SDO can be used to clock data from the shift register in daisy chain mode or in readback mode. Ready Pin. This active high open drain output identifies the completion of a write or read operation to or from the RDAC register or memory. FIGURE 3. Terminal function. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12616 PAGE 10 VDD RESET POWER-ON RESET V LOGIC RDAC REGISTER SCLK SERIAL INTERFAC E SYNC DATA A OTP MEMORY BLOCK DIN W B SDO RDY VSS EXT_CAP GND FIGURE 4. Functional block diagram. FIGURE 5. Shift register content. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12616 PAGE 11 FIGURE 6. Write timing diagram, CPOL = 0, CPHA = 1. FIGURE 7. Read timing diagram, CPOL = 0, CPHA = 1. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12616 PAGE 12 FIGURE 8. Resistor position nonlinearity error (Rheostat operation; R-INL, R-DNL). FIGURE 9. Potentiometer divider Nonlinearity error (INL, DNL). RWB = . RW = FIGURE 10. Wiper resistance. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12616 PAGE 13 V+ = VDD ±10% PSRR (dB) = 20 log PSS(%%) = ∆ ∆ ∆ % ∆ % FIGURE 11. Power supply sensitive (PSS, PSRR). FIGURE 12. Gain vs Frequency. FIGURE 13. Common mode leakage current DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12616 PAGE 14 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/12616-01XB 24355 AD5292SRU-20-EP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 24355 DLA LAND AND MARITIME COLUMBUS, OHIO Source of supply Analog Devices 1 Technology Way P.O. Box 9106 Norwood, MA 02062-9106 SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12616 PAGE 15