EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/ EVAL-AD5757SDZ User Guide UG-244 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Evaluation Board for a Quad Channel, 16-Bit, Serial Input, 4 mA to 20 mA, Voltage Output DAC with Dynamic Power Control and HART Connectivity FEATURES DEVICE DESCRIPTION Full-featured evaluation board for the AD5755, AD5755-1, and AD5757 Link options PC control in conjunction with Analog Devices, Inc., system demonstration platform (SDP) PC software for control The AD5755 is a quad, voltage and current output DAC that operates with a power supply range from −26.4 V to +33 V. On-chip dynamic power control minimizes package power dissipation in current mode. This is achieved by regulating the voltage on the output driver from 7.4 V to 29.5 V. The part uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI™, MICROWIRE™, DSP, and microcontroller interface standards. The interface also features optional CRC-8 packet error checking, as well as a watchdog timer that monitors activity on the interface. GENERAL DESCRIPTION This user guide describes a full-featured evaluation board that is designed to allow the user to easily evaluate all features of the AD5755, AD5755-1, or AD5757, quad channel, 16-bit current source and voltage output DAC with dynamic power control and HART connectivity. The board can be controlled by two means: via the on-board connector (J11) or via the SDP connector (J9). The SDP board allows the evaluation board to be controlled through the USB port of a Windows® XP (SP2 or later), Windows Vista (32-bit or 64-bit), or Windows 7 (32-bit or 64-bit) based PC using the AD575X evaluation software. The AD5757 is a current output-only version of the AD5755 and is HART compatible. The AD5755-1 is identical to the AD5755 except the –VSENSE_x functionality has been removed and, instead, the device is HART compatible. For both the AD5757 and AD5755-1, each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output. EVALUATION BOARD PHOTOGRAPH Figure 1. PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. C | Page 1 of 19 UG-244 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide TABLE OF CONTENTS Features .............................................................................................. 1 Enabling the Output Correctly ....................................................7 General Description ......................................................................... 1 Changing and Reprogramming the Range ................................7 Device Description ........................................................................... 1 Clear Command ............................................................................8 Evaluation Board Photograph......................................................... 1 Control of Digital Pins ..................................................................8 Revision History ............................................................................... 2 Writing to Data Registers .............................................................8 Evaluation Board Hardware ............................................................ 3 Reading from Registers ................................................................8 Power Supplies .............................................................................. 3 Writing to the DAC Control Registers .......................................9 Link Options ................................................................................. 3 Writing to the DC-to-DC Control Register............................ 10 Output Connectors ...................................................................... 5 Writing to the Main Control Register ..................................... 10 DC-to-DC Boost .......................................................................... 5 Writing to the Slew Rate Control Register .............................. 10 Patchwork ...................................................................................... 5 Other Options ............................................................................. 11 System Demonstration Platform (SDP) .................................... 5 Status Readback .......................................................................... 11 Evaluation Board Software .............................................................. 6 Closing the Software .................................................................. 11 Software Installation .................................................................... 6 Evaluation Board Schematics and Artwork ................................ 13 Software Operation ...................................................................... 6 Ordering Information .................................................................... 18 Demonstration Mode................................................................... 7 Bill of Materials ........................................................................... 18 Selecting the Device ..................................................................... 7 Related Links ................................................................................... 18 REVISION HISTORY 12/14—Rev. B to Rev. C Added Figure 1; Renumbered Sequentially .................................. 1 Changes to Table 1 and Table 3 ....................................................... 3 Changes to Table 6, Table 7, and Table 8 ....................................... 5 Changes to Evaluation Board Software Section ........................... 6 Changes to Figure 18 ...................................................................... 14 Changes to Table 12 ........................................................................ 18 4/13—Rev. A to Rev. B Changes to Table 1 ............................................................................ 3 6/11—Rev. 0 to Rev. A Added AD5755 and AD5757 ............................................ Universal Changes to Table 2 ............................................................................ 3 Added Table 5 and Table 6; Renumbered Sequentially; Changes to Table 6, and Changes to Patchwork Section ............. 4 Changes to Bill of Materials Section and Related Links Section .............................................................................................. 15 5/11—Revision 0: Initial Version Rev. C | Page 2 of 19 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide UG-244 EVALUATION BOARD HARDWARE LINK OPTIONS POWER SUPPLIES The link options on the evaluation board should be set for the required operating setup before using the board. The functions of the link options are described in Table 4. Table 1. Power Supply Connections Connector AVDD Nominal 15 V AVSS −15 V/ +0 V AVCC 5V DVDD 3.3 V REFIN 5V Comment Positive analog supply voltage. 10.8 V to 33 V range. (Green LED D2 lights up when power is supplied to AVDD.) Negative analog supply voltage. −10.8 V to −26.4 V range, or 0 V for the AD5757 or AD5755-1 in unipolar supply mode. DC-to-dc supply voltage. 4.5 V to 5.5 V range. The AVCC input supplies all four onboard dc-to-dc blocks and may draw as much as 0.8 A peak current per channel, depending on the configuration (see the device data sheet for more information). Supplied from the SDP connector. 2.7 V to 5.5 V range. See Table 4 for selecting the reference source: the DAC internal reference, the on-board ADR02 reference, or externally provided via the REFIN input. Both analog AGND and PGND inputs are provided on the board. The PGND input is for the ground of the dc-to-dc converter circuitry, and a ground connection for the AVCC supply should be made at this point. The AGND and PGND planes are connected at one location on the evaluation board. The AGND and DGND planes are connected at one location close to the AD5755, AD5755-1, or AD5757 device. Each supply is decoupled to the relevant ground plane with 10 μF and 0.1 μF capacitors. Each device supply pin is also decoupled with a 10 μF and 0.1 μF capacitor pair to the relevant ground plane. Default Link Option Setup The default link options are listed in Table 2. Table 2. Default Link Options Link No. LK0 LK1 LK2 LK3 LK4 LK5 LK6 LK7 LK8 LK9 LK10 LK11 LK12 LK13 LK14 LK15 AD5755 Link Setup Removed Removed Inserted Inserted Inserted Inserted Inserted Inserted Inserted Inserted Inserted Inserted Removed Removed Removed Removed AD5755-1 Link Setup Removed Removed Inserted Inserted Inserted Removed Inserted Removed Inserted Removed Inserted Removed Removed Removed Removed Removed AD5757 Link Setup Removed Removed Inserted Inserted Removed Removed Removed Removed Removed Removed Removed Removed Removed Removed Removed Removed Connector J11 Pin Descriptions 2 4 6 8 10 12 1 3 5 7 9 11 09633-100 The following power supplies are required. Figure 2. Connector J11 Pin Configuration Table 3. Connector J11 Pin Descriptions1 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 1 Description DVDD DGND SYNC SCLK SDIN SDO (output) LDAC CLEAR POC (AD5755 and AD5755-1) RESET FAULT (output) ALERT (output) The SDP board must be disconnected when using the J11 connector. Rev. C | Page 3 of 19 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide PC USB PORT POWER SUPPLY INPUTS AD5755 SYSTEM DEMONSTRATION PLATFORM BOARD PIN HEADER (J11) PER-CHANNEL DC-DC CIRCUITRY 5V VOLTAGE REFERENCE AGND IOUT_C –VSENSE_C VOUT_C +VSENSE_C CHANNEL C AGND IOUT_D –VSENSE_D VOUT_D +VSENSE_D CHANNEL D AGND IOUT_A –VSENSE_A VOUT_A +VSENSE_A CHANNEL A AGND IOUT_B –VSENSE_B VOUT_B +VSENSE_B CHANNEL B EXT REF REFOUT REFIN 09633-001 UG-244 Figure 3. Evaluation Board Connection Diagram Table 4. Link Options Link No. LK0, LK1, LK2 Device All models LK3 LK4, LK6 LK10, LK8 All models AD5755, AD5755-1 LK5, LK7 LK9, LK11 AD5755 LK12, LK13, LK14, LK15 All models Description These links select the voltage reference source (only one of these should be inserted at any one time). LK0 selects the internal voltage reference of the DAC as the voltage reference source. LK1 selects an external voltage reference source that can be applied at Connector J7. LK2 selects the on-board ADR02 as the voltage reference source. The ADR02 is supplied by the AVDD supply and operates under the same input voltage range as the AVDD input of the DAC, that is 9 V to 33 V. Powers the on-board ADR02 5 V reference by connecting the AVDD supply to the ADR02 supply pin. These links connect the +VSENSE input to VOUT for Channel A, Channel B, Channel C, and Channel D, respectively. When this link is inserted, the +VSENSE input is connected directly to the VOUTx pin. When this link is removed, the +VSENSE input is left floating and should be connected to the high-side of the load resistance external to the evaluation board. These links connect the −VSENSE input to VOUT for Channel A, Channel B, Channel C, and Channel D, respectively. When this link is inserted, the −VSENSE input is connected directly to the VOUT pin. When this link is removed, the −VSENSE input is left floating and should be connected to the high-side of the load resistance external to the evaluation board. These links allow connection of an external VBOOST supply. (Remove Resistors R43, R44, R17, and R20 to use this feature.) When inserted, these connect the VBOOST pin of Channel A, Channel B, Channel C, and Channel D, respectively, to the AVDD supply. When removed, the VBOOST supplies are controlled by the dc-to-dc converter circuitry. Rev. C | Page 4 of 19 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide UG-244 OUTPUT CONNECTORS DC-TO-DC BOOST There are five connectors per channel on the evaluation board PCB. The output connectors are used as outlined in Table 5, Table 6, and Table 7. Each channel has a dc-to-dc boost converter. This consists of a Schottky diode, inductor, and a low ESR, high voltage capacitor. A low-pass RC filter is also included on a per-channel basis. Table 5. On-Board Connectors for AD5755 Table 8. DC-to-DC Circuitry Connector GND A1, B1, C1, D1 Symbol LDCDC CDCDC DDCDC RFILTER CFILTER A3, B3, C3, D3 A4, B4, C4, D4 Component XAL4040-103 GRM32ER71H475KA88L PD3S160-7 N/A N/A 410 kHz switching frequency. Consult the AD5755, AD5755-1, or AD5757 data sheet for more information on the dc-to-dc converter circuitry. A2, B2, C2, D2 A4, B3, C3, D4 A3, B4, C4, D3 LDCDC Function There is a per-channel connection to AGND. IOUT output for Channel A, Channel B, Channel C, and Channel D, respectively. CHART input for Channel A, Channel B, Channel C, and Channel D, respectively. HART signals should be capacitively coupled onto these pins as described in the AD5757 data sheet. Leave open circuit if not required. Connection to the IGATEx pin. Not used. Table 7. On-Board Connectors for AD5755-1 Connector GND A1, B1, C1, D1 A2, B2, C2, D2 A3, B3, C3, D3 A4, B4, C4, D4 Function There is a per-channel connection to AGND. IOUT output for Channel A, Channel B, Channel C, and Channel D, respectively. CHART input for Channel A, Channel B, Channel C, and Channel D, respectively. HART signals should be capacitively coupled onto these pins as described in the AD5755-1 data sheet. Leave open circuit if not required. VOUT output for Channel A, Channel B, Channel C, and Channel D, respectively. +VSENSE input for Channel A, Channel B, Channel C, and Channel D, respectively. Manufacturer Coilcraft Murata Diodes Inc. N/A N/A The LDCDC 10 μH inductor provides the best performance at the Table 6. On-Board Connectors for AD5757 Connector GND A1, B1, C1, D1 Value 10 μH 4.7 μF 0.55 VF 10 Ω 0.1 μF DDCDC RFILTER AVCC CIN CDCDC VBOOST_X CFILTER SWx 09633-002 A2, B2, C2, D2 Function There is a per-channel connection to AGND. IOUT output for Channel A, Channel B, Channel C, and Channel D, respectively. −VSENSE input for Channel A, Channel B, Channel C, and Channel D, respectively. VOUT output for Channel A, Channel B, Channel C, and Channel D, respectively. +VSENSE input for Channel A, Channel B, Channel C, and Channel D, respectively. Figure 4. DC-to-DC Converter Circuitry PATCHWORK Patchwork is included on the evaluation board near the output connectors. This is connected in rows with one row connected to AGND per channel and one row connected to IOUT per channel. All other rows are left floating. When evaluating the EVAL-AD5757SDZ, the patchwork gives access to the drain, gate and source of a discreet PMOS transistor which can be used to evaluate the IGATE functionality (only applies to AD5757). SYSTEM DEMONSTRATION PLATFORM (SDP) The evaluation board can connect to the SDP board via the J9 connector. The SDP is a hardware and software platform that provides a means to communicate from the PC to supported Analog Devices products and systems that require digital control and/or readback. The SDP has a Blackfin® (ADSPBF527) at its core. This has on-chip USB 2.0 capabilities as well as many external interface ports, such as SPI, SPORT, I2C, and a 16-bit parallel interface. See Figure 21 for connections made to the SDP board. Rev. C | Page 5 of 19 UG-244 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide EVALUATION BOARD SOFTWARE SOFTWARE INSTALLATION 2. The evaluation kit includes self-installing software on a CD. The software is compatible with Windows XP (SP2), Windows Vista (32-bit or 64-bit), and Windows 7 (32-bit or 64-bit). If the setup file does not run automatically, you can run setup.exe from the CD. If the evaluation system is not connected to the USB port when the software is launched, a connectivity error is displayed (see Figure 5). Simply connect the evaluation board to the USB port of the PC, wait a number of seconds, and click Rescan. Follow the instructions. If you click Cancel, the software enters Demonstration Mode. Install the evaluation software before connecting the evaluation board and SDP board to the USB port of the PC to ensure that the evaluation system is correctly recognized when connected to the PC. 1. 2. 3. After installation from the CD is complete, power up the evaluation board as described in the Power Supplies section. Next, connect the SDP board to the evaluation board and then to the USB port of your PC using the supplied cable. When the evaluation system is detected, proceed through any dialog boxes that appear. This finishes the installation. SOFTWARE OPERATION To launch the software, complete the following steps: 1. From the Start menu, select Analog Devices –AD575X Evaluation Software, and then select AD575X Evaluation Software. The main window of the software opens (see Figure 6). Figure 6. Main Window Rev. C | Page 6 of 19 Figure 5. Connectivity Error Alert EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide DEMONSTRATION MODE Demonstration mode is accessible when the evaluation board is not connected to the PC. It allows the user to operate the software without the evaluation board. The user will have access to the majority of the software’s features and the GUI will simulate the evaluation board. In demonstration mode, all communication to the SDP is disabled. Exit and restart the software to connect to the evaluation board. UG-244 A flowchart of enabling the output correctly is shown in Figure 9. POWER ON. STEP 1: PERFORM A SOFTWARE/HARDWARE RESET. STEP 2: WRITE TO DC-TO-DC CONTROL REGISTER TO SET DC-TO-DC CLOCK FREQUENCY, PHASE, AND MAXIMUM VOLTAGE. STEP 3: WRITE TO DAC CONTROL REGISTER. SELECT THE DAC CHANNEL AND OUTPUT RANGE. SET THE DC_DC BIT AND OTHER CONTROL BITS AS REQUIRED. SET THE INT_ENABLE BIT BUT DO NOT SELECT THE OUTEN BIT. STEP 4: WRITE TO EACH/ALL DAC DATA REGISTERS. ALLOW AT LEAST 200µs BETWEEN STEP 3 AND STEP 5 FOR REDUCED OUTPUT GLITCH. Figure 7. Evaluation Mode STEP 5: WRITE TO DAC CONTROL REGISTER. RELOAD SEQUENCE AS IN STEP 3 ABOVE. THIS TIME SELECT THE OUTEN BIT TO ENABLE THE OUTPUT. In the flow chart tab, select the main device on the board, either AD5755, AD5755-1, or AD5757, from the drop-down list (see Figure 8) to adjust the available controls accordingly. 09633-006 SELECTING THE DEVICE Figure 9. Programming Sequence for Enabling the Output Correctly CHANGING AND REPROGRAMMING THE RANGE When changing between ranges, the same sequence as described in the Enabling the Output Correctly section should be used. It is recommended to set the range to its zero point (can be midscale or zero scale) prior to disabling the output. Because the dc-to-dc converter switching frequency, maximum voltage, and phase have already been selected, there is no need to reprogram these. A flowchart of changing and reprogramming the range is shown in Figure 10. Figure 8. Device Selection ENABLING THE OUTPUT CORRECTLY CHANNEL’S OUTPUT IS ENABLED. 1. 2. 3. 4. 5. Perform a hardware or software reset after initial power-on. The dc-to-dc converter supply block must be configured. Set the dc-to-dc switching frequency, maximum output voltage allowed, and the phase that the four dc-to-dc channels clock at. Configure the DAC control register on a per channel basis. The output range is selected, and the dc-to-dc converter block is enabled (DC_DC bit). Other control bits can be configured at this point. Set the INT_ENABLE bit; however, the output enable bit (OUTEN) should not be set. Write the required code to the DAC data register. This implements a full DAC calibration internally. Allow at least 200 µs before Step 5 for reduced output glitch. Write to the DAC control register again to enable the output (set the OUTEN bit). Rev. C | Page 7 of 19 STEP 1: WRITE TO CHANNEL’S DAC DATA REGISTER. SET THE OUTPUT TO 0V (ZERO OR MIDSCALE). STEP 2: WRITE TO DAC CONTROL REGISTER. DISABLE THE OUTPUT (OUTEN = 0), AND SET THE NEW OUTPUT RANGE. KEEP THE DC_DC BIT AND THE INT_ENABLE BIT SET. STEP 3: WRITE VALUE TO THE DAC DATA REGISTER. STEP 4: WRITE TO DAC CONTROL REGISTER. RELOAD SEQUENCE AS IN STEP 2 ABOVE. THIS TIME SELECT THE OUTEN BIT TO ENABLE THE OUTPUT. Figure 10. Steps for Changing the Output Range 09633-007 To correctly write to and set up the part from a power-on condition, use the following sequence. UG-244 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide CLEAR COMMAND WRITING TO DATA REGISTERS To clear an output, each relevant channel must have its clear code set in the relevant data register (default of 0x0000) and be enabled for clear operation via the DAC control registers. After these are set, assert the CLEAR pin to clear the selected channels. This function allows you to write to all the data registers. Select the register to write to from the pull-down menu, enter the 16-bit data-word to be written (in hexadecimal) and click WRITE to load data to the register (see Figure 12). Note that the effect of the gain and offset register values on the output is only seen once the data register is written to. CONTROL OF DIGITAL PINS The RESET, LDAC, POC, and CLR pins can all be controlled by selecting HIGH/LOW in the relevant boxes shown in Figure 11. The FAULT and ALERT lights display the status of their respective pins. The FAULT and ALERT pins of the device are polled by the evaluation software every ~100 ms. The FAULT pin is also connected to the reference LED, D1, on the evaluation board, and ALERT is connected to the orange LED, D14. READING FROM REGISTERS This function allows you to read from all the data registers, control registers, and the status register. Select the register to read from the pull-down menu and click READ (see Figure 12). The 16 bits of LSB data appear in the number box in hexadecimal format. This function is unavailable in demonstration mode. Figure 11. Digital Pin Controls and Indicators in the Evaluation Software Figure 12. Write to/Read From Data Register in the Evaluation Software Rev. C | Page 8 of 19 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide UG-244 WRITING TO THE DAC CONTROL REGISTERS This function allows you to write to and configure the DAC control register for a selected channel. Select the required DAC channel to be configured from the tab menu. After configuring the settings you require, click WRITE TO CH A CTRL REG to write to the device. The menu selection is shown in Figure 13. Table 9. DAC Control Register Functions Option INT_ENABLE EN Clear EN Output (OUTEN) Rset EN DC-DC Over-Range Output Range Description Powers up internal amplifiers. This should be done when enabling the output. Selects if the channel clears when the CLEAR pin is activated. Enables/disables the selected output channel. Selects whether internal or external sense resistor is used when using a current range. Powers up/down the dc-to-dc converter on a selected channel. To correctly power down the dc-to-dc converter, EN Output (OUTEN) and INT_ENABLE must also be disabled. Enables/disables 20% overrange. This is available on VOUT ranges only. Selects the output range for the specified channel. Figure 13. Write to the DAC Control Registers in the Evaluation Software Rev. C | Page 9 of 19 UG-244 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide WRITING TO THE DC-TO-DC CONTROL REGISTER The dc-to-dc control register function is located in the Control Registers tab (Figure 14). This function allows you to write to and configure the dc-to-dc control register. Select the required clamp voltage, switching frequency, and phase from the pulldown menu and click the WRITE TO DC-DC CONTROL REGISTER button to write the selected data to the device. On the evaluation board, the dc-to-dc converter perform best at a 410 kHz switching frequency (see the DC-to-DC Boost section). See the device data sheet for information on the DCDC Comp bit. If selecting an external compensation resistor, this can be placed at R12, R13, R14, and R15. WRITING TO THE MAIN CONTROL REGISTER This function allows you to write to and configure the main control register. After configuring the settings you require, click the WRITE TO MAIN CONTROL REGISTER button to write to the device. See Table 11 for main control register functions. WRITING TO THE SLEW RATE CONTROL REGISTER The slew rate control register can be accessed from the other options tab (see Figure 15). The slew rate control functions (Slew Rate Clock and Slew Rate Step) allow you to configure the slew rate on a per-channel basis. After configuring the setting you require, click WRITE to write to the device. Table 10. Slew Rate Register Functions Option Slew Rate EN Slew Rate Clock Slew Rate Step Description Enable/disable the slew rate control feature. Set the slew clock rate. Set the step size when slewing. Figure 14. Write to the DC-to-DC Control Register and Main Control Register in the Evaluation Software Table 11. Main Control Register Functions Option POC STATREAD EN Watchdog Timer (EWD) Watchdog Timeout ShtCctLim OUTEN ALL DC-DC ALL Description Determines the state of the VOUT channel when the voltage output channel is disabled during normal operation. Disabled: disabled VOUT channels goes to the function set by the POC pin. Enabled: disabled VOUT channels goes to the opposite function of the POC pin. Enable/disable status readback during a write (see the Status Readback section for details about using this feature). Enable/disable the watchdog timer (see the Writing to the Main Control Register section for details about using this feature). Select timeout period for watchdog timer (using 100 ms or 200 ms with the evaluation software recommended). Selects short-circuit current limit on the VOUT channels. Enables the output on all four DACs simultaneously. Do not use OUTEN ALL when enabling channels via the DAC control registers. When set, powers up the dc-to-dc converter on all four channels simultaneously. To power down the dc-to-dc converters, all channels outputs must first be disabled. Do not use the DC-DC ALL option when enabling the dc-to-dc converters via the DAC control registers. Rev. C | Page 10 of 19 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide UG-244 OTHER OPTIONS Click the Other Options tab shown in Figure 15 to access this feature. From this tab, the user can set the slew rate register, PEC, and user toggle bit (AD5755/AD5757 only) that is contained in the status register. A software reset can also be performed. This tab contains a feature for using the watchdog timer. By entering a value for Delay (ms), the evaluation software attempts to send the SPI code required to the software register (0x195) in approximately the time specified. Note that, because the latency of the USB connection is not strictly defined, this time delay is only a rough estimate but can be far exceeded. It is recommended to use the 100 ms or 200 ms watchdog timeouts when using this feature. PEC In packet error checking mode, only 32-bit commands are accepted. This consists of the 24 data bits and an 8-bit frame check calculated using the polynomial: AD5755-1 The AD5755-1 PEC function is activated by enabling the PEC enable bit (Bit 12 in the software register). Once enabled, each command must be 32 bits long. To activate this feature in the software, ensure that the correct product is selected from the device selection menu (see Figure 8) then click ENABLE PEC (see Figure 15). The PEC enable bit is enabled and software will now perform 32-bit writes to the device. The status of the PEC enable bit can be checked by reading the status register (Bit D11) or utilizing the STATREAD function (see the Status Readback section). Clicking the PEC enable bit once again will return the software to 24-bit write mode. The PEC enable bit will also be disabled. In this mode, the AD5755-1 will accept 24-bit writes once again. For more information, refer to the Packet Error Checking section of the respective device data sheets. C(x) = x8 + x2 + x1 + 1 STATUS READBACK AD5755 and AD5757 The AD5755 and AD5757 PEC function is activated by writing 32-bits to the device. The frame check must match the 24 data bits or the command will be ignored. To activate this feature in the software, ensure that the correct product is selected from the device selection menu (see Figure 8) then click ENABLE PEC (see Figure 15). The software will now perform 32-bit writes to the device. Clicking ENABLE PEC once again will return the software to 24-bit write mode. In this mode, the AD5755 and AD5757 will accept 24-bit writes once again. When STATREAD is enabled (see Figure 14), the status register is displayed shown in Figure 16. Note that the status register readback on a write operation reports any errors present immediately before the current write command. CLOSING THE SOFTWARE If the software is closed but the AD5755/AD5755-1/AD5757 and SDP remain powered, the evaluation board will retain the last state set by the software, with the exception of the PEC, which is disabled. Rev. C | Page 11 of 19 UG-244 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide Figure 15. Other Options in the Evaluation Software (AD5755/AD5757 Device Selected) Figure 16. Status Readback Indicator (AD5755/AD5757 Device Selected) Rev. C | Page 12 of 19 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide UG-244 09633-015 EVALUATION BOARD SCHEMATICS AND ARTWORK 09633-016 Figure 17. Main Device Circuitry Figure 18. DC-to-DC Circuitry Rev. C | Page 13 of 19 UG-244 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide GND GND AGND J3-5 AGND GND J3-5 A1 IOUTA J3-4 –VSENSEA J3-1 A2 IOUTA CHARTA-AD5755-1 /AD5757 IOUTC J3-4 –VSENSEC J3-1 C2 IOUTC CHARTC-AD5755-1 /AD5757 –VSENSEC-AD5755 –VSENSEA-AD5755 LK8 LK5 C3 A3 VOUTA J3-2 VOUTA VOUTC A4 J3-3 +VSENSEA +VSENSEA +VSENSEC J3-5 AGND GND J3-4 B2 –VSENSEB C4 J3-3 +VSENSEC J3-5 J3-1 GND D1 B1 IOUTB VOUTB GND GND AGND J3-2 LK9 LK4 IOUTD IOUTB CHARTB-AD5755-1 /AD5757 J3-4 D2 –VSENSED J3-1 IOUTD CHARTD-AD5755-1 /AD5757 –VSENSED-AD5755 –VSENSEB-AD5755 LK10 LK6 D3 B3 VOUTB J3-2 VOUTB VOUTD J3-2 VOUTD D4 J3-3 +VSENSED LK11 LK7 B4 J3-3 +VSENSEB +VSENSED Figure 19. Output (Terminal Blocks) Circuitry 09633-018 +VSENSEB GND C1 Figure 20. Supply Connections and Circuitry Rev. C | Page 14 of 19 UG-244 09633-019 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide 09633-020 Figure 21. SDP Board Connector Figure 22. Component Placement Rev. C | Page 15 of 19 09633-021 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide Figure 23. Top PCB Layer 09633-022 UG-244 Figure 24. Inner First PCB Layer Rev. C | Page 16 of 19 UG-244 09633-023 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide 09633-024 Figure 25. Inner Second PCB Layer Figure 26. Bottom PCB Layer Rev. C | Page 17 of 19 UG-244 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide ORDERING INFORMATION BILL OF MATERIALS Table 12. Qty 4 4 5 17 Part Description 10 µF, 10 V, SMD tantalum capacitor, Case A 4.7 µF, 50 V, X7R ceramic capacitor, 1210 10 µF, 50 V, X5R ceramic capacitor, 1210 0.1 µF, 50 V, X7R ceramic capacitor, 0603 Part Number TCJA106M010R0300 GRM32ER71H475KA88L UMK325BJ106MM-T MCRR25101COGJ0100 Stock Code FEC 1135234 FEC 1404215 FEC 1683595 FEC 1288255 4 4 4 1 3 4 1 2 1 1 4 16 Reference Designator C1, C42, C48, C52 C2, C32, C33, C44 C4, C6, C8, C10, C16 C3, C5, C7, C9, C11, C12, C14, C21, C22, C25, C31, C35, C39, C47, C51, C54, C55 C15, C28 to C30 C17, C19, C20, C27 C26, C37, C50, C56 D1 D2, D11, D14 J1 to J4 J5 J6, J7 J9 J11 L1 to L4 LK0 to L15 100 pF, 100 V, C0G ceramic capacitor, radial 10 nF, 50 V, X7R ceramic capacitor, 0603 10 µF, 16 V, X5R ceramic capacitor, 0805 Red, SMD LED, 0603 Green, SMD LED, 0603 5-pin terminal block (3.81 mm pitch) 3-pin terminal block (3.81 mm pitch) 2-pin terminal block (3.81 mm pitch) 120-way connector, 0.6 mm pitch 12-pin (2 × 6) 0.1" pitch header Inductor 2-pin (0.1" pitch) header and jumper socket B37979G1101J B37931K5103K60 GRM21BR61C106KE15L SML-D12U8WT86 SML-512MWT86R 3704609 1727023 1727010 FX8-120S-SV(21) M20-9980646 XAL4040-103 M20-9990246 4 1 7 1 3 4 4 3 1 R1, R2, R3, R4 R5 R6, R8, R9, R12, R13, R14, R15 R10 R11, R18, R19 R17, R20, R43, R44 SCH1 to SCH4 TP1 to TP3 U1 15 kΩ, low drift, SMD resistor, 0805 0 Ω, SMD resistor, 0603 0 Ω, SMD resistor, 0603 2.2 kΩ, SMD resistor, 0603 1 kΩ, SMD resistor, 0603 10 Ω, SMD resistor, 0603 1 A, 60 V, Schottky diode, POWERDI323 Test point Quad 16-bit DAC with dynamic power control PCF0805-13-15K-B-T1 CRCW06030000Z0EA CRCW06030000Z0EA CRCW06032K20JNEA CRCW06031K00JNEA CRCW060310R0FKEA PD3S160-7 1 1 4 U3 U4 U2, U5, U6, U7 5 V precision reference, 8-lead SOIC 32 kB I2C serial EEPROM, 8-lead MSOP MOSFET P-channel, 30 V (only populate on EVAL-AD5757 boards) FEC 1216416 FEC 753622 FEC 1762635 FEC 1685094 FEC 1685076 FEC 3704609 FEC 3704580 FEC 3704579 FEC 1324660 FEC 1022238 Coilcraft XAL4040-103 FEC 1022247 and FEC 150411 FEC 1108896 DNP FEC 1469739 FEC 1652868 FEC 1652851 FEC 1469751 FEC 1843697 DNP AD5755BCPZ AD5755-1ACPZ AD5757ACPZ ADR02BRZ FEC 1331330 Digi-Key FDMA530PZCT-ND AD5755 AD5755-1 AD5757 ADR02BRZ 24LC32A-I/MS FDMA530PZ RELATED LINKS Resource AD5755 AD5757 AD5755-1 ADR02 Description Product Page, Quad Channel, 16-Bit, Serial Input, 4 mA to 20 mA and Voltage Output DAC, Dynamic Power Control Product Page, Quad Channel, 16-Bit, Serial Input, 4 mA to 20 mA Output DAC, Dynamic Power Control, HART Connectivity Product Page, Quad Channel, 16-Bit, Serial Input, 4 mA to 20 mA and Voltage Output DAC, Dynamic Power Control, HART Connectivity Product Page, Ultracompact, Precision 5.0 V Voltage Reference Rev. C | Page 18 of 19 EVAL-AD5755SDZ/EVAL-AD5755-1SDZ/EVAL-AD5757SDZ User Guide UG-244 NOTES ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2011–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG09633-0-12/14(C) Rev. C | Page 19 of 19