Circuit Note CN-0198 Devices Connected/Referenced Circuits from the Lab™ reference circuits are engineered and tested for quick and easy system integration to help solve today’s analog, mixed-signal, and RF design challenges. For more information and/or support, visit www.analog.com/CN0198. AD5755 16-Bit Quad Channel, Voltage Output DAC with Dynamic Power Control ADP2300 700 kHz Nonsynchronous Step-Down Switching Regulator 5 V Regulator Supplies High Transient Current for Dynamic Power Controlled DAC EVALUATION AND DESIGN SUPPORT some additional headroom) to provide a sufficient voltage to drive high value resistive loads. For low value resistive loads, however, the fixed value, high voltage supply results in significant internal power dissipation that can affect DAC accuracy and require additional heat sinking. Circuit Evaluation Boards AD5755 Evaluation Board (EVAL-AD5755SDZ) System Demonstration Platform (EVAL-SDP-CB1Z) ADP2300 Evaluation Board (ADP2300-EVALZ) Design and Integration Files Schematics, Layout Files, Bill of Materials CIRCUIT FUNCTION AND BENEFITS The circuit shown in Figure 1 provides a unique power saving solution for a digital-to-analog converter (DAC)-based, 4 mA to 20 mA output circuit. To provide sufficient headroom for typical resistive loads between 10 Ω and 1000 Ω, traditional 4 mA to 20 mA output driver stages must operate on at least 20 V (plus –15V The AD5755 quad 16-bit DAC has four independent high efficiency, internal dc-to-dc converters that drive the four output stages at a dynamically adjusted boost voltage based on sensing the actual output voltage of the 4 mA to 20 mA driver. The boost circuit maintains several volts of headroom on the output stage, regardless of the load resistance, thereby reducing the maximum internal power dissipation by a factor of approximately 4× for a 24 mA output current into a 10 Ω load. +15V NOTE: x = A, B, C ,AND D ADP2300 DC-TO-DC CONVERTER CIRCUIT AVSS –15V AGND AVDD +15V AVCC 5.0V SWx DC-TO-DC CONVERTER DVDD VBOOST_x 7.4V TO 29.5V DGND LDAC SCLK SDIN SYNC DIGITAL INTERFACE SDO + CLEAR FAULT GAIN REG A OFFSET REG A ALERT AD1 DAC A CURRENT AND VOLTAGE OUTPUT RANGE SCALING IOUT_x RSET_x AD0 +VSENSE_x VOUT_x REFERENCE DAC CHANNEL A REFIN AD5755 DAC CHANNEL B DAC CHANNEL C DAC CHANNEL D –VSENSE_x 09688-001 REFOUT Figure 1. Current and Voltage Output DAC with Modified Power Scheme (Simplified Schematic: All Connections and Decoupling Not Shown) Rev. 0 Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. CN-0198 Circuit Note The entire circuit operates on ±15 V supplies that allow the DAC to provide voltage outputs that cover the industrial signal level range of up to ±10 V in addition to the 4 mA to 20 mA outputs. This combination of parts is a low cost, power efficient solution that minimizes the number of external components required and that ensures 16-bit performance for varying load conditions. CIRCUIT DESCRIPTION This circuit enhances the slew rate control and dynamic power control features of the AD5755 to create a more complete and robust DAC solution. By implementing a simple step-down dc-to-dc converter using the ADP2300, the circuit can provide higher than normal supply currents that are required when slewing the AD5755 outputs. The AD5755 behaves like any standard DAC converting digital data to analog current (for example, 0 mA to 20 mA, 4 mA to 24 mA, or 0 mA to 24 mA) or voltage outputs (0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V). The AD5755 operates with an extended AVSS power supply range to −26.4 V, and an AVDD range to +33.0 V. Power Dissipation Control In standard, current controlled module or actuator designs, the load resistor value can range from typically 50 Ω to 750 Ω, but it can be as low as 10 Ω or as high as 1 kΩ. The 4 mA to 20 mA output driver stage must operate on a supply voltage that provides sufficient headroom for the full range of the load resistor values. For example, when driving 24 mA into a 1 kΩ load, a supply voltage of greater than 27 V is required, assuming a 3 V headroom is needed. In this case, the internal package power dissipation due to the output driver is 3 V × 24 mA = 72 mW. However, when driving a 10 Ω load with the same 27 V supply voltage, the internal power dissipation of the driver is approximately 27 V × 24 mA = 648 mW. For a quad DAC, this is greater than 2.5 W. The AD5755 circuitry senses the output voltage and dynamically regulates the boost supply voltage to meet supply voltage requirements plus a sufficient amount of headroom. For 24 mA output into 10 Ω, the boost voltage of 7.4 V results in an internal power dissipation of only 7.4 V × 24 mA = 178 mW. This represents nearly a 4× reduction in power vs. the unregulated case. DC-to-DC Converters The AD5755 contains four independent, on-board dc-to-dc converters. They provide dynamic control of the VBOOST_X supply voltage for each individual channel. Figure 2 shows the discrete components needed for the dc-to-dc circuitry, and the following sections describe the operation of this circuitry. LDCDC AVCC DDCDC 10µH CIN ≥10µF CDCDC 4.7µH RFILTER 10Ω CFILTER 0.1µF SWX VBOOST_x 09688-002 The internal dc-to-dc converters require an external 5 V supply and can draw significant currents when the DAC outputs fullscale slew. A high efficiency external dc-to-dc converter circuit based on the ADP2300 is driven from the 15 V and supplies this voltage. The ADP2300 has excellent transient response to large current steps up to 800 mA and ensures proper operation of the boost converters as well as eliminating the need for a separate 5 V supply. Figure 2. DC-to-DC External Circuit It is recommended to place a 10 Ω, 100 nF low-pass RC filter after CDCDC. This consumes a small amount of power; however, it reduces the amount of ripple on the VBOOST_X supply. The suggested component values for LDCDC, CDCDC, and DDCDC are given in Table 1. Table 1. Discrete Components for DC-to-DC Converter Symbol LDCDC CDCDC DDCDC Component XAL4040-103 GRM32ER71H475KA88L PMEG3010BEA Value 10 µH 4.7 µF 0.38 VF Manufacturer Coilcraft Murata NXP DC-to-DC Converter Operation The on-board dc-to-dc converters use a constant frequency, peak current mode control scheme to step up an AVCC input of 4.5 V to 5.5 V to drive the AD5755 output channel. These are designed to operate in discontinuous conduction mode (DCM) with a duty cycle of <90% typical. Discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. The dc-to-dc converters are nonsynchronous; that is, they require an external Schottky diode. DC-to-DC Converter Output Voltage When a channel current output is enabled, the converter regulates the VBOOST_X supply to 7.4 V (±5%) or (IOUT × RLOAD + Headroom), whichever is greater. The value of the headroom voltage is approximately 3 V. In the voltage output mode with the output disabled, the converter regulates the VBOOST_X supply to +15 V (±5%). In current output mode with the output disabled, the converter regulates the VBOOST_X supply to 7.4 V (±5%). Within a channel, the VOUT_X and IOUT_X stages share a common VBOOST_X supply so that the outputs of the IOUT_X and VOUT_X stages can be tied together. A separate boost supply voltage is generated for each of the four DAC outputs by four independent dc-to-dc converters operating on a 5 V input. Rev. 0 | Page 2 of 6 Circuit Note CN-0198 DC-to-DC Converter Settling Time AVCC Supply Static Current Requirements When in current output mode, the settling time for a step greater than approximately 1 V (IOUT × RLOAD) is dominated by the settling time of the dc-to-dc converter. The exception to this is when the required voltage at the IOUT_X pin plus the compliance voltage is below 7.4 V (±5%). The settling time for smaller loads is faster. The settling time for current steps less than 24 mA is also faster. The dc-to-dc converter is designed to supply a VBOOST_X voltage of VBOOST = IOUT × RLOAD + Headroom This means that, for a fixed load and output voltage, the dc-todc converter output current can be calculated by AI CC = DC-to-DC Converter VMAX Functionality VMAX DC-DC BIT 29.5 VBOOST_x VOLTAGE (mV) 29.3 29.2 29.1 DC-DC MaxV = 29.5V ADP2300 AVCC Supply fSW = 410kHz 28.9 The ADP2300 and several discrete components are used to create a simple 5 V rail that meets the supply current demands of the AD5755 as previously described. The output voltage is set externally by a resistive voltage divider from the output voltage to the FB pin, as show in Figure 4. TA = 25°C 28.8 28.7 0.5 1.0 1.5 2.0 2.5 TIME (ms) 3.0 3.5 4.0 09688-003 DC-DCx BIT = 0 28.6 0 I OUT × VBOOST ηVBOOST × AVCC The AICC current requirement while slewing is greater than in static operation because the output power increases to charge the output capacitance of the dc-to-dc converter. If not enough AICC current is provided, the AVCC voltage drops. Due to this AVCC drop, the AICC current required to slew increases further. This means that the voltage at AVCC drops further, and the VBOOST_X voltage, and thus the output voltage, may never reach its intended value. Because this AVCC voltage is common to all channels, this may also affect other channels. 0mA TO 24mA RANGE, 24mA OUTPUT OUTPUT UNLOADED DC-DCx BIT = 1 = AVCC Supply Slewing Current Requirements- 29.4 29.0 Efficiency × AVCC where: IOUT is the output current from IOUT_X in amps. ηVBOOST is the efficiency at VBOOST_X as a fraction. The maximum VBOOST_X voltage is set in the dc-to-dc control register. On reaching this maximum voltage, the dc-to-dc converter is disabled, and the VBOOST_X voltage is allowed to decay by approximately 0.4 V. After the VBOOST_X voltage has decayed, the dc-to-dc converter is reenabled, and the voltage ramps up again to VMAX, if still required. 29.6 Power Out Figure 3. VMAX Operation As seen in Figure 3, the DC-DCx bit in the status register asserts when the AD5755 is ramping to the VMAX value and deasserts when the voltage is decaying to VMAX − 0.4 V. L1 10µH J2 VOUT C4 NC C3 22µF C1 0.1µF D1 B230A GND U1 1 BST SW 6 2 GND VIN 5 J1 R2 52.3kΩ R4 10kΩ 3 FB EN ADP2300 (700kHz) VIN C2 10µF 4 R1 10kΩ R3 1.8kΩ 1 2 3 J5 EN Figure 4. ADP2300 Typical Application (ADP2300 Evaluation Board) Rev. 0 | Page 3 of 6 J3 GND 09688-004 J4 CN-0198 Circuit Note 0.016 All test data was gathered using the EVAL-AD5755SDZ, EVAL-SDP-CB1Z, and ADP2300-EVALZ boards. The integral nonlinearity (INL), differential nonlinearity (DNL), and total unadjusted error (TUE) of the system using the ADP2300 circuit is shown in Figure 5, Figure 6, and Figure 7, respectively. The AD5755 boost regulators were active for all the measurements. 0.014 TOTAL UNADJUSTED ERROR (% FSR) Test Data and Results Complete documentation for the system can be found in the CN0198 Design Support package. 0.0015 0.010 0.008 +5V RANGE +10V RANGE ±5V RANGE ±10V RANGE 0.006 0.004 0.002 0 8 2268 4528 6788 9048 11308 13568 15828 18088 20348 22608 24868 27128 29388 31648 33908 36168 38428 40688 42948 45208 47468 49728 51988 54248 56508 58768 61028 63288 0.0005 DAC CODE 09688-007 –0.002 0.0010 INL ERROR (% FSR) 0.012 Figure 7. TUE for Voltage Outputs 0 COMMON VARIATIONS The AD5755-1 is similar to the AD5755; however, it has HART connectivity. Each channel has a corresponding CHARTx pin so that HART signals can be coupled onto the current outputs of the AD5755-1. –0.0005 +5V RANGE +10V RANGE ±5V RANGE ±10V RANGE –0.0010 09688-005 8 2538 5068 7598 10128 12658 15188 17718 20248 22778 25308 27838 30368 32898 35428 37958 40488 43018 45548 48078 50608 53138 55668 58198 60728 63258 –0.0015 DAC CODE Figure 5. INL for Voltage Outputs 0.3 0.2 This circuit uses the EVAL-AD5755SDZ circuit board and the EVAL-SDP-CB1Z System Demonstration Platform (SDP) evaluation board. The two boards have 120-pin mating connectors, allowing for the quick setup and evaluation of the performance of the circuit. The EVAL-AD5755SDZ circuit board contains the circuit to be evaluated, and the SDP evaluation board is used with the AD5755 Evaluation Software to capture data. 0.1 0 –0.1 Equipment Needed –0.2 The following equipment is needed: • A PC with a USB port and Windows® XP, Windows Vista® (32-bit), or Windows 7 (32-bit) –0.3 –0.4 +5V RANGE +10V RANGE ±5V RANGE ±10V RANGE • The EVAL-AD5755SDZ circuit board DAC CODE Figure 6. DNL for Voltage Outputs 09688-006 –0.5 8 1788 3568 5348 7128 8908 10688 12468 14248 16028 17808 19588 21368 23148 24928 26708 28488 30268 32048 33828 35608 37388 39168 40948 42728 44508 46288 48068 49848 51628 53408 55188 56968 58748 60528 62308 64088 DNL ERROR (LSB) CIRCUIT EVALUATION AND TEST • The EVAL-SDP-CB1Z SDP evaluation board • The ADP2300-EVALZ evaluation board • The AD5755 Evaluation Software • A power supply: ±15 V • A digital multimeter (that is, Agilent 34401A) • A GPIB-to-USB cable (only required for capturing analog data from the DAC and transferring it to the PC). Rev. 0 | Page 4 of 6 Circuit Note CN-0198 Getting Started With power to the supply off, do the following: Load the evaluation software by placing the AD5755 Evaluation Software CD into the PC. Using My Computer, locate the drive that contains the evaluation software CD and open the Readme file. Follow the instructions contained in the Readme file for installing and using the evaluation software. • • • Functional Block Diagram Figure 8 shows the test setup block diagram, and the EVALCN0198-SDPZ-SCH-RevX.pdf file has the circuit schematics. This file is contained in the CN0198 Design Support Package. • • ±15V POWER SUPPLY Connect a ±15 V power supply to J5 terminal block on the EVAL-AD5755SDZ. Connect a 15 V power supply to the inputs of the ADP2300-EVALZ. Connect the output pins to the J6 connector of the EVALAD5755SDZ. Connect a ±15 V power supply to the J5 connector on the EVAL-AD5755SDZ. Connect the USB cable supplied with the SDP board to the USB port on the PC. Note: Do not connect the USB cable to the mini-USB connector on the SDP board at this time. Test Apply power to the ADP2300-EVALZ and the EVAL-AD5755SDZ supplies. PC GND +15V ADP2300-EVALZ −15V +15V J5 GND Connect the USB cable from the PC to the mini-USB connector on the SDP board and launch the evaluation software. USB +5V J6 EVAL-AD5755SDZ Once USB communications are established, the SDP board can be used to send and receive data from the EVAL-AD5755SDZ. EVAL-SDP-CB1Z 120-PIN CONNECTOR 09688-008 J9 Figure 8. Photo Test Setup Block Diagram Setup Information regarding the EVAL-SDP-CB1Z can be found in the SDP User Guide. Information and details regarding test setup and how to use the evaluation software for data capture can be found in the CN-0198 User Guide. Connect the 120-pin connector on the EVAL-AD5755SDZ to the CON A connector on the EVAL-SDP-CB1Z. Used nylon hardware to firmly secure the two boards, using the holes provided at the ends of the 120-pin connectors. Rev. 0 | Page 5 of 6 Circuit Note 09688-009 CN-0198 Figure 9. Photo of the EVAL-AD5755SDZ Board LEARN MORE Data Sheets and Evaluation Boards CN0198 Design Support Package: http://www.analog.com/CN0198-DesignSupport. AD5755 Data Sheet UG-244 (EVAL-AD5755SDZ Evaluation Board User Guide). Evaluation Board for a Quad-Channel, 16-Bit, Serial Input, 4 mA to 20 mA, Voltage Output DAC with Dynamic Power Control and HART Connectivity. Analog Devices, Inc., 2011. ADP2300 Data Sheet UG-179 (ADP2300-EVALZ Evaluation Board User Guide). Evaluation Board for the 1.2 A, 20 V Nonsynchronous StepDown Regulators. Analog Devices, 2010. 12/12—Revision 0: Initial Version AD5755 Evaluation Board ADP2300 Evaluation Board REVISION HISTORY ADIsimPower MT-031 Tutorial, Grounding Data Converters and Solving the Mystery of "AGND" and "DGND", Analog Devices. MT-101 Tutorial, Decoupling Techniques, Analog Devices. (Continued from first page) Circuits from the Lab circuits are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. While you may use the Circuits from the Lab circuits in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or use of the Circuits from the Lab circuits. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the Lab circuits are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. Analog Devices reserves the right to change any Circuits from the Lab circuits at any time without notice but is under no obligation to do so. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. CN09688-0-12/12(0) Rev. 0 | Page 6 of 6