Quad-Channel, Digital Isolators, Enhanced System-Level ESD Reliability ADuM3400/ADuM3401/ADuM3402 Data Sheet FEATURES GENERAL DESCRIPTION Enhanced system-level ESD performance per IEC 61000-4-x Low power operation 5 V operation 1.4 mA per channel maximum at 0 Mbps to 2 Mbps 4.3 mA per channel maximum at 10 Mbps 34 mA per channel maximum at 90 Mbps 3 V operation 0.9 mA per channel maximum at 0 Mbps to 2 Mbps 2.4 mA per channel maximum at 10 Mbps 20 mA per channel maximum at 90 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 105°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics 2 ns maximum pulse width distortion 2 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Output enable function 16-lead SOIC wide body, RoHS-compliant package Safety and regulatory approvals UL recognition: 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 VIORM = 560 V peak The ADuM3400/ADuM3401/ADuM34021 are 4-channel digital isolators based on the Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices. APPLICATIONS General-purpose multichannel isolation SPI/data converter isolation RS-232/RS-422/RS-485 transceivers Industrial field bus isolation iCoupler devices remove the design difficulties commonly associated with optocouplers. Typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). All models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. The isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during powerup/power-down conditions. In comparison to the ADuM1400/ADuM1401/ADuM1402 isolators, the ADuM3400/ADuM3401/ADuM3402 isolators contain various circuit and layout changes to provide increased capability relative to system-level IEC 61000-4-x testing (ESD/ burst/surge). The precise capability in these tests for either set of isolators is strongly determined by the design and layout of the user’s board or module. For more information, see the AN-793 Application Note, ESD/Latch-Up Considerations with iCoupler Isolation Products. VDD1 1 16 VDD2 VDD1 1 16 VDD2 VDD1 1 16 VDD2 GND1 2 15 GND2 GND1 2 15 GND2 GND1 2 15 GND2 DECODE 14 VOA VIA 3 ENCODE DECODE 14 VOA VIA 3 ENCODE DECODE 14 VOA ENCODE DECODE 13 VOB VIB 4 ENCODE DECODE 13 VOB VIB 4 ENCODE DECODE 13 VOB VIC 5 ENCODE DECODE 12 VOC VIC 5 ENCODE DECODE 12 VOC VOC 5 DECODE ENCODE 12 VIC VID 6 ENCODE DECODE 11 VOD VOD 6 DECODE ENCODE 11 VID VOD 6 DECODE ENCODE 11 VID NC 7 10 VE2 VE1 7 10 VE2 VE1 7 GND1 8 9 GND2 Figure 1. ADuM3400 Functional Block Diagram 1 GND1 8 9 GND2 05985-002 ENCODE 05985-001 VIA 3 VIB 4 Figure 2. ADuM3401 Functional Block Diagram GND1 8 10 VE2 9 GND2 05985-003 FUNCTIONAL BLOCK DIAGRAMS Figure 3. ADuM3402 Functional Block Diagram Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2006–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuM3400/ADuM3401/ADuM3402 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ......................................................... 14 Applications ....................................................................................... 1 ESD Caution................................................................................ 14 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ......................... 15 Functional Block Diagrams ............................................................. 1 Typical Performance Characteristics ........................................... 18 Revision History ............................................................................... 2 Application Information ................................................................ 20 Specifications..................................................................................... 3 PC Board Layout ........................................................................ 20 Electrical Characteristics—5 V Operation................................ 3 System-Level ESD Considerations and Enhancements ........ 20 Electrical Characteristics—3 V Operation................................ 6 Propagation Delay-Related Parameters................................... 20 Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V Operation....................................................................................... 8 DC Correctness and Magnetic Field Immunity........................... 20 Package Characteristics ............................................................. 12 Regulatory Information ............................................................. 12 Insulation and Safety-Related Specifications .......................... 12 Power Consumption .................................................................. 21 Insulation Lifetime ..................................................................... 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics ............................................................................ 13 Recommended Operating Conditions .................................... 13 REVISION HISTORY 7/15—Rev. C to Rev. D Changes to Table 5 and Table 6 ..................................................... 12 4/14—Rev. B to Rev. C Changes to Table 5 .......................................................................... 12 2/12—Rev. A to Rev. B Created Hyperlink for Safety and Regulatory Approvals Entry in Features Section................................................................. 1 Change to PC Board Layout Section ............................................ 20 6/07—Rev. 0 to Rev. A Updated VDE Certification Throughout ...................................... 1 Changes to Features, General Description, Note 1, Figure 1, Figure 2, and Figure 3....................................................................... 1 Changes to Regulatory Information Section .............................. 12 Changes to Table 7 and Figure 4 Caption.................................... 13 Added Table 10; Renumbered Sequentially ................................ 14 Added Insulation Lifetime Section .............................................. 22 Inserted Figure 21, Figure 22, and Figure 23 .............................. 22 Changes to Ordering Guide .......................................................... 23 3/06—Revision 0: Initial Version Rev. D | Page 2 of 24 Data Sheet ADuM3400/ADuM3401/ADuM3402 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Table 1. Parameter DC SPECIFICATIONS Input Supply Current per Channel, Quiescent Output Supply Current per Channel, Quiescent ADuM3400, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current VDD2 Supply Current 90 Mbps (CRW Grade Only) VDD1 Supply Current VDD2 Supply Current ADuM3401, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current VDD2 Supply Current 90 Mbps (CRW Grade Only) VDD1 Supply Current VDD2 Supply Current ADuM3402, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 or VDD2 Supply Current 10 Mbps (BRW and CRW Grades Only) VDD1 or VDD2 Supply Current 90 Mbps (CRW Grade Only) VDD1 or VDD2 Supply Current For All Models Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages Symbol Min Typ Max Unit IDDI (Q) IDDO (Q) 0.57 0.29 0.83 mA 0.35 mA IDD1 (Q) IDD2 (Q) 2.9 1.2 3.5 1.9 IDD1 (10) IDD2 (10) 9.0 3.0 11.6 mA 5.5 mA 5 MHz logic signal freq. 5 MHz logic signal freq. IDD1 (90) IDD2 (90) 72 19 100 36 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. IDD1 (Q) IDD2 (Q) 2.5 1.6 3.2 2.4 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. IDD1 (10) IDD2 (10) 7.4 4.4 10.6 mA 6.5 mA 5 MHz logic signal freq. 5 MHz logic signal freq. IDD1 (90) IDD2 (90) 59 32 82 46 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. IDD1 (Q), IDD2 (Q) 2.0 2.8 mA DC to 1 MHz logic signal freq. IDD1 (10), IDD2 (10) 6.0 7.5 mA 5 MHz logic signal freq. IDD1 (90), IDD2 (90) 51 62 mA 45 MHz logic signal freq. µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2 IIA, IIB, IIC, IID, IE1, IE2 VIH, VEH VIL, VEL VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL −10 +0.01 +10 2.0 0.8 (VDD1 or VDD2) − 0.1 5.0 (VDD1 or VDD2) − 0.4 4.8 0.0 0.04 0.2 Rev. D | Page 3 of 24 0.1 0.1 0.4 mA mA V V V V V V V Test Conditions DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. IOx = −20 µA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 µA, VIx = VIxL IOx = 400 µA, VIx = VIxL IOx = 4 mA, VIx = VIxL ADuM3400/ADuM3401/ADuM3402 Parameter SWITCHING SPECIFICATIONS ARW Package Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |tPLH − tPHL|4 Propagation Delay Skew5 Channel-to-Channel Matching6 BRW Package Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |tPLH − tPHL|4 Change vs. Temperature Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional Channels6 Channel-to-Channel Matching, Opposing-Directional Channels6 CRW Package Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |tPLH − tPHL|4 Change vs. Temperature Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional Channels6 Channel-to-Channel Matching, Opposing-Directional Channels6 For All Models Output Disable Propagation Delay (High/Low-to-High Impedance) Output Enable Propagation Delay (High Impedance-to-High/Low) Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate Input Dynamic Supply Current per Channel8 Output Dynamic Supply Current per Channel8 Symbol Data Sheet Min Typ PW tPHL, tPLH PWD tPSK tPSKCD/OD 1 50 65 PW Max Unit Test Conditions 1000 ns Mbps 100 ns 40 ns 50 ns 50 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels 100 CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels tPSK tPSKCD 15 3 ns Mbps ns ns ps/°C ns ns tPSKOD 6 ns tPHL, tPLH PWD 10 20 32 50 3 5 PW tPSK tPSKCD 11.1 ns Mbps 32 ns 2 ns ps/°C 10 ns 2 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels tPSKOD 5 ns CL = 15 pF, CMOS signal levels tPHL, tPLH PWD 90 18 8.3 120 27 0.5 3 tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V tR/tF |CMH| 25 2.5 35 ns kV/µs |CML| 25 35 kV/µs 1.2 0.20 0.05 Mbps mA/Mbps mA/Mbps fr IDDI (D) IDDO (D) Rev. D | Page 4 of 24 Data Sheet ADuM3400/ADuM3401/ADuM3402 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. 1 Rev. D | Page 5 of 24 ADuM3400/ADuM3401/ADuM3402 Data Sheet ELECTRICAL CHARACTERISTICS—3 V OPERATION All voltages are relative to their respective ground. 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. Table 2. Parameter DC SPECIFICATIONS Input Supply Current per Channel, Quiescent Output Supply Current per Channel, Quiescent ADuM3400, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current VDD2 Supply Current 90 Mbps (CRW Grade Only) VDD1 Supply Current VDD2 Supply Current ADuM3401, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current VDD2 Supply Current 90 Mbps (CRW Grade Only) VDD1 Supply Current VDD2 Supply Current ADuM3402, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 or VDD2 Supply Current 10 Mbps (BRW and CRW Grades Only) VDD1 or VDD2 Supply Current 90 Mbps (CRW Grade Only) VDD1 or VDD2 Supply Current For All Models Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages SWITCHING SPECIFICATIONS ARW Package Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Symbol Min Typ Max Unit IDDI (Q) IDDO (Q) 0.31 0.19 0.49 mA 0.27 mA IDD1 (Q) IDD2 (Q) 1.6 0.7 2.1 1.2 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. IDD1 (10) IDD2 (10) 4.8 1.8 7.1 2.3 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. IDD1 (90) IDD2 (90) 37 11 54 15 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. IDD1 (Q) IDD2 (Q) 1.4 0.9 1.9 1.5 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. IDD1 (10) IDD2 (10) 4.1 2.5 5.6 3.3 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. IDD1 (90) IDD2 (90) 31 17 44 24 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. IDD1 (Q), IDD2 (Q) 1.2 1.7 mA DC to 1 MHz logic signal freq. IDD1 (10), IDD2 (10) 3.3 4.4 mA 5 MHz logic signal freq. IDD1 (90), IDD2 (90) 24 39 mA 45 MHz logic signal freq. µA 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2 IIA, IIB, IIC, IID, IE1, IE2 VIH, VEH VIL, VEL VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL −10 +0.01 +10 1.6 0.4 (VDD1 or VDD2) − 0.1 3.0 (VDD1 or VDD2) − 0.4 2.8 0.0 0.04 0.2 0.1 0.1 0.4 1 50 1000 ns Mbps 100 ns PW tPHL, tPLH V V V V V V V Rev. D | Page 6 of 24 75 Test Conditions IOx = −20 µA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 µA, VIx = VIxL IOx = 400 µA, VIx = VIxL IOx = 4 mA, VIx = VIxL CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels Data Sheet Parameter Pulse Width Distortion, |tPLH − tPHL|4 Propagation Delay Skew5 Channel-to-Channel Matching6 BRW Package Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |tPLH − tPHL|4 Change vs. Temperature Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional Channels6 Channel-to-Channel Matching, Opposing-Directional Channels6 CRW Package Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |tPLH − tPHL|4 Change vs. Temperature Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional Channels6 Channel-to-Channel Matching, Opposing-Directional Channels6 For All Models Output Disable Propagation Delay (High/Low-to-High Impedance) Output Enable Propagation Delay (High Impedance-to-High/Low) Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate Input Dynamic Supply Current per Channel8 Output Dynamic Supply Current per Channel8 ADuM3400/ADuM3401/ADuM3402 Symbol PWD tPSK tPSKCD/OD Min Typ PW Max 40 50 50 Unit ns ns ns Test Conditions CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels 100 CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels tPSK tPSKCD 22 3 ns Mbps ns ns ps/°C ns ns tPSKOD 6 ns tPHL, tPLH PWD 10 20 38 50 3 5 PW tPSK tPSKCD 11.1 ns Mbps 45 ns 2 ns ps/°C 16 ns 2 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels tPSKOD 5 ns CL = 15 pF, CMOS signal levels tPHL, tPLH PWD 90 20 8.3 120 34 0.5 3 tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V tR/tF |CMH| 25 3 35 ns kV/µs |CML| 25 35 kV/µs 1.1 0.10 0.03 Mbps mA/Mbps mA/Mbps fr IDDI (D) IDDO (D) The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. 1 Rev. D | Page 7 of 24 ADuM3400/ADuM3401/ADuM3402 Data Sheet ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.0 V. Table 3. Parameter DC SPECIFICATIONS Input Supply Current per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation Output Supply Current per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation ADuM3400, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 90 Mbps (CRW Grade Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation ADuM3401, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation Symbol Min Typ Max Unit Test Conditions 0.57 0.31 0.83 0.49 mA mA 0.29 0.19 0.27 0.35 mA mA 2.9 1.6 3.5 2.1 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 0.7 1.2 1.2 1.9 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 9.0 4.8 11.6 7.1 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. 1.8 3.0 2.3 5.5 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. 72 37 100 54 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. 11 19 15 36 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. 2.5 1.4 3.2 1.9 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 0.9 1.6 1.5 2.4 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 7.4 4.1 10.6 5.6 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. 2.5 4.4 3.3 6.5 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. IDDI (Q) IDDO (Q) IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10) IDD1 (90) IDD2 (90) IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10) Rev. D | Page 8 of 24 Data Sheet Parameter 90 Mbps (CRW Grade Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation ADuM3402, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps (BRW and CRW Grades Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 90 Mbps (CRW Grade Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation For All Models Input Currents Logic High Input Threshold 5 V/3 V Operation 3 V/5 V Operation Logic Low Input Threshold 5 V/3 V Operation 3 V/5 V Operation Logic High Output Voltages Logic Low Output Voltages SWITCHING SPECIFICATIONS ARW Package Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |tPLH − tPHL|4 Propagation Delay Skew5 Channel-to-Channel Matching6 ADuM3400/ADuM3401/ADuM3402 Symbol Min Typ Max Unit Test Conditions 59 31 82 44 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. 17 32 24 46 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. 2.0 1.2 2.8 1.7 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 1.2 2.0 1.7 2.8 mA mA DC to 1 MHz logic signal freq. DC to 1 MHz logic signal freq. 6.0 3.3 7.5 4.4 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. 3.3 6.0 4.4 7.5 mA mA 5 MHz logic signal freq. 5 MHz logic signal freq. 46 24 62 39 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. 24 46 39 62 mA mA 45 MHz logic signal freq. 45 MHz logic signal freq. +0.01 +10 µA 0 V ≤ VIA,VIB, VIC,VID ≤ VDD1 or VDD2, 0 V ≤ VE1,VE2 ≤ VDD1 or VDD2 IDD1 (90) IDD2 (90) IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10) IDD1 (90) IDD2 (90) IIA, IIB, IIC, IID, IE1, IE2 VIH, VEH −10 2.0 1.6 V V VIL, VEL 0.8 0.4 VOAH, VOBH, (VDD1 or VDD2) − 0.1 VOCH, VODH (VDD1 or VDD2) − 0.4 VOAL, VOBL, VOCL, VODL (VDD1 or VDD2) (VDD1 or VDD2) − 0.2 0.0 0.1 0.04 0.1 0.2 0.4 PW tPHL, tPLH PWD tPSK tPSKCD/OD 1 50 70 Rev. D | Page 9 of 24 V V V IOx = −20 µA, VIx = VIxH V IOx = −4 mA, VIx = VIxH V V V IOx = 20 µA, VIx = VIxL IOx = 400 µA, VIx = VIxL IOx = 4 mA, VIx = VIxL 1000 ns Mbps 100 ns 40 ns 50 ns 50 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels ADuM3400/ADuM3401/ADuM3402 Parameter BRW Package Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |tPLH − tPHL|4 Change vs. Temperature Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional Channels6 Channel-to-Channel Matching, Opposing-Directional Channels6 CRW Package Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |tPLH − tPHL|4 Change vs. Temperature Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional Channels6 Channel-to-Channel Matching, Opposing-Directional Channels6 For All Models Output Disable Propagation Delay (High/Low-to-High Impedance) Output Enable Propagation Delay (High Impedance-to-High/Low) Output Rise/Fall Time (10% to 90%) 5 V/3 V Operation 3 V/5 V Operation Common-Mode Transient Immunity at Logic High Output7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate 5 V/3 V Operation 3 V/5 V Operation Input Dynamic Supply Current per Channel8 5 V/3 V Operation 3 V/5 V Operation Output Dynamic Supply Current per Channel8 5 V/3 V Operation 3 V/5 V Operation Symbol Data Sheet Min Typ PW Max Unit Test Conditions 100 CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels tPSK tPSKCD 22 3 ns Mbps ns ns ps/°C ns ns tPSKOD 6 ns CL = 15 pF, CMOS signal levels 11.1 CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels tPHL, tPLH PWD 10 15 35 50 3 5 PW tPSK tPSKCD 14 2 ns Mbps ns ns ps/°C ns ns tPSKOD 5 ns CL = 15 pF, CMOS signal levels tPHL, tPLH PWD 90 20 8.3 120 30 0.5 3 40 2 tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels tR/tf CL = 15 pF, CMOS signal levels |CMH| 25 3.0 2.5 35 ns ns kV/µs |CML| 25 35 kV/µs 1.2 1.1 Mbps Mbps 0.20 0.10 mA/Mbps mA/Mbps 0.03 0.05 mA/Mbps mA/Mbps fr IDDI (D) IDDO (D) Rev. D | Page 10 of 24 VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Data Sheet ADuM3400/ADuM3401/ADuM3402 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. 1 Rev. D | Page 11 of 24 ADuM3400/ADuM3401/ADuM3402 Data Sheet PACKAGE CHARACTERISTICS Table 4. Parameter Resistance (Input-to-Output)1 Capacitance (Input-to-Output)1 Input Capacitance2 IC Junction-to-Case Thermal Resistance, Side 1 IC Junction-to-Case Thermal Resistance, Side 2 1 2 Symbol RI-O CI-O CI θJCI θJCO Min Typ 1012 2.2 4.0 33 28 Max Unit Ω pF pF °C/W °C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside Device considered a 2-terminal device; Pin 1 to Pin 8 are shorted together and Pin 9 to Pin 16 are shorted together. Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM3400/ADuM3401/ADuM3402 are approved by the organizations listed in Table 5. Refer to Table 10 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 5. UL Recognized Under 1577 Component Recognition Program1 Single Protection, 2500 V rms Isolation Voltage File E214100 CSA Approved under CSA Component Acceptance Notice 5A CQC Approved under CQC11-471543-2012 VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-122 Basic insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage Basic insulation per GB4943.1-2011 400 V rms (588 V peak) maximum working voltage, tropical climate, altitude ≤ 5000 meters Reinforced insulation, 560 V peak File CQC14001117249 File 2471900-4880-0001 Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage File 205078 In accordance with UL 1577, each ADuM3400/ADuM3401/ADuM3402 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA). 2 In accordance with DIN V VDE V 0884-10, each ADuM3400/ADuM3401/ADuM3402 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval. 1 INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 6. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol Value 2500 L(I01) 7.7 min Unit Conditions V rms 1-minute duration mm Measured from input terminals to output terminals, shortest distance through air 8.1 min mm Measured from input terminals to output terminals, shortest distance path along body 0.017 min mm Insulation distance through insulation >400 V DIN IEC 112/VDE 0303 Part 1 II Material Group (DIN VDE 0110, 1/89, Table 1) Minimum External Tracking (Creepage) L(I02) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI Rev. D | Page 12 of 24 Data Sheet ADuM3400/ADuM3401/ADuM3402 DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The * marking on packages denotes DIN V VDE V 0884-10 approval. Table 7. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Conditions VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values VIO = 500 V Characteristic Unit VIORM VPR I to IV I to III I to II 40/105/21 2 560 1050 V peak V peak 896 672 V peak V peak VTR 4000 V peak TS IS1 IS2 RS 150 265 335 >109 °C mA mA Ω VPR 350 RECOMMENDED OPERATING CONDITIONS 300 Table 8. Parameter Operating Temperature Range (TA) Supply Voltages (VDD1, VDD2)1 Input Signal Rise and Fall Times 250 SIDE #2 200 Rating −40°C to +105°C 2.7 V to 5.5 V 1.0 ms 150 SIDE #1 1 100 All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields. 50 0 0 50 100 150 CASE TEMPERATURE (°C) 200 05985-004 SAFETY-LIMITING CURRENT (mA) Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 seconds Maximum value allowed in the event of a failure (see Figure 4) Symbol Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. D | Page 13 of 24 ADuM3400/ADuM3401/ADuM3402 Data Sheet ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Table 9. Parameter Storage Temperature Range (TST) Ambient Operating Temperature Range (TA) Supply Voltages (VDD1, VDD2)1 Input Voltage (VIA, VIB, VIC, VID, VE1, VE2)1, 2 Output Voltage (VOA, VOB, VOC, VOD)1, 2 Average Output Current per Pin3 Side 1 (IO1) Side 2 (IO2) Common-Mode Transients (CMH, CML)4 Rating −65°C to +150°C −40°C to +105°C −0.5 V to +7.0 V −0.5 V to VDD1 + 0.5 V −0.5 V to VDDO + 0.5 V −18 mA to +18 mA −22 mA to +22 mA −100 kV/µs to +100 kV/µs Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION All voltages are relative to their respective ground. VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section. 3 See Figure 4 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Ratings can cause latchup or permanent damage. 1 2 Table 10. Maximum Continuous Working Voltage1 Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Basic Insulation Reinforced Insulation DC Voltage Basic Insulation Reinforced Insulation 1 Max 565 Unit V peak Constraint 50-year minimum lifetime 1131 560 V peak V peak Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 1131 560 V peak V peak Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Table 11. Truth Table (Positive Logic) VIx Input1 H L x x x x 1 2 VEx Input2 H or NC H or NC L H or NC L x VDDI State1 Powered Powered Powered Unpowered Unpowered Powered VDDO State1 Powered Powered Powered Powered Powered Unpowered VOX Output1 Notes H L Z H Outputs return to the input state within 1 µs of VDDI power restoration. Z Indeterminate Outputs return to the input state within 1 µs of VDDO power restoration if VEx state is H or NC. Outputs return to high impedance state within 8 ns of VDDO power restoration if VEx state is L. VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively. In noisy environments, connecting VEx to an external logic high or low is recommended. Rev. D | Page 14 of 24 Data Sheet ADuM3400/ADuM3401/ADuM3402 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 16 VDD2 VDD1 1 15 GND2* VIA 3 ADuM3400 VIB 4 TOP VIEW (Not to Scale) VIC 5 14 VOA 13 VOB 12 VOC VID 6 11 VOD NC 7 10 VE2 *GND1 8 9 GND2* NC = NO CONNECT 05985-005 *GND1 2 *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND2 IS RECOMMENDED. IN NOISY ENVIRONMENTS, CONNECTING OUTPUT ENABLES (PIN 7 FOR ADuM3401/ADuM3402 AND PIN 10 FOR ALL MODELS) TO AN EXTERNAL LOGIC HIGH OR LOW IS RECOMMENDED. Figure 5. ADuM3400 Pin Configuration Table 12. ADuM3400 Pin Function Descriptions Pin No. 1 2, 8 3 4 5 6 7 9, 15 10 Mnemonic VDD1 GND1 VIA VIB VIC VID NC GND2 VE2 11 12 13 14 16 VOD VOC VOB VOA VDD2 Description Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for Isolator Side 1. Logic Input A. Logic Input B. Logic Input C. Logic Input D. No Connect. Ground 2. Ground reference for Isolator Side 2. Output Enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected. VOA, VOB, VOC, and VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is recommended. Logic Output D. Logic Output C. Logic Output B. Logic Output A. Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V. Rev. D | Page 15 of 24 ADuM3400/ADuM3401/ADuM3402 Data Sheet 16 VDD2 VDD1 1 15 GND2* VIA 3 ADuM3401 VIB 4 TOP VIEW (Not to Scale) VIC 5 14 VOA 13 VOB 12 VOC VOD 6 11 VID VE1 7 10 VE2 *GND1 8 9 GND2* 05985-006 *GND1 2 *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND2 IS RECOMMENDED. IN NOISY ENVIRONMENTS, CONNECTING OUTPUT ENABLES (PIN 7 FOR ADuM3401/ADuM3402 AND PIN 10 FOR ALL MODELS) TO AN EXTERNAL LOGIC HIGH OR LOW IS RECOMMENDED. Figure 6. ADuM3401 Pin Configuration Table 13. ADuM3401 Pin Function Descriptions Pin No. 1 2, 8 3 4 5 6 7 Mnemonic VDD1 GND1 VIA VIB VIC VOD VE1 9, 15 10 GND2 VE2 11 12 13 14 16 VID VOC VOB VOA VDD2 Description Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for Isolator Side 1. Logic Input A. Logic Input B. Logic Input C. Logic Output D. Output Enable 1. Active high logic input. VOD output is enabled when VE1 is high or disconnected. VOD is disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is recommended. Ground 2. Ground reference for Isolator Side 2. Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected. VOA, VOB, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is recommended. Logic Input D. Logic Output C. Logic Output B. Logic Output A. Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Rev. D | Page 16 of 24 ADuM3400/ADuM3401/ADuM3402 VDD1 1 16 VDD2 *GND1 2 15 GND2* VIA 3 ADuM3402 14 VOA VIB 4 TOP VIEW (Not to Scale) 13 VOB 12 VIC VOD 6 11 VID VE1 7 10 VE2 *GND1 8 9 GND2* VOC 5 05985-007 Data Sheet *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO GND2 IS RECOMMENDED. IN NOISY ENVIRONMENTS, CONNECTING OUTPUT ENABLES (PIN 7 FOR ADuM3401/ADuM3402 AND PIN 10 FOR ALL MODELS) TO AN EXTERNAL LOGIC HIGH OR LOW IS RECOMMENDED. Figure 7. ADuM3402 Pin Configuration Table 14. ADuM3402 Pin Function Descriptions Pin No. 1 2, 8 3 4 5 6 7 Mnemonic VDD1 GND1 VIA VIB VOC VOD VE1 9, 15 10 GND2 VE2 11 12 13 14 16 VID VIC VOB VOA VDD2 Description Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. Ground 1. Ground reference for Isolator Side 1. Logic Input A. Logic Input B. Logic Output C. Logic Output D. Output Enable 1. Active high logic input. VOC and VOD outputs are enabled when VE1 is high or disconnected. VOC and VOD outputs are disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is recommended. Ground 2. Ground reference for Isolator Side 2. Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected. VOA and VOB outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is recommended. Logic Input D. Logic Input C. Logic Output B. Logic Output A. Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V. Rev. D | Page 17 of 24 ADuM3400/ADuM3401/ADuM3402 Data Sheet 80 15 60 CURRENT (mA) 20 5V 10 3V 5V 3V 0 20 40 60 DATA RATE (Mbps) 80 100 0 0 Figure 8. Typical Input Supply Current per Channel vs. Data Rate (No Load) 60 40 DATA RATE (Mbps) 15 60 CURRENT (mA) 80 100 40 20 5 5V 5V 20 40 60 DATA RATE (Mbps) 80 100 05985-009 0 0 0 Figure 9. Typical Output Supply Current per Channel vs. Data Rate (No Load) 15 60 CURRENT (mA) 80 5V 40 60 DATA RATE (Mbps) 80 100 Figure 12. Typical ADuM3400 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation 20 10 20 05985-012 3V 3V 0 40 5V 20 5 3V 0 0 20 40 60 DATA RATE (Mbps) 80 100 05985-010 3V Figure 10. Typical Output Supply Current per Channel vs. Data Rate (15 pF Output Load) Rev. D | Page 18 of 24 0 0 20 40 60 DATA RATE (Mbps) 80 100 Figure 13. Typical ADuM3401 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation 05985-013 CURRENT/CHANNEL (mA) 80 Figure 11. Typical ADuM3400 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation 20 10 20 05985-011 0 CURRENT/CHANNEL (mA) 40 20 5 05985-008 CURRENT/CHANNEL (mA) TYPICAL PERFORMANCE CHARACTERISTICS Data Sheet ADuM3400/ADuM3401/ADuM3402 40 80 PROPAGATION DELAY (ns) CURRENT (mA) 60 40 5V 20 3V 35 30 5V 0 20 40 60 DATA RATE (Mbps) 80 100 Figure 14. Typical ADuM3401 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation CURRENT (mA) 60 40 5V 20 20 40 60 DATA RATE (Mbps) 80 100 05985-015 3V 0 –25 25 0 50 TEMPERATURE (°C) 75 Figure 16. Propagation Delay vs. Temperature, C Grade 80 0 25 –50 Figure 15. Typical ADuM3402 VDD1 or VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation Rev. D | Page 19 of 24 100 05985-016 0 05985-014 3V ADuM3400/ADuM3401/ADuM3402 Data Sheet APPLICATION INFORMATION The ADuM3400/ADuM3401/ADuM3402 digital isolators require no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 17). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VDD2. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless the ground pair on each package side is connected close to the package. While the ADuM3400/ADuM3401/ADuM3402 improve systemlevel ESD reliability, they are no substitute for a robust systemlevel design. See the AN-793 Application Note, ESD/Latch-Up Considerations with iCoupler Isolation Products for detailed recommendations on board layout and system-level design. PROPAGATION DELAY-RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output can differ from the propagation delay to a logic high. INPUT (VIx) 50% tPLH VDD2 GND2 VOA VOB VOC/IC VOD/ID VE2 GND2 OUTPUT (VOx) tPHL 50% Figure 18. Propagation Delay Parameters 05985-017 VDD1 GND1 VIA VIB VIC/OC VID/OD VE1 GND1 05985-018 PC BOARD LAYOUT Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal’s timing is preserved. Figure 17. Recommended Printed Circuit Board Layout In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the Absolute Maximum Ratings of the device, thereby leading to latch-up or permanent damage. See the AN-1109 Application Note for board layout guidelines. SYSTEM-LEVEL ESD CONSIDERATIONS AND ENHANCEMENTS System-level ESD reliability (for example, per IEC 61000-4-x) is highly dependent on system design, which varies widely by application. The ADuM3400/ADuM3401/ADuM3402 incorporate many enhancements to make ESD reliability less dependent on system design. The enhancements include: ESD protection cells added to all input/output interfaces. Key metal trace resistances reduced using wider geometry and paralleling of lines with vias. The SCR effect inherent in CMOS devices minimized by use of guarding and isolation technique between PMOS and NMOS devices. Areas of high electric field concentration eliminated using 45° corners on metal traces. Supply pin overvoltage prevented with larger ESD clamps between each supply pin and its respective ground. Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM3400/ADuM3401/ADuM3402 component. Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM3400/ADuM3401/ ADuM3402 components operating under the same conditions. DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 11) by the watchdog timer circuit. The limitation on the magnetic field immunity of the ADuM3400/ ADuM3401/ADuM3402 is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM3400/ADuM3401/ ADuM3402 is examined because it represents the most susceptible mode of operation. Rev. D | Page 20 of 24 Data Sheet ADuM3400/ADuM3401/ADuM3402 where: β is magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM3400/ ADuM3401/ADuM3402 and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 19. MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) 100 10 1 10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1 0.01 1k 10k 100k 1M 100M 10M MAGNETIC FIELD FREQUENCY (Hz) Figure 20. Maximum Allowable Current for Various Current-toADuM3400/ADuM3401/ADuM3402 Spacings Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. POWER CONSUMPTION The supply current at a given channel of the ADuM3400/ ADuM3401/ADuM3402 isolator is a function of the supply voltage, the channel’s data rate, and the channel’s output load. 0.1 0.01 For each input channel, the supply current is given by 1M 10k 100k 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 05985-019 0.001 1k DISTANCE = 1m 100 05985-020 V = (−dβ/dt)∑∏rn2; N = 1, 2, … , N 1000 MAXIMUM ALLOWABLE CURRENT (kA) The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by Figure 19. Maximum Allowable External Magnetic Flux Density IDDI = IDDI (Q) f ≤ 0.5 fr IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5 fr For each output channel, the supply current is given by For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil, which is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM3400/ADuM3401/ADuM3402 transformers. Figure 20 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM3400/ ADuM3401/ADuM3402 are extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted, one would have to place a 0.5 kA current 5 mm away from the ADuM3400/ADuM3401/ADuM3402 to affect the operation of the component. IDDO = IDDO (Q) f ≤ 0.5 fr IDDO = (IDDO (D) + (0.5 × 10 ) × CL × VDDO) × (2f − fr) + IDDO (Q) f > 0.5 fr −3 where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz); it is half of the input data rate expressed in units of Mbps. fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA). Rev. D | Page 21 of 24 ADuM3400/ADuM3401/ADuM3402 Data Sheet To calculate the total IDD1 and IDD2 supply current, the supply currents for each input and output channel corresponding to VDD1 and VDD2 are calculated and totaled. Figure 8 provides the per-channel input supply current as a function of the data rate. Figure 9 and Figure 10 provide the per-channel supply output current as a function of the data rate for an unloaded output condition and for a 15 pF output condition, respectively. Figure 11 through Figure 15 provide the total VDD1 and VDD2 supply current as a function of the data rate for the ADuM3400/ADuM3401/ ADuM3402 channel configurations. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower, which allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 10 can be applied while maintaining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross insulation voltage waveform that does not conform to Figure 22 or Figure 23 should be treated as a bipolar ac waveform and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 10. INSULATION LIFETIME Note that the voltage presented in Figure 22 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. 05985-021 0V Figure 21. Bipolar AC Waveform RATED PEAK VOLTAGE 05985-022 Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Figure 21 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. RATED PEAK VOLTAGE 0V Figure 22. Unipolar AC Waveform RATED PEAK VOLTAGE 05985-023 All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM3400/ ADuM3401/ADuM3402. 0V The insulation lifetime of the ADuM3400/ADuM3401/ ADuM3402 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 21, Figure 22, and Figure 23 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the recommended maximum working voltage of Analog Devices. Rev. D | Page 22 of 24 Figure 23. DC Waveform Data Sheet ADuM3400/ADuM3401/ADuM3402 OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 45° 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 8° 0° 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 03-27-2007-B 1 Figure 24. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1, 2 ADuM3400ARWZ ADuM3400BRWZ ADuM3400CRWZ ADuM3401ARWZ ADuM3401BRWZ ADuM3401CRWZ ADuM3402ARWZ ADuM3402BRWZ ADuM3402CRWZ 1 2 Number of Inputs, VDD1 Side 4 4 4 3 3 3 2 2 2 Number of Inputs, VDD2 Side 0 0 0 1 1 1 2 2 2 Maximum Data Rate (Mbps) 1 10 90 1 10 90 1 10 90 Maximum Propagation Delay, 5 V (ns) 100 50 32 100 50 32 100 50 32 Maximum Pulse Width Distortion (ns) 40 3 2 40 3 2 40 3 2 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Z = RoHS Compliant Part. Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape-and-reel option. Rev. D | Page 23 of 24 Package Description 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W Package Option RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 ADuM3400/ADuM3401/ADuM3402 Data Sheet NOTES ©2006–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05985-0-7/15(D) Rev. D | Page 24 of 24