NTMFS4921N

NTMFS4921N
Power MOSFET
30 V, 58.5 A, Single N−Channel, SO−8 FL
Features
•
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
Thermally Enhanced SO−8 Package
These are Pb−Free Device
http://onsemi.com
V(BR)DSS
Applications
• CPU Power Delivery
• DC−DC Converters
• High Side Switching
RDS(ON) MAX
6.95 mW @ 10 V
30 V
Symbol
D (5,6)
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
ID
13.8
A
Continuous Drain
Current RqJA
(Note 1)
TA = 25°C
Power Dissipation
RqJA (Note 1)
TA = 25°C
PD
2.14
Continuous Drain
Current RqJA v
10 sec
TA = 25°C
ID
22.4
Power Dissipation
RqJA, t v 10 sec
Continuous Drain
Current RqJA
(Note 2)
TA = 85°C
N−CHANNEL MOSFET
A
16.1
TA = 25°C
PD
5.61
W
TA = 25°C
ID
8.8
A
TA = 85°C
6.4
PD
0.87
Continuous Drain
Current RqJC
(Note 1)
TC = 25°C
ID
58.5
Power Dissipation
RqJC (Note 1)
TC = 25°C
PD
38.5
W
TA = 25°C
IDM
117
A
TA = 25°C
IDmaxpkg
100
A
TJ,
TSTG
−55 to
+150
°C
IS
38.5
A
Drain to Source dV/dt
dV/dt
6
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 50 V, VGS = 10 V,
IL = 24 Apk, L = 0.3 mH, RG = 25 W)
EAS
86
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
TL
260
TC = 85°C
Current limited by package
Operating Junction and Storage
Temperature
Source Current (Body Diode)
W
A
42.3
May, 2012 − Rev. 4
1
1
SO−8 FLAT LEAD
CASE 488AA
STYLE 1
A
Y
W
ZZ
S
S
S
G
4921N
AYWZZ
D
D
D
= Assembly Location
= Year
= Work Week
= Lot Traceability
ORDERING INFORMATION
Device
Package
Shipping†
NTMFS4921NT1G
SO−8FL
(Pb−Free)
1500 /
Tape & Reel
mJ
NTMFS4921NT3G
SO−8FL
(Pb−Free)
5000 /
Tape & Reel
°C
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
© Semiconductor Components Industries, LLC, 2012
MARKING
DIAGRAM
D
TA = 25°C
tp=10ms
S (1,2,3)
W
Power Dissipation
RqJA (Note 2)
Pulsed Drain
Current
G (4)
10
TA = 85°C
Steady
State
58.5 A
10.8 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
ID MAX
Publication Order Number:
NTMFS4921N/D
NTMFS4921N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Junction−to−Case (Drain)
Parameter
RqJC
3.25
Junction−to−Ambient – Steady State (Note 1)
RqJA
58.3
Junction−to−Ambient – Steady State (Note 2)
RqJA
144.1
Junction−to−Ambient − t v 10 sec
RqJA
22.3
Unit
°C/W
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
(transient)
V(BR)DSSt
VGS = 0 V, ID(aval) = 13 A,
Tcase = 25°C, ttransient = 100 ns
34
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Parameter
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
V
25
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25°C
1
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.5
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
1.45
1.8
VGS(TH)/TJ
RDS(on)
mV/°C
VGS = 10 V to
11.5 V
ID = 30 A
5.3
ID = 15 A
5.2
VGS = 4.5 V
ID = 30 A
8.6
ID = 15 A
8.4
gFS
VDS = 1.5 V, ID = 30 A
6.95
10.8
54
mW
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
136
Total Gate Charge
QG(TOT)
10.7
Threshold Gate Charge
QG(TH)
1.4
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
1400
VGS = 0 V, f = 1 MHz, VDS = 12 V
VGS = 4.5 V, VDS = 15 V; ID = 30 A
282
4.1
pF
16
nC
3.8
QG(TOT)
VGS = 11.5 V, VDS = 15 V,
ID = 30 A
25
nC
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
13.3
tr
td(OFF)
VGS = 4.5 V, VDS = 15 V, ID = 15 A,
RG = 3.0 W
tf
38
16.6
3.8
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
2
ns
NTMFS4921N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
8.2
tr
td(OFF)
20
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
ns
23
tf
3.1
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.85
TJ = 125°C
0.74
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 30 A
1.0
V
11
7.5
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 30 A
ns
3.5
QRR
2.0
nC
Source Inductance
LS
1.3
nH
Drain Inductance
LD
Gate Inductance
LG
Gate Resistance
RG
PACKAGE PARASITIC VALUES
0.005
TA = 25°C
1.84
0.5
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
3
1.1
2.0
W
NTMFS4921N
100
90
VGS = 4.5 V
3.8 V
10 V
60
3.6 V
50
3.4 V
TJ = 25°C
40
30
3.2 V
20
3.0 V
10
2.8 V
2.6 V
0
1
2
3
4
5
80
70
60
50
40
30
TJ = 25°C
0
0
1
TJ = −55°C
2
3
4
5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
ID = 30 A
TJ = 25°C
0.03
0.02
0.01
2
4
6
8
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
6
0.0195
TJ = 25°C
0.017
0.0145
VGS = 4.5 V
0.012
0.0095
0.007
VGS = 11.5 V
0.0045
0.002
30
40
50
60
70
80
90
100
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10000
1.8
ID = 30 A
VGS = 10 V
1.6
VGS = 0 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
TJ = 125°C
20
10
6
0.04
0
VDS ≥ 10 V
90
4.0 V
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (A)
70
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
5.0 V
ID, DRAIN CURRENT (A)
80
1.4
1.2
1
TJ = 150°C
1000
TJ = 125°C
100
0.8
0.6
−50
−25
0
25
50
75
100
125
150
10
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
http://onsemi.com
4
30
NTMFS4921N
TJ = 25°C
C, CAPACITANCE (pF)
1800
1600
Ciss
1400
1200
1000
800
600
Coss
400
Crss
200
0
0
12
VGS, GATE−TO−SOURCE VOLTAGE (V)
2000
5
10
15
20
25
QT
10
8
6
0
30
ID = 30 A
TJ = 25°C
0
4
8
12
16
20
24
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
30
td(off)
100
tf
tr
10
1
td(on)
1
10
20
15
10
5
0
0.2
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
VGS = 20 V
Single Pulse
TC = 25°C
10 ms
100 ms
10
1 ms
10 ms
dc
1
RDS(on) Limit
Thermal Limit
Package Limit
0.1
0.1
1
10
EAS, SINGLE PULSE DRAIN−TO−
SOURCE AVALANCHE ENERGY (mJ)
1000
100
VGS = 0 V
TJ = 25°C
25
IS, SOURCE CURRENT (A)
VDD = 15 V
ID = 30 A
VGS = 11.5 V
t, TIME (ns)
VGS
Qgd
2
1000
ID, DRAIN CURRENT (A)
Qgs
4
100
90
ID = 24 A
80
70
60
50
40
30
20
10
0
25
50
75
100
125
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ, STARTING JUNCTION TEMPERATURE(°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
http://onsemi.com
5
150
NTMFS4921N
90
100
80
VDS = 1.5 V
100°C
70
125°C
60
10
50
Id (A)
gFS (S)
25°C
40
30
1
20
10
0
0
10
20
30
40
50
60
70
80
90
0.1
0.1
DRAIN CURRENT (A)
1
10
100
PULSE WIDTH (ms)
Figure 13. gFS vs. Drain Current
1000
Figure 14. Avalanche Characteristics
http://onsemi.com
6
10000
NTMFS4921N
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE G
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
0.20 C
D
2
A
B
D1
2X
0.20 C
4X
E1
2
3
q
E
2
1
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
c
A1
4
TOP VIEW
C
3X
e
0.10 C
SEATING
PLANE
DETAIL A
A
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
0.10 C
SIDE VIEW
SOLDERING FOOTPRINT*
DETAIL A
3X
8X
0.10
C A B
0.05
c
4X
e/2
1
4
0.965
K
G
0.750
1.000
L
PIN 5
(EXPOSED PAD)
4X
1.270
b
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.15 BSC
4.50
4.90
5.10
3.50
−−−
4.22
6.15 BSC
5.50
5.80
6.10
3.45
−−−
4.30
1.27 BSC
0.51
0.61
0.71
1.20
1.35
1.50
0.51
0.61
0.71
0.05
0.17
0.20
3.00
3.40
3.80
0_
−−−
12 _
1.330
2X
0.905
2X
E2
L1
M
0.495
4.530
3.200
0.475
D2
2X
BOTTOM VIEW
1.530
4.560
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
7
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NTMFS4921N/D