PHILIPS 89C535

INTEGRATED CIRCUITS
89C535/89C536/89C538
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
Preliminary specification
IC20 Data Handbook
1997 June 05
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
DESCRIPTION
89C535/89C536/89C538
LOGIC SYMBOL
The 89C535/89C536/89C538 are Single-Chip 8-Bit Microcontrollers
manufactured in advanced CMOS process and are derivatives of
the 80C51 microcontroller family. All the devices have the same
instruction set as the 80C51.
VCC
VSS
PORT 0
XTAL1
The devices also have four 8-bit I/O ports, three 16-bit timer/event
counters, a multi-source, two-priority-level, nested interrupt
structure, UART and on-chip oscillator and timing circuits. For
systems that require extra data memory capability up to 64k bytes,
each can be expanded using standard TTL-compatible memories
and logic.
ADDRESS AND
DATA BUS
XTAL2
RST
EA/VPP
FEATURES
• 80C51 Central Processing Unit
• 8k x 8 (89C535) 16k × 8 (89C536) or 64k × 8 (89C538), FLASH
RxD
TxD
INT0
INT1
T0
T1
WR
RD
PORT 3
SECONDARY FUNCTIONS
PSEN
ALE/PROG
PORT 2
The 89C535/89C536/89C538 contain a non-volatile FLASH EPROM
program memory (8K bytes in 89C535, 16k bytes in the 89C536,
and 64k bytes in the 89C538). The devices have 512 bytes of RAM
data memory.
PORT 1
T2
T2EX
ADDRESS BUS
SU00830
EPROM Program Memory
• 512 × 8 RAM, externally expandable to 64k × 8 Data Memory
• Three 16-bit counter/timers
• Up to 3 external interrupt request inputs
• 6 interrupt sources with 2 priority levels
• Four 8-bit I/O ports
• Full-duplex UART
• Power control modes
– Idle mode
– Power down mode, with wakeup from power down using
external interrupt
• 44-pin PLCC and QFP packages
ORDERING INFORMATION
MEMORY SIZE
TEMPERATURE RANGE (°C) AND PACKAGE
FREQ.
(MHz)
DRAWING
NUMBER
P89C535NBA A
8k bytes
0 to +70, 44-pin Plastic Leaded Chip Carrier
33
SOT187-2
P89C536NBA A
16k bytes
0 to +70, 44-pin Plastic Leaded Chip Carrier
33
SOT187-2
P89C536NBB B
16k bytes
0 to +70, 44-pin Plastic Quad Flat Package
33
SOT307-2
P89C538NBA A
64k bytes
0 to +70, 44-pin Plastic Leaded Chip Carrier
33
SOT187-2
P89C538NBB B
64k bytes
0 to +70, 44-pin Plastic Quad Flat Package
33
SOT307-2
PART NUMBER
1997 Jun 05
2
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
BLOCK DIAGRAM
P0.0–P0.7
P2.0–P2.7
PORT 0
DRIVERS
PORT 2
DRIVERS
VCC
VSS
RAM ADDR
REGISTER
PORT 0
LATCH
RAM
PORT 2
LATCH
ROF/EPROM
8
B
REGISTER
STACK
POINTER
ACC
PROGRAM
ADDRESS
REGISTER
TMP1
TMP2
BUFFER
ALU
SFRs
PC
INCREMENTER
TIMERS
PSW
8
16
PSEN
ALE/PROG
EAVPP
TIMING
AND
CONTROL
RST
INSTRUCTION
REGISTER
PROGRAM
COUNTER
PD
DPTR’S
MULTIPLE
PORT 1
LATCH
PORT 3
LATCH
PORT 1
DRIVERS
PORT 3
DRIVERS
P1.0–P1.7
P3.0–P3.7
OSCILLATOR
XTAL1
XTAL2
SU00854
1997 Jun 05
3
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
CERAMIC AND PLASTIC LEADED CHIP CARRIER
PIN FUNCTIONS
6
1
89C535/89C536/89C538
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
40
7
44
34
39
1
33
LCC
PQFP
17
29
18
11
23
28
12
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Function
VSS
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
* NO INTERNAL CONNECTION
1997 Jun 05
Function
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
VCC
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
P2.7/A15
PSEN
ALE/PROG
NIC*
EA/VPP
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VCC
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SU00852A
Function
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
* NO INTERNAL CONNECTION
4
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
22
Function
VSS
VCC
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE/PROG
NIC*
EA/VPP
P0.7/AD7
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VCC
VSS
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
SU00853A
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
LCC
QFP
TYPE
VSS
1, 22
16, 39
I
Ground: 0V reference.
VCC
23, 44
17, 38
I
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
P0.0–0.7
43–36
37–30
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float
and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and data memory. In this application, it uses strong
internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and
received code bytes during EEPROM programming. External pull-ups are required during program
verification.
2–9
40–44,
1–3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that
are externally pulled low will source current because of the internal pull-ups. (See DC Electrical
Characteristics: IIL). Port 1 also receives the low-order address byte during program memory
verification.
2
3
40
41
I/O
I
P2.0–P2.7
24–31
18–25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that
are externally being pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external
program memory and during accesses to external data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. Some Port 2 pins
receive the high order address bits during EEPROM programming and verification.
P3.0–P3.7
11,
13–19
5,
7–13
I/O
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
I
O
I
I
I
I
O
O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that
are externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below:
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
RST
10
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An
internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC.
ALE/PROG
33
27
O
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory. This pin is also the program pulse input
(PROG) during EEPROM programming.
PSEN
32
26
O
Program Store Enable: The read strobe to external program memory. When the processor is
executing code from the external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data memory. PSEN is
not activated during fetches from internal program memory.
EA/VPP
35
29
I
External Access Enable/Programming Supply Voltage: EA must be externally held low to enable
the device to fetch code from external program memory. If EA is held high, the device executes from
internal program memory. This pin also receives the 12V programming supply voltage (VPP) during
EPROM programming. EA is internally latched on Reset.
XTAL1
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
XTAL2
20
14
O
Crystal 2: Output from the inverting oscillator amplifier.
P1.0–P1.7
NAME AND FUNCTION
Alternate functions for Port 1 include:
T2 (P1.0): Timer/Counter 2 external count input
T2EX (P1.1): Timer/Counter 2 Reload/Capture
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5V or VSS – 0.5V, respectively.
1997 Jun 05
5
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
Table 1. Special Function Registers
SYMBOL
DESCRIPTION
DIRECT
ADDRESS
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB
LSB
RESET
VALUE
ACC*
Accumulator
E0H
E7
E6
E5
E4
E3
E2
E1
E0
00H
B*
B register
F0H
F7
F6
F5
F4
F3
F2
F1
F0
00H
DPTR:
DPH
DPL
Data Pointer (2 bytes)
Data Pointer High
Data Pointer Low
83H
82H
00H
00H
AF
IE*
IP*
P0*
P1*
P2*
Interrupt Enable
Interrupt Priority
Port 0
Port 1
Port 2
A8H
B8H
80H
90H
A0H
AE
AD
AC
AB
AA
A9
A8
EA
–
BF
BE
ET2
ES
ET1
EX1
ET0
EX0
BD
BC
BB
BA
B9
B8
–
–
PT2
PS
PT1
PX1
PT0
PX0
87
86
85
84
83
82
81
80
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
97
96
95
94
93
92
91
90
–
–
–
–
–
–
T2EX
T2
A7
A6
A5
A4
A3
A2
A1
A0
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
B7
B6
B5
B4
B3
B2
B1
B0
00H
x0000000B
FFH
FFH
FFH
P3*
Port 3
B0H
RD
WR
T1
T0
INT1
INT0
TxD
RxD
FFH
PCON#
Power Control
87H
SMOD
–
–
–
GF1
GF0
PD
IDL
0xxxx000B
D7
D6
D5
D4
D3
D2
D1
D0
PSW*
Program Status Word
D0H
CY
AC
F0
RS1
RS0
OV
–
P
RACAP2H#
RACAP2L#
Timer 2 Capture High
Timer 2 Capture Low
CBH
CAH
SBUF
Serial Data Buffer
99H
SCON*
Serial Control
98H
SP
Stack Pointer
81H
TCON*
Timer Control
88H
00H
00H
00H
xxxxxxxxB
9F
9E
9D
9C
9B
9A
99
98
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
00H
07H
8F
8E
8D
8C
8B
8A
89
88
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
CF
CE
CD
CC
CB
CA
C9
C8
00H
T2CON*
TH0
TH1
TH2#
TL0
TL1
TL2#
Timer 2 Control
Timer High 0
Timer High 1
Timer High 2
Timer Low 0
Timer Low 1
Timer Low 2
C8H
8CH
8DH
CDH
8AH
8BH
CCH
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
00H
00H
00H
00H
00H
00H
00H
TMOD
Timer Mode
89H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
– Reserved bits.
1997 Jun 05
6
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
the instruction that invoked Power Down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
their values down to 2.0V and care must be taken to return VCC to
the minimum specified operating voltages before the Power Down
Mode is terminated.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
Either a hardware reset or external interrupt can be used to exit from
Power Down. Reset redefines all the SFRs but does not change the
on-chip RAM. An external interrupt allows both the SFRs and the
on-chip RAM to retain their values.
To properly terminate Power Down the reset or external interrupt
should not be executed before VCC is restored to its normal
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10ms).
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
VCC and RST must come up at the same time for a proper start-up.
Ports 1, 2, and 3 will asynchronously be driven to their reset
condition when a voltage above VIH1 (min.) is applied to RESET.
With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the
oscillator but bringing the pin back high completes the exit. Once the
interrupt is serviced, the next instruction to be executed after RETI
will be the one following the instruction that put the device into
Power Down.
Design Consideration
• To eliminate the possibility of an unexpected write when Idle is
LOW POWER MODES
terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or to memory.
Idle Mode
In the idle mode (see Table 2), the CPU puts itself to sleep while all
of the on-chip peripherals stay active. The instruction to invoke the
idle mode is the last instruction executed in the normal operating
mode before the idle mode is activated. The CPU contents, the
on-chip RAM, and all of the special function registers remain intact
during this mode. The idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up at the
interrupt service routine and continued), or by a hardware reset
which starts the processor in the same manner as a power-on reset.
ONCE Mode
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked by:
1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the 8XC51FA/FB is
in this mode, an emulator or test CPU can be used to drive the
circuit. Normal operation is restored when a normal reset is applied.
Power-Down Mode
To save even more power, a Power Down mode (see Table 2) can
be invoked by software. In this mode, the oscillator is stopped and
Table 2. External Pin Status During Idle and Power-Down Mode
MODE
PROGRAM MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power-down
Internal
0
0
Data
Data
Data
Data
Power-down
External
0
0
Float
Data
Data
Data
1997 Jun 05
7
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
illustrated in Figure 2 (There is no reload value for TL2 and TH2 in
this mode. Even when a capture event occurs from T2EX, the
counter keeps on counting T2EX pin transitions or osc/12 pulses.).
TIMER 2 OPERATION
Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an
event timer or an event counter, as selected by C/T2* in the special
function register T2CON (see Figure 1). Timer 2 has three operating
modes:Capture, Auto-reload, and Baud Rate Generator, which are
selected by bits in the T2CON as shown in Table 3.
Auto-Reload Mode
In the 16-bit auto-reload mode, Timer 2 can be configured as either
a timer or counter (C/T2* in T2CON).
Figure 3 shows the auto–reload mode of Timer 2. In this mode there
are two options selected by bit EXEN2 in T2CON register. If
EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2
(Overflow Flag) bit upon overflow. This causes the Timer 2 registers
to be reloaded with the 16-bit value in RCAP2L and RCAP2H.
Capture Mode
In the capture mode there are two options which are selected by bit
EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or
counter (as selected by C/T2* in T2CON) which, upon overflowing
sets bit TF2, the timer 2 overflow bit. This bit can be used to
generate an interrupt (by enabling the Timer 2 interrupt bit in the
IE register/SFR table). If EXEN2= 1, Timer 2 operates as described
above, but with the added feature that a 1- to -0 transition at external
input T2EX causes the current value in the Timer 2 registers, TL2
and TH2, to be captured into registers RCAP2L and RCAP2H,
respectively. In addition, the transition at T2EX causes bit EXF2 in
T2CON to be set, and EXF2 like TF2 can generate an interrupt
(which vectors to the same location as Timer 2 overflow interrupt.
The Timer 2 interrupt service routine can interrogate TF2 and EXF2
to determine which event caused the interrupt). The capture mode is
The values in RCAP2L and RCAP2H are preset by software. If
EXEN2=1, then a 16-bit reload can be triggered either by an
overflow or by a 1-to-0 transition at input T2EX. This transition also
sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be
generated when either TF2 or EXF2 are 1.
The external flag EXF2 toggles when Timer 2 underflows or
overflows. This EXF2 bit can be used as a 17th bit of resolution if
needed. The EXF2 flag does not generate an interrupt in this mode
of operation.
(MSB)
TF2
Symbol
Position
TF2
T2CON.7
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
(LSB)
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Name and Significance
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set
when either RCLK or TCLK = 1.
T2CON.6
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2
interrupt routine. EXF2 must be cleared by software.
T2CON.5
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock
in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
T2CON.4
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock
in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
T2CON.3
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.
T2CON.2
Start/stop control for Timer 2. A logic 1 starts the timer.
T2CON.1
Timer or counter select. (Timer 2)
0 = Internal timer (OSC/12)
1 = External event counter (falling edge triggered).
T2CON.0
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When
cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when
EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload
on Timer 2 overflow.
SU00866
Figure 1.
Timer/Counter 2 (T2CON) Control Register
Table 3. Timer 2 Operating Modes
RCLK + TCLK
CP/RL2
TR2
0
0
1
16-bit Auto-reload
0
1
1
16-bit Capture
1
X
1
Baud rate generator
X
X
0
(off)
1997 Jun 05
MODE
8
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
OSC
89C535/89C536/89C538
÷ 12
C/T2 = 0
TL2
(8-bits)
TH2
(8-bits)
TF2
C/T2 = 1
T2 Pin
Control
TR2
Capture
Transition
Detector
Timer 2
Interrupt
RCAP2L
RCAP2H
T2EX Pin
EXF2
Control
EXEN2
SU00066
Figure 2.
OSC
Timer 2 in Capture Mode
÷ 12
C/T2 = 0
TL2
(8-BITS)
TH2
(8-BITS)
C/T2 = 1
T2 PIN
CONTROL
TR2
RELOAD
TRANSITION
DETECTOR
RCAP2L
RCAP2H
TF2
TIMER 2
INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
SU00067
Figure 3.
1997 Jun 05
Timer 2 in Auto-Reload Mode
9
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
Timer 1
Overflow
÷2
NOTE: OSC. Freq. is divided by 2, not 12.
“0”
÷2
OSC
“1”
C/T2 = 0
SMOD
TL2
(8-bits)
“1”
TH2
(8-bits)
“0”
RCLK
C/T2 = 1
T2 Pin
Control
÷ 16
“1”
TR2
Reload
Transition
Detector
RCAP2L
T2EX Pin
EXF2
RCAP2H
RX Clock
“0”
TCLK
÷ 16
TX Clock
Timer 2
Interrupt
Control
EXEN2
Note availability of additional external interrupt.
SU00068
Figure 4.
Table 4.
Timer 2 in Baud Rate Generator Mode
The baud rates in modes 1 and 3 are determined by Timer 2’s
overflow rate given below:
Timer 2 Generated Commonly Used
Baud Rates
Modes 1 and 3 Baud Rates Timer 2 Overflow Rate
16
Timer 2
Ba d Rate
Baud
Osc Freq
375K
9.6K
2.8K
2.4K
1.2K
300
110
300
110
12MHz
12MHz
12MHz
12MHz
12MHz
12MHz
12MHz
6MHz
6MHz
RCAP2H
RCAP2L
FF
FF
FF
FF
FE
FB
F2
FD
F9
FF
D9
B2
64
C8
1E
AF
8F
57
The timer can be configured for either “timer” or “counter” operation.
In many applications, it is configured for “timer” operation (C/T2*=0).
Timer operation is different for Timer 2 when it is being used as a
baud rate generator.
Usually, as a timer it would increment every machine cycle (i.e., 1/12
the oscillator frequency). As a baud rate generator, it increments
every state time (i.e., 1/2 the oscillator frequency). Thus the baud
rate formula is as follows:
Modes 1 and 3 Baud Rates =
Oscillator Frequency
[32 [65536 (RCAP2H, RCAP2L)]]
Baud Rate Generator Mode
Where: (RCAP2H, RCAP2L)= The content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.
Bits TCLK and/or RCLK in T2CON (Table 3) allow the serial port
transmit and receive baud rates to be derived from either Timer 1 or
Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit
baud rate generator. When TCLK= 1, Timer 2 is used as the serial
port transmit baud rate generator. RCLK has the same effect for the
serial port receive baud rate. With these two bits, the serial port can
have different receive and transmit baud rates – one generated by
Timer 1, the other by Timer 2.
The Timer 2 as a baud rate generator mode shown in Figure 4, is
valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a
rollover in TH2 does not set TF2, and will not generate an interrupt.
Thus, the Timer 2 interrupt does not have to be disabled when
Timer 2 is in the baud rate generator mode. Also if the EXEN2
(T2 external enable flag) is set, a 1-to-0 transition in T2EX
(Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but
will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2).
Therefore when Timer 2 is in use as a baud rate generator, T2EX
can be used as an additional external interrupt, if needed.
Figure 4 shows the Timer 2 in baud rate generation mode. The baud
rate generation mode is like the auto-reload mode,in that a rollover
in TH2 causes the Timer 2 registers to be reloaded with the 16-bit
value in registers RCAP2H and RCAP2L, which are preset by
software.
1997 Jun 05
10
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
If Timer 2 is being clocked internally , the baud rate is:
When Timer 2 is in the baud rate generator mode, one should not try
to read or write TH2 and TL2. As a baud rate generator, Timer 2 is
incremented every state time (osc/2) or asynchronously from pin T2;
under these conditions, a read or write of TH2 or TL2 may not be
accurate. The RCAP2 registers may be read, but should not be
written to, because a write might overlap a reload and cause write
and/or reload errors. The timer should be turned off (clear TR2)
before accessing the Timer 2 or RCAP2 registers.
Baud Rate +
[32
f OSC
[65536 * (RCAP2H, RCAP2L)]]
Where fOSC= Oscillator Frequency
To obtain the reload value for RCAP2H and RCAP2L, the above
equation can be rewritten as:
Table 4 shows commonly used baud rates and how they can be
obtained from Timer 2.
RCAP2H, RCAP2L + 65536 *
ǒ
32
f OSC
Baud Rate
Ǔ
Summary Of Baud Rate Equations
Timer/Counter 2 Set-up
Timer 2 is in baud rate generating mode. If Timer 2 is being clocked
through pin T2(P1.0) the baud rate is:
Except for the baud rate generator mode, the values given for
T2CON do not include the setting of the TR2 bit. Therefore, bit TR2
must be set, separately, to turn the timer on. see Table 5 for set-up
of Timer 2 as a timer. Also see Table 6 for set-up of Timer 2 as a
counter.
Baud Rate + Timer 2 Overflow Rate
16
Table 5. Timer 2 as a Timer
T2CON
MODE
INTERNAL CONTROL
(Note 1)
EXTERNAL CONTROL
(Note 2)
16-bit Auto-Reload
00H
08H
16-bit Capture
01H
09H
Baud rate generator receive and transmit same baud rate
34H
36H
Receive only
24H
26H
Transmit only
14H
16H
Table 6. Timer 2 as a Counter
TMOD
MODE
INTERNAL CONTROL
(Note 1)
EXTERNAL CONTROL
(Note 2)
16-bit
02H
0AH
Auto-Reload
03H
0BH
NOTES:
1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate
generator mode.
1997 Jun 05
11
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
Mode 3: 11 bits are transmitted (through TxD) or received (through
jRxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data
bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all
respects except baud rate. The baud rate in Mode 3 is variable.
Serial Interface
The 89C538/536 has a standard 80C51 serial port. This serial port
can operate in 4 modes:
Mode 0: Serial data enters and exits through RxD. TxD outputs the
shift clock. 8 bits are transmitted/received (LSB first). The baud rate
is fixed at 1/12 the oscillator frequency.
In all four modes, transmission is initiated by any instruction that
uses SBUF as a destination register. Reception is initiated in Mode 0
by the condition RI = 0 and REN = 1. Reception is initiated in the
other modes by the incoming start bit if REN = 1.
Mode 1: 10 bits are transmitted (through TxD) or received (through
RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On
receive, the stop bit goes into RB8 in Special Function Register
SCON. The baud rate is variable.
Serial Port Control Register
The serial port control and status register is the Special
FunctionRegister SCON, shown in Figure 5. This register contains
not only the mode selection bits, but also the 9th data bit for transmit
and receive (TB8 and RB8), and the serial port interrupt bits (TI and
RI).
Mode 2: 11 bits are transmitted (throughTxD) or received (through
RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data
bit, and a stop bit (1). On Transmit, the 9th data bit (TB8 in SCON)
can be assigned the value of 0 or 1, Or, for example, the parity bit
(P, in the PSW) could be moved into TB8. On receive, the 9th data
bit goes into RB8 in Special Function Register SCON, while the stop
bit is ignored. The baud rate is programmable to either 1/32 or 1/64
the oscillator frequency.
Additional details of serial port operation may be found in the 80C51
Family Hardware Description found in the Philips 80C51–Based
8–Bit Microcontroller Data Handbook, IC20.
SCON Address = 98H
Reset Value = 0000 0000B
Bit Addressable
Bit:
SM0
SM1
SM2
REN
TB8
RB8
Tl
Rl
7
6
5
4
3
2
1
0
Symbol
Function
SM0
Serial Port Mode Bit 0
SM1
Serial Port Mode Bit 1
SM0
SM1
Mode
0
0
1
1
0
1
0
1
0
1
2
3
Description
Baud Rate**
shift register
8-bit UART
9-bit UART
9-bit UART
fOSC/12
variable
fOSC/64 or fOSC/32
variable
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
REN
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
TB8
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
RB8
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Tl
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Rl
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
NOTE:
**fOSC = oscillator frequency
SU00867
Figure 5.
1997 Jun 05
SCON: Serial Port Control Register
12
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
Interrupt Priority Structure
The 89C535/536/538 has a 6-source two-level interrupt structure
(see Table 7). There are 2 SFRs associated with the interrupts on
the 89C535/536/538. They are the IE and IP. (See Figures 6 and 7.)
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IP.x
0
Level 0 (lowest priority)
1
Level 1 (highest priority)
Table 7.
Interrupt Table
SOURCE
POLLING PRIORITY
REQUEST BITS
X0
1
IE0
T0
2
TP0
Y
0BH
X1
3
IE1
N (L) Y (T)
13H
T1
4
TF1
Y
1BH
SP
5
R1, TI
N
23H
T2
6
TF2, EXF2
N
2BH
NOTES:
1. L = Level activated
2. T = Transition activated
1997 Jun 05
13
HARDWARE CLEAR?
N (L)1
Y (T)2
VECTOR ADDRESS
03H
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
IE (0A8H)
89C535/89C536/89C538
7
6
5
4
3
2
1
0
EA
—
ET2
ES
ET1
EX1
ET0
EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
IE.7
SYMBOL
EA
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
—
ET2
ES
ET1
EX1
ET0
EX0
FUNCTION
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
Not implemented.
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
Figure 6.
IP (0B8H)
SU00571
IE Registers
7
6
5
4
3
2
1
0
—
—
PT2
PS
PT1
PX1
PT0
PX0
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
SYMBOL
—
—
PT2
PS
PT1
PX1
PT0
PX0
FUNCTION
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit.
Serial Port interrupt priority bit.
Timer 1 interrupt priority bit.
External interrupt 1 priority bit.
Timer 0 interrupt priority bit.
External interrupt 0 priority bit.
Figure 7.
1997 Jun 05
IP Registers
14
SU00572
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
For example:
Expanded Data RAM Addressing
The 89C535/536/538 has internal data memory that is mapped into
four separate segments: the lower 128 bytes of RAM, upper 128
bytes of RAM, 128 bytes Special Function Register (SFR), and 256
bytes expanded RAM (ERAM).
MOV @R0,#data
where R0 contains 0A0H, accesses the data byte at address 0A0H,
rather than P2 (whose address is 0A0H).
The ERAM can be accessed by indirect addressing and MOVX
instructions. This part of memory is physically located on-chip,
logically occupies the first 256-bytes of external data memory.
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are
directly and indirectly addressable.
The ERAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or
DPTR. An access to ERAM will not affect ports P0, P3.6 (WR#) and
P3.7 (RD#). P2 SFR is output during external addressing.
For example,
2. The Upper 128 bytes of RAM (addresses 80H to FFH) are
indirectly addressable only.
3. The Special Function Registers, SFRs, (addresses 80H to FFH)
are directly addressable only.
MOVX @R0,#data
4. The 256-bytes expanded RAM (ERAM, 00H – FFH) are indirectly
accessed by move external instruction, MOVX.
where R0 contains 0A0H, accesses the ERAM at address 0A0H
rather than external memory. An access to external data memory
locations higher than FFH (i.e., 0100H to FFFFH) will be performed
with the MOVX DPTR instructions in the same way as in the
standard 80C51, so with P0 and P2 as data/address bus, and P3.6
and P3.7 as write and read timing signals. Refer to Figure 8.
The Lower 128 bytes can be accessed by either direct or indirect
addressing. The Upper 128 bytes can be accessed by indirect
addressing only. The Upper 128 bytes occupy the same address
space as the SFRs. That means they have the same address, but
are physically separate from SFR space.
External data memory cannot be accessed using the MOVX with R0
or R1. This will always access the ERAM.
When an instruction accesses an internal location above address
7FH, the CPU knows whether the access is to the upper 128 bytes
of data RAM or to SFR space by the addressing mode used in the
instruction. Instructions that use direct addressing access SFR
space. For example:
The stack pointer (SP) may be located anywhere in the 256 bytes
RAM (lower and upper RAM) internal data memory. The stack may
not be located in the ERAM.
MOV 0A0H,#data
accesses the SFR at location 0A0H (which is P2). Instructions that
use indirect addressing access the Upper 128 bytes of data RAM.
FF
FF
UPPER
128 BYTES
INTERNAL RAM
ERAM
256 BYTES
FFFF
FF
80
SPECIAL
FUNCTION
REGISTER
EXTERNAL
DATA
MEMORY
80
LOWER
128 BYTES
INTERNAL RAM
00
00
Figure 8.
1997 Jun 05
00
0100
0000
Internal and External Data Memory Address Space
15
SU00868
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER
Operating temperature under bias
Storage temperature range
Voltage on EA/VPP pin to VSS
Voltage on any other pin to VSS
Maximum IOL per I/O pin
RATING
UNIT
0 to +70
°C
–65 to +150
°C
0 to +13.0
V
–0.5 to +6.5
V
15
mA
Power dissipation (based on package heat transfer limitations, not device power consumption)
1
W
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.
1997 Jun 05
16
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C; 5V ±10%; VSS = 0V
SYMBOL
PARAMETER
LIMITS
TEST
CONDITIONS
MIN
MAX
4.5V < VCC < 5.5V
–0.5
0.2VCC–0.1
V
0.2VCC+0.9
VCC+0.5
V
0.7VCC
VCC+0.5
V
UNIT
VIL
Input low voltage
VIH
Input high voltage (ports 0, 1, 2, 3, EA)
VIH1
Input high voltage, XTAL1, RST
VOL
Output low voltage, ports 1, 2, 3 6
VCC = 4.5V
IOL = 1.6mA1
0.4
V
VOL1
Output low voltage, port 0, ALE, PSEN 5, 6
VCC = 4.5V
IOL = 3.2mA1
0.4
V
VOH
Output high voltage, ports 1, 2, 3 2
VCC = 4.5V
IOH = –30µA
VCC – 0.7
V
VOH1
Output high voltage (port 0 in external bus mode), ALE7,
PSEN2
VCC = 4.5V
IOH = –800µA
VCC – 0.7
V
IIL
Logical 0 input current, ports 1, 2, 3
VIN = 0.4V
–1
–50
µA
ITL
Logical 1-to-0 transition current, ports 1, 2, 3
VIN = 2.0V
See note 3
–650
µA
ILI
Input leakage current, port 0
0.45 < VIN < VCC – 0.3
±10
µA
ICC
Power supply current (see Figure 16):
Active mode
Idle mode
Power-down mode or clock stopped
(see
Figure 20 ffor conditions)
(
Fi
diti
)
See note 4
VCC = 5.5V
FREQ = 24 MHz
Tamb = 0°C to 70°C
60
25
100
mA
mA
µA
RRST
Internal reset pull-down resistor
40
225
kΩ
NOTES:
1. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
2. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC–0.7 specification when the
address bits are stabilizing.
3. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2V.
4. See Figures 17 through 20 for ICC test conditions.
Active mode:
ICC(MAX) = 0.9 × FREQ. + 1.1mA
Idle mode:
ICC(MAX) = 0.18 × FREQ. +1.0mA; See Figure 16.
5. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
15mA
Maximum IOL per port pin:
26mA
Maximum IOL per 8-bit port:
71mA
Maximum total IOL for all outputs:
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
7. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification.
8. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF
(except EA is 25pF).
1997 Jun 05
17
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V1, 2, 3
VARIABLE CLOCK
SYMBOL
FIGURE
1/tCLCL
9
PARAMETER
Oscillator frequency
Speed versions : N (33MHz)
MIN
MAX
3.5
33
33MHz CLOCK
MIN
MAX
3.5
33
UNIT
MHz
tLHLL
9
ALE pulse width
2tCLCL–40
21
ns
tAVLL
9
Address valid to ALE low
tCLCL–25
5
ns
tLLAX
9
Address hold after ALE low
tCLCL–25
5
ns
tLLIV
9
ALE low to valid instruction in
tLLPL
9
ALE low to PSEN low
tCLCL–25
5
ns
tPLPH
9
PSEN pulse width
3tCLCL–45
45
ns
tPLIV
9
PSEN low to valid instruction in
tPXIX
9
Input instruction hold after PSEN
tPXIZ
9
Input instruction float after PSEN
tCLCL–25
5
ns
tAVIV
9
Address to valid instruction in
5tCLCL–80
70
ns
tPLAZ
9
PSEN low to address float
10
10
ns
4tCLCL–65
55
3tCLCL–60
0
30
0
ns
ns
ns
Data Memory
tRLRH
10, 11
RD pulse width
6tCLCL–100
tWLWH
10, 11
WR pulse width
6tCLCL–100
tRLDV
10, 11
RD low to valid data in
tRHDX
10, 11
Data hold after RD
tRHDZ
10, 11
Data float after RD
2tCLCL–28
32
ns
tLLDV
10, 11
ALE low to valid data in
8tCLCL–150
90
ns
tAVDV
10, 11
Address to valid data in
9tCLCL–165
105
ns
tLLWL
10, 11
ALE low to RD or WR low
3tCLCL–50
140
ns
tAVWL
10, 11
Address valid to WR low or RD low
4tCLCL–75
45
ns
tQVWX
10, 11
Data valid to WR transition
tCLCL–30
0
ns
tWHQX
10, 11
Data hold after WR
tCLCL–25
5
ns
tQVWH
11
tRLAZ
10, 11
RD low to address float
tWHLH
10, 11
RD or WR high to ALE high
82
82
5tCLCL–90
0
Data valid to WR high
ns
60
0
3tCLCL+50
7tCLCL–130
40
tCLCL+25
5
ns
ns
80
0
tCLCL–25
ns
ns
0
ns
55
ns
External Clock
tCHCX
13
High time
17
tCLCL–tCLCX
ns
tCLCX
13
Low time
17
tCLCL–tCHCX
ns
tCLCH
13
Rise time
5
ns
tCHCL
13
Fall time
5
ns
tXLXL
12
Serial port clock cycle time
tQVXH
12
tXHQX
12
tXHDX
12
Input data hold after clock rising edge
Shift Register
12tCLCL
360
ns
Output data setup to clock rising edge
10tCLCL–133
167
ns
Output data hold after clock rising edge
2tCLCL–80
50
ns
0
0
ns
tXHDV
12
Clock rising edge to input data valid
10tCLCL–133
167
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
1997 Jun 05
18
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
EXPLANATION OF THE AC SYMBOLS
P – PSEN
Q – Output data
R – RD signal
t – Time
V – Valid
W – WR signal
X – No longer a valid logic level
Z – Float
Examples: tAVLL = Time for address valid to ALE low.
tLLPL =Time for ALE low to PSEN low.
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
tLHLL
ALE
tAVLL
tLLPL
tPLPH
tLLIV
tPLIV
PSEN
tLLAX
A0–A7
PORT 0
tPXIZ
tPLAZ
tPXIX
A0–A7
INSTR IN
tAVIV
PORT 2
A0–A15
A8–A15
SU00006
Figure 9.
External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV
tLLWL
tRLRH
RD
tAVLL
tLLAX
tRLAZ
PORT 0
tRHDZ
tRLDV
tRHDX
A0–A7
FROM RI OR DPL
DATA IN
A0–A7 FROM PCL
INSTR IN
tAVWL
tAVDV
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00025
Figure 10.
1997 Jun 05
External Data Memory Read Cycle
19
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
ALE
tWHLH
PSEN
tWLWH
tLLWL
WR
tLLAX
tAVLL
tWHQX
tQVWX
tQVWH
A0–A7
FROM RI OR DPL
PORT 0
DATA OUT
A0–A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00026
Figure 11.
INSTRUCTION
0
1
External Data Memory Write Cycle
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK
tXHQX
tQVXH
OUTPUT DATA
0
1
2
WRITE TO SBUF
3
4
5
6
7
tXHDX
tXHDV
SET TI
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CLEAR RI
SET RI
SU00027
Figure 12.
VCC–0.5
0.45V
Shift Register Mode Timing
0.7VCC
0.2VCC–0.1
tCHCL
tCHCX
tCLCH
tCLCX
tCLCL
SU00009
Figure 13.
1997 Jun 05
External Clock Drive
20
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
VCC–0.5
89C535/89C536/89C538
VLOAD+0.1V
0.2VCC+0.9
TIMING
REFERENCE
POINTS
VLOAD
0.2VCC–0.1
0.45V
VLOAD–0.1V
VOL+0.1V
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from
load voltage occurs, and begins to float when a 100mV change from the loaded
VOH/VOL level occurs. IOH/IOL ≥ ±20mA.
NOTE:
AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.
SU00717
Figure 14.
VOH–0.1V
SU00718
AC Testing Input/Output
Figure 15.
Float Waveform
90.00
80.00
MAX ACTIVE MODE
70.00
ICC(mA)
60.00
50.00
TYP ACTIVE MODE
40.00
30.00
20.00
MAX IDLE MODE
10.00
TYP IDLE MODE
0.00
0
4
8
12
16
20
24
28
32
36
FREQ AT XTAL1 (MHz)
SU00886
Figure 16.
1997 Jun 05
ICC vs. FREQ Valid only within frequency specifications of the device under test
21
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
VCC
VCC
ICC
ICC
VCC
VCC
VCC
VCC
RST
RST
VCC
P0
P0
EA
EA
(NC)
XTAL2
(NC)
XTAL2
CLOCK SIGNAL
XTAL1
CLOCK SIGNAL
XTAL1
VSS
VSS
SU00719
SU00720
Figure 17.
ICC Test Condition, Active Mode
All other pins are disconnected
VCC–0.5
Figure 18.
ICC Test Condition, Idle Mode
All other pins are disconnected
0.7VCC
0.2VCC–0.1
0.45V
tCHCL
tCHCX
tCLCH
tCLCX
tCLCL
SU00009
Figure 19.
Clock Signal Waveform for ICC Tests in Active and Idle Modes
tCLCH = tCHCL = 5ns
VCC
ICC
VCC
VCC
RST
P0
EA
(NC)
XTAL2
XTAL1
VSS
SU00016
Figure 20.
ICC Test Condition, Power Down Mode
All other pins are disconnected. VCC = 2V to 5.5V
1997 Jun 05
22
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
does not require the system to time out or verify the data
programmed. The typical room temperature chip programming time
of the 89C535/536/538 is less than 5 seconds.
FLASH EPROM PROGRAM MEMORY
FEATURES
• 8K (89C535), 16K (89C536), 64K (89C538) or
89C535/89C536/89C538
Automatic Chip Erase
electrically
The device may be erased using the automatic Erase algorithm. The
automatic Erase algorithm automatically programs the entire array
prior to electrical erase. The timing and verification of electrical
erase are controlled internal to the device.
erasable internal program.
• Up to 64 Kilobyte external program memory if the internal program
memory is switched off (EA = 0)..
• Programming and erasing voltage 12V 5%
• Command register architecture
Automatic Programming Algorithm
The 89C535/536/538 automatic Programming algorithm requires the
user to only write a program set–up command and a program
command (program data and address). The device automatically
times the programming pulse width, provides the program verify, and
counts the number of sequences. A status bit similar to DATA
polling and a status bit toggling between consecutive read cycles,
provide feedback to the user as to the status of the programming
operation.
– Byte Programming (10 us typical)
– Auto chip erase 5 seconds typical (including preprogramming
time)
• Auto Erase and auto program
– DATA polling
– Toggle bit
• 100 minimum erase/program cycles
• Advanced CMOS FLASH EPROM memory technology
AUTOMATIC ERASE ALGORITHM
The 89C535/536/538 Automatic Erase algorithm requires the user to
only write an erase set–up command and erase command. The
device will automatically pre–program and verify the entire array.
Then the device automatically times the erase pulse width, provides
the erase verify, and counts the number of sequences. A status bit
similar to DATA polling and a status bit toggling between
consecutive read cycles, provide feedback to the user as to the
status of the erase operation.
GENERAL DESCRIPTION
The 89C535/536/538 FLASH EPROM memory augments EPROM
functionality with In–circuit electrical erasure and programming. The
89C535/536/538 uses a command register to manage this
functionality.
Commands are written to the command register. Register contents
serve as inputs to an internal state–machine which controls the
erase and programming circuitry. During write cycles, the command
register internally latches address and data needed for the
programming and erase operations. For system design
simplification, the 89C535/536/538 is designed to support either WE
or CE controlled writes. During a system write cycle, addresses are
latched on the falling edge of WE or CE, whichever occurs last. Data
is latched on the rising edge of WE or CE, whichever occurs first. To
simplify the following discussion, the WE pin is used as the write
cycle control pin through the rest of this text. All setup and hold
times are with respect to the WE signal.
The FLASH EPROM reliably stores memory contents even after 100
erase and program cycles. The cell is designed to optimize the
erase and programming mechanisms. In addition, the combination
of advanced tunnel oxide processing and low internal electric fields
for erase and programming operations produces reliable cycling.
The 89C535/536/538 uses a 12.0V 5%VPP supply to perform the
Auto Program/Erase algorithms.
Automatic Programming
The 89C535/536/538 is byte programmable using the Automatic
Programming algorithm. The Automatic Programming algorithm
1997 Jun 05
23
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
+5V
VDD
A0–A7
P1
1
RST
P0
PGM COMMAND/DATA
EA
VPP
ALE/WE
CE
P3.3
LOW PULSE
PSEN
89C535/536/538
0
P2.7
OE
P3.5
A15
XTAL2
4–6 MHz
A8–A13
P2.0–P2.5
XTAL1
P3.4
VSS
A14
0000b
P2.6, P3.7, P3.1, P3.0
su00876
Figure 21.
Erase/Programming/Verification
Table 8. Pin Description
PIN NAME
SYMBOL
FUNCTION
P1.0–P1.7
A0–A7
Input Low Order Address Bits
P2.0–P2.5, P3.4, P3.5
A8–A13, A14–A15
Input High Order Address Bits
P0.0–P0.7
Q0–Q7
Data Input/Output
P3.3
CE
Chip Enable Input
P2.7
OE
Output Enable Input
ALE/WE
WE
Write Enable Pin
EA
VPP
Program Supply Voltage
P2.6, P3.7, P3.1, P3.0
FTEST3–FTEST0
Flash Test Mode Selection
VCC
VCC
Power Supply Voltage (+5V)
GND
GND
Ground Pin
Table 9. Command Definitions
FIRST BUS CYCLE
COMMAND
BUS CYCLES
OPERATION ADDRESS DATA
SECOND BUS CYCLE
OPERATION ADDRESS DATA
Setup auto erase/auto erase (chip)
2
Write
X
30H
Write
X
30H
Setup auto program/program
2
Write
X
40H
Write
PA
PD
Reset
2
Write
X
FFH
Write
X
FFH
Note:
Command Definitions
• PA = Address of memory location to be programmed
• PD = Data to be programmed at location
1997 Jun 05
When low voltage is applied to the VPP pin, the contents of the
command register default to 00H. Placing high voltage on the VPP
pin enables read/write operations. Device operations are selected
by writing specific data patterns into the command register. Table 2
defines these 89C535/536/538 register commands. Table 3 defines
the bus operations of 89C535/536/538.
24
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
Table 10.
OPERATION
VPP(1)
CE
OE
WE
D00–D07
READ/WRITE
Read(2)
VPPH
VIL
VIL
VIH
DATA OUT(3)
Standby(4)
VPPH
VIH
X
X
Tri–State
Write
VPPH
VIL
VIH
VIL
Data In(5)
NOTES:
1. VPPH is the programming voltage specified for the device.
2. Read operation withVPP = VPPH may access array data (if write command is preceded) or silicon ID codes.
3. With VPP at high voltage, the standby current equals ICC+IPP (standby).
4. Refer to Table 38 for valid Data–In during a write operation.
5. X can be VIL or VIH.
Set–Up Automatic Chip Erase/Erase Commands
Reset Command
The automatic chip erase does not require the device to be entirely
pre–programmed prior to executing the Automatic set–up erase
command and automatic chip erase command. Upon executing the
Automatic chip erase command, the device automatically will
program and verify the entire memory for an all–zero data pattern.
When the device is automatically verified to contain an all–zero
pattern, a self–timed chip erase and verify begins. The erase and
verify operations are complete when the data on DQ7 is”1” at which
time the device returns to the standby mode. The system is not
required to provide any control or timing during these operations.
A reset command is provided as a means to safely abort the erase–
or program–command sequences. Following either set–up
command (erase or program) with two consecutive writes of FFH
will safely abort the operation. Memory contents will not be altered.
Should program–fail or erase–fail happen, two consecutive writes of
FFH will reset the device to abort the operation. A valid command
must then be written to place the device in the desired state.
Write Operation Status
Toggle Bit–DQ6
When using the Automatic Chip Erase algorithm, note that the erase
automatically terminates when adequate erase margin has been
achieved for the memory array (no erase verify command is
required). The margin voltages are internally generated in the same
manner as when the standard erase verify command is used.
The 89C535/536/538 features a “Toggle Bit” as a method to indicate
to the host system that the Auto Program/Erase algorithms are
either in progress or completed.
While the Automatic Program or Erase algorithm is in progress,
successive attempts to read data from the device will result in DQ6
toggling between one and zero. Once the Automatic Program or
Erase algorithm is completed, DQ6 will stop toggling and valid data
will be read. The toggle bit is valid after the rising edge of the
second WE pulse of the two write pulse sequences.
The Automatic set–up erase command is a command only operation
that stages the device for automatic electrical erasure of all bytes in
the array. Automatic set–up erase is performed by writing 30H to the
command register.
To command automatic chip erase, the command 30H must be
written again to the command register. The automatic chip erase
begins on the rising edge of the WE and terminates when the data
on DQ7 is ”1 “ and the data on DQ6 stops toggling for two
consecutive read cycles, at which time the device returns to the
standby mode.
Data Polling–D07
The 89C535/536/538 also features DATA Polling as a method to
indicate to the host system that the Automatic Program or Erase
algorithms are either in progress or completed.
While the Automatic Programming algorithm is in operation an
attempt to read the device will produce the complement data of the
data last written to DQ7. Upon completion of the Automatic Program
algorithm an attempt to read the device will produce the true data
last written to DQ7. The Data Polling feature is valid after the rising
edge of the second WE pulse of the two write pulse sequences.
Set–Up Automatic Program/Program Commands
The Automatic Set–up Program is a command–only operation that
stages the devices for automatic programming. Automatic Set–up
Program is performed by writing 40H to the command register.
Once the Automatic Set–up Program operation is performed, the
next WE pulse causes a transition to an active programming
operation. Addresses are internally latched on the falling edge of the
WE pulse. Data is internally latched on the rising edge of the WE
pulse. The rising edge of WE also begins the programming
operation. The system is not required to provide further controls or
timings. The device will automatically provide an adequate internally
generated program pulse and verify margin. The automatic
programming operation is completed when the data read on DQ6
stops toggling for two consecutive read cycles and the data on DQ7
and DQ6 are equivalent to data written to these two bits at which
time the device returns to the Read mode (no program verify
command is required; but data can be read out if OE is active low).
1997 Jun 05
While the Automatic Erase algorithm is in operation, DQ7 will read
“0” until the erase operation is completed. Upon completion of the
erase operation, the data on DQ7 will read “1”. The DATA Polling
feature is valid after the rising edge of the second WE pulse of two
writes pulse sequences.
The DATA Polling feature is active during Automatic Program/Erase
algorithms.
Write Operation
The data to be programmed into Flash should be inverted when
programming. In other words to program the value ‘00’, ‘FF’ should
be applied to port P0.
25
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
dependent on the output capacitance loading of the device. At a
minimum, a 0.1uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between VCC and GND,
and between VPP and GND to minimize transient effects.
System Considerations
During the switch between active and standby conditions, transient
current peaks are produced on the rising and falling edges of Chip
Enable. The magnitude of these transient current peaks is
MIN
89C535/89C536/89C538
SYMBOL
PARAMETER
MAX
UNIT
CONDITION
CIN
VPPH
TYP
14
PF
VIN = 0V
COUT
VPPH
16
pF
VOUT = 0V
Command programming/Data programming/Erase Operation
DC CHARACTERISTICS
Tamb = 0°C to 70°C, VCC = 5V ± 10%, VPP = 12.0V ± 5%
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
ILI
Input Leakage Current
VIN = GND to VCC
10
µA
ILO
Output Leakage Current
VOUT = GND to VCC
10
µA
ISB1
Standby VCC Current
CE = VIH
1
mA
100
µA
IOUT = 0 mA, f=1 MHz
30
mA
ICC2
IOUT = 0 mA, F=11MHz
50
mA
ICC3 (Program)
In Programming
50
mA
ICC4 (Erase)
In Erase
50
mA
ICC5 (Program Verify)
In Program Verify
50
mA
ICC6 (Erase Verify)
In erase Verify
50
mA
VPP=12.6 V
100
µA
IPP2 (Program)
In Programming
50
mA
IPP3 (Erase)
In Erase
50
mA
IPP4 (Program Verify)
In Program Verify
50
mA
IPP5 (Erase Verify)
In Erase Verify
50
mA
–0.5 (Note 5)
0.2VPP – 0.3
V
2.4
VCC+0.3V
V
ISB2
ICC1 (Read)
IPP1 (Read)
VIL
CE = VCC ± 0.3 V
Operating VCC Current
VPP Current
Input Voltage
VIH
1
(Note 6)
VOL
Output Voltage Low
IOL=2.1mA
VOH
Output Voltage High
IOH=400uA
0.45
2.4
NOTES:
1. VCC must be applied before VPP and removed after VPP.
2. VPP must not exceed 14V including overshoot.
3. An influence may be had upon device reliability if the device is installed or removed while VPP=12V.
4. Do not alter VPP from VIL to 12V or 12V to VIL when CE=VIL
5. VIL min. = –0.5V for pulse width ≤ 20ns.
6. If VIH is over the specified maximum value, programming operation cannot be guaranteed.
7. All currents are in RMS unless otherwise noted. (Sampled, not 100% tested.).
1997 Jun 05
26
V
V
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
AC CHARACTERISTICS
Tamb = 0°C to 70°C, VCC = 5V 10%, VPP = 12V 5%
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
τVPS
VPP setup time
100
ns
τOES
OE setup time
100
ns
τCWC
Command programming cycles
150
ns
τCEP
WE programming pulse width
60
ns
τEPH1
WE programming pulse width High
20
ns
τCEPH2
WE programming pulse width High
100
ns
τAS
Address setup time
0
ns
τAH1
Address hold time for DATA Polling
0
ns
τDS
DATA setup time
50
ns
τDH
DATA hold time
10
ns
τCESP
CE setup time before DATA polling/toggle bit
100
ns
τCES
CE setup time
0
ns
τCESC
CE setup time before command write
100
ns
τVPH
VPP hold time
100
ns
τDF
Output disable time (Note 2)
τDPA
τAETC
τAVT
Total programming time in auto verify
35
ns
DATA polling/toggle bit access time
150
ns
Total erase time in auto chip erase
5(TYP)
s
300
s
15
NOTES:
1. CE and OE must be fixed high during VPP transition from 5V to 12V or from 12V to 5V.
2. τDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
circuit. Programming completion can be verified by DATA polling and
toggle bit checking after automatic verify starts. Device outputs
DATA during programming and DATA after programming on Q7. Q0
to Q5(Q6 is for toggle bit; see toggle bit, DATA polling, timing
waveform) are in high impedance.
Timing Waveform
Automatic Programming
One byte of data is programmed. Verifying in fast algorithm and
additional programming by external control are not required because
these operations are executed automatically by an internal control
1997 Jun 05
27
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
SETUP AUTO PROGRAM/
AUTO PROGRAM & DATA POLLING
PROGRAM COMMAND
VCC 5V
12V
VPP
OV
τVPH
τVPS
ADDRESS
VALID
A0–A15
τAS
WE
τAH1
τAVT
τcwc
CE
τQES
τCEP
τCEPH1
τDS
τDH
τCEP
τCESP
τCESC
τCES
OE
Q7
COMMAND IN
Q0–Q5
COMMAND IN
τDS
τDH
DATA IN
τDPA
tDF
DATA
DATA
DATA POLLING
DATA IN
DATA
COMMAD #40H
su00877
Figure 22.
Automatic Programming Timing Waveform
0 during erasure and 1 after erasure on Q7, Q0 to Q5 (Q6 is for
toggle bit; see toggle bit, DATA polling, timing waveform) are in high
impedance.
AUTOMATIC CHIP ERASE
All data in the FLASH memory is erased. External erase verification
is not required. Erasure completion can be verified by DATA polling
and toggle bit checking after automatic erase starts. Device outputs
1997 Jun 05
28
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
RESET
SETUP AUTO CHIP ERASE/
ERASE COMMAND
AUTO CHIP ERASE & DATA POLLING
VCC 5V
12V
τVPH
VPP
OV
τVPS
A0–A15
WE
τAETC
τCWC
CE
τQES
τCEP
τCEPH1
τCEP
τCESP
τCESC
τCES
OE
τDS
Q7
τDH
τDS
τDH
COMMAND IN
COMMAND IN
COMMAND IN
COMMAND IN
τDPA
τDF
DATA POLLING
Q0–Q5
su00878
Figure 23.
1997 Jun 05
Automatic Chip Erase Timing Waveform
29
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
VCC 5V
12V
VPP
0V
τVPS
A0–A15
tCWC
WE
CE
τQES
τCEP
τCEPH1
τCEP
OE
τDS
Q0–Q7
τDH
COMMAND IN
τDS
τDH
COMMAND IN
FFH
FFH
su00879
Figure 24.
Reset Timing Waveform
Toggle Bit, Data Polling
Toggle bit appears in Q6, when program/erase is operating. DATA
polling appears in Q7 during programming or erase.
1997 Jun 05
30
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
HIGH
WE
VPP 12V
CE
OE
TOGGLE BIT
OE
HIGH–Z
DATA
DURING P/E
DATA POLLING
O7
HIGH–Z
DATA
DATA
DATA
DATA
DURING P
O7
DURING P
PROGRAM/ERASE COMPLETE
HIGH–Z
DATA POLLING
HIGH–Z
O0–O5
DATA
su00880
Figure 25.
1997 Jun 05
Toggle Bit, Data Polling Timing Waveform
31
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
PLCC44: plastic leaded chip carrier; 44 leads
1997 June 05
89C535/89C536/89C538
SOT187-2
32
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
1997 June 05
33
SOT307-2
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
NOTES
1997 June 05
34
89C535/89C536/89C538
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
with FLASH program memory
89C535/89C536/89C538
DEFINITIONS
Data Sheet Identification
Product Status
Definition
Objective Specification
Formative or in Design
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Preliminary Specification
Preproduction Product
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Product Specification
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
 Copyright Philips Electronics North America Corporation 1997
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
1997 June 05
35