Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers DESCRIPTION 87C54/87C58 PIN CONFIGURATIONS The 87C54/87C58 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 87C54/87C58 has the same instruction set as the 80C51. T2/P1.0 1 40 VCC T2EX/P1.1 2 39 P0.0/AD0 This device provides architectural enhancements that make it applicable in a variety of applications for general control systems. The 87C58 contains 32k × 8 EPROM memory, and the 87C54 contains 16k × 8 EPROM memory, a volatile 256 × 8 read/write data memory, four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, two-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. For systems that require extra capability, the 87C54/87C58 can be expanded using standard TTL compatible memories and logic. P1.2 3 38 P0.1/AD1 P1.3 4 37 P0.2/AD2 P1.4 5 36 P0.3/AD3 P1.5 6 35 P0.4/AD4 P1.6 7 34 P0.5/AD5 P1.7 8 33 P0.6/AD6 RST 9 32 P0.7/AD7 Its added features make it an even more powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multiprocessor communications. RxD/P3.0 See 80C52/54/58 datasheet for ROM device specification. FEATURES • 80C51 central processing unit • 16k × 8 EPROM expandable externally to 64k bytes (87C54) • 16k × 8 EPROM (87C54) and 32k × 8 EPROM expandable externally to 64k bytes (87C58) – Improved Quick Pulse programming algorithm DUAL IN-LINE PACKAGE 31 EA/VPP 30 ALE/PROG INT0/P3.2 12 29 PSEN INT1/P3.3 13 28 P2.7/A15 T0/P3.4 14 27 P2.6/A14 T1/P3.5 15 26 P2.5/A13 WR/P3.6 16 25 P2.4/A12 RD/P3.7 17 24 P2.3/A11 XTAL2 18 23 P2.2/A10 XTAL1 19 22 P2.1/A9 VSS 20 21 P2.0/A8 SU00748 – Two level program security system – 32 byte encryption array • 256 × 8 RAM, expandable externally to 64k bytes • Three 16-bit timer/counters – T2 is an up/down counter • Four 8-bit I/O ports • Full-duplex enhanced UART – Framing error detection – Automatic address recognition • Power control modes – Idle mode – Power-down mode • Once (On Circuit Emulation) Mode • Five package styles • OTP package available • Programmable clock out • 6 interrupt sources • 2 level priority 1996 Aug 16 10 TxD/P3.1 11 3-215 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers 87C54/87C58 ORDERING INFORMATION 16k × 8 EPROM1 32k × 8 EPROM1 TEMPERATURE RANGE °C AND PACKAGE FREQUENCY DRAWING NUMBER OTP 0 to +70, 40-Pin Plastic Dual In-line Package 16MHz SOT129-1 P87C54EBP N P87C58EBP N P87C54EBF FA P87C58EBF FA UV 0 to +70, 40-Pin Ceramic Dual In-line Package w/Window 16MHz 0590B P87C54EBA A P87C58EBA A OTP 0 to +70, 44-Pin Plastic Leaded Chip Carrier 16MHz SOT187-2 P87C54EBL KA P87C58EBL KA UV 0 to +70, 44-Pin Ceramic Leaded Chip Carrier w/Window 16MHz 1472A P87C54EBB B P87C58EBB B OTP 0 to +70, 44-Pin Plastic Quad Flat Pack 16MHz SOT307-2 P87C54EFP N P87C58EFP N OTP –40 to +85, 40-Pin Plastic Dual In-line Package 16MHz SOT129-1 P87C54EFF FA P87C58EFF FA UV –40 to +85, 40-Pin Ceramic Dual In-line Package w/Window 16MHz 0590B P87C54EFA A P87C58EFA A OTP –40 to +85, 44-Pin Plastic Leaded Chip Carrier 16MHz SOT187-2 P87C54EFB B P87C58EFB B OTP –40 to +85, 44-Pin Plastic Quad Flat Pack 16MHz SOT307-2 P87C54IBP N P87C58IBP N OTP 0 to +70, 40-Pin Plastic Dual In-line Package 24MHz SOT129-1 P87C54IBF FA P87C58IBF FA UV 0 to +70, 40-Pin Ceramic Dual In-line Package w/Window 24MHz 0590B P87C54IBA A P87C58IBA A OTP 0 to +70, 44-Pin Plastic Leaded Chip Carrier 24MHz SOT187-2 P87C54IBL KA P87C58IBL KA UV 0 to +70, 44-Pin Ceramic Leaded Chip Carrier w/Window 24MHz 1472A P87C54IBB B P87C58IBB B OTP 0 to +70, 44-Pin Plastic Quad Flat Pack 24MHz SOT307-2 P87C54IFP N P87C58IFP N OTP –40 to +85, 40-Pin Plastic Dual In-line Package 24MHz SOT129-1 P87C54IFF FA P87C58IFF FA UV –40 to +85, 40-Pin Ceramic Dual In-line Package w/Window 24MHz 0590B P87C54IFA A P87C58IFA A OTP –40 to +85, 44-Pin Plastic Leaded Chip Carrier 24MHz SOT187-2 P87C54IFB B P87C58IFB B OTP –40 to +85, 44-Pin Plastic Quad Flat Pack 24MHz SOT307-2 NOTE: 1. OTP = One Time Programmable EPROM. UV = Erasable EPROM. LOGIC SYMBOL VCC VSS PORT 0 XTAL1 ADDRESS AND DATA BUS XTAL2 RST EA PORT 2 ALE RxD TxD INT0 INT1 T0 T1 WR RD PORT 3 SECONDARY FUNCTIONS PSEN PORT 1 T2 T2EX ADDRESS BUS SU00732 1996 Aug 16 3-216 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers 87C54/87C58 BLOCK DIAGRAM P0.0–P0.7 P2.0–P2.7 PORT 0 DRIVERS PORT 2 DRIVERS VCC VSS RAM ADDR REGISTER PORT 0 LATCH RAM B REGISTER PORT 2 LATCH ROM/EPROM STACK POINTER ACC PROGRAM ADDRESS REGISTER TMP1 TMP2 BUFFER ALU SFRs PC INCREMENTER TIMERS PSW PSEN ALE/PROG EA/VPP TIMING AND CONTROL RST INSTRUCTION REGISTER PROGRAM COUNTER PD DPTR PORT 1 LATCH PORT 3 LATCH PORT 1 DRIVERS PORT 3 DRIVERS P1.0–P1.7 P3.0–P3.7 OSCILLATOR XTAL1 XTAL2 SU00182 1996 Aug 16 3-217 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers Table 1. SYMBOL 87C54/87C58 87C54/87C58 Special Function Registers DESCRIPTION DIRECT ADDRESS BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB RESET VALUE ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H AUXR# Auxiliary 8EH – – – – – – – AO xxxxxxx0B B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H DPTR: DPH DPL Data Pointer (2 bytes) Data Pointer High Data Pointer Low 83H 82H IE* Interrupt Enable A8H 00H 00H AF AE AD AC AB AA A9 A8 EA – ET2 ES ET1 EX1 ET0 EX0 BF BE BD BC BB BA B9 B8 – PT2 PS PT1 PX1 PT0 PX0 IP* Interrupt Priority B8H – 87 86 85 84 83 82 81 80 P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 97 96 95 94 93 92 91 90 P1* Port 1 90H – – – – – – T2EX T2 A7 A6 A5 A4 A3 A2 A1 A0 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 B7 B6 B5 B4 B3 B2 B1 B0 P2* Port 2 A0H 00H x0000000B FFH FFH FFH P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TxD RxD FFH PCON# Power Control 87H SMOD1 SMOD0 – POF1 GF1 GF0 PD IDL 00xxxx00B D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program Status Word D0H CY AC F0 RS1 RS0 OV – P RCAP2H# RCAP2L# SADDR# SADEN# Timer 2 Capture High Timer 2 Capture Low Slave Address Slave Address Mask CBH CAH A9H B9H SBUF Serial Data Buffer 99H SCON* Serial Control 98H SP Stack Pointer 81H TCON* Timer Control 88H T2CON#* Timer 2 Control C8H TH0 TH1 TH2# TL0 TL1 TL2# Timer High 0 Timer High 1 Timer High 2 Timer Low 0 Timer Low 1 Timer Low 2 8CH 8DH CDH 8AH 8BH CCH TMOD Timer Mode 89H 00H 00H 00H 00H xxxxxxxxB 9F 9E 9D 9C 9B 9A 99 98 SM0 SM1 SM2 REN TB8 RB8 TI RI 8F 8E 8D 8C 8B 8A 89 88 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 CF CE CD CC CB CA C9 C8 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00H 07H 00H 00H 00H 00H 00H 00H 00H 00H C7 C6 C5 C4 C3 C2 C1 C0 GATE C/T M1 M0 GATE C/T M1 M0 – – – – – T2OE DCEN T2MOD#* Timer 2 Mode Control C9H – * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. 1. Reset value depends on reset source. 1996 Aug 16 00H 3-218 00H xxxxxx00B Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers CERAMIC AND PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS 87C54/87C58 PLASTIC QUAD FLAT PACK PIN FUNCTIONS 44 6 1 34 40 7 39 1 33 PQFP LCC 11 17 18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function NC* T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RxD/P3.0 NC* TxD/P3.1 INT0/P3.2 INT1/P3.3 * DO NOT CONNECT 1996 Aug 16 23 29 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 12 28 Function T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function P2.7/A15 PSEN ALE/PROG NC* EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC Function P1.5 P1.6 P1.7 RST RxD/P3.0 NC* TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 * DO NOT CONNECT SU00061 3-219 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 22 Function VSS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG NC* EA/VPP P0.7/AD7 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC NC* T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 SU00062 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers 87C54/87C58 PIN DESCRIPTIONS PIN NUMBER MNEMONIC DIP LCC QFP TYPE VSS 20 22 16 I Ground: 0V reference. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and receives code bytes during EPROM programming. External pull-ups are required during program verification. 1–8 2–9 40–44, 1–3 I/O 1 2 2 3 40 41 I I Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also receives the low-order address byte during program memory verification. Alternate functions include: T2 (P1.0): Timer/Counter 2 external count input/Clockout T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins receive the high order address bits during EPROM programming and verification. P3.0–P3.7 10–17 11, 13–19 5, 7–13 I/O 10 11 12 13 14 15 16 17 11 13 14 15 16 17 18 19 5 7 8 9 10 11 12 13 I O I I I I O O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe RST 9 10 4 I ALE/PROG 30 33 27 I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When the 8XC58 is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA/VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 7FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 7FFFH. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. If security bit 1 is programmed, EA will be internally latched on Reset. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. P0.0–0.7 P1.0–P1.7 NAME AND FUNCTION Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5V or VSS – 0.5V, respectively. 1996 Aug 16 3-220 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers 87C54/87C58 idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. TIMER 2 This is a 16-bit up or down counter, which can be operated as either a timer or event counter. It can be operated in one of three different modes (autoreload, capture or as the baud rate generator for the UART). In the autoreload mode the Timer can be set to count up or down by setting or clearing the bit DCEN in the T2CON Special Function Register. The SFR’s RCAP2H and RCAP2L are used to reload the Timer upon overflow or a 1-to-0 transition on the T2EX input (P1.1). Power-Down Mode To save even more power, a Power Down mode can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power Down mode is terminated. In the Capture mode Timer 2 can either set TF2 and generate an interrupt or capture its value. To capture Timer 2 in response to a 1-to-0 transition on the T2EX input, the EXEN2 bit in the T2CON must be set. Timer 2 is then captured in SFR’s RCAP2H and RCAP2L. On the 8XC58 either a hardware reset or external interrupt can use an exit from Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. As the baud rate generator, Timer 2 is selected by setting TCLK and/or RCLK in T2CON. As the baud rate generator Timer 2 is incremented at 1/2 the oscillator frequency. POWER OFF FLAG To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). The Power Off Flag (POF) is set by on-chip circuitry when the VCC level on the 8XC58 rises from 0 to 5V. The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. The VCC level must remain above 3V for the POF to remain unaffected by the VCC level. With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down. Design Consideration • When the idle mode is terminated by a hardware reset, the device OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. • Reset normally resumes program execution, from where it left off, up to two machine cycles before the internal rest algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. The windowed parts must be covered with an opaque label to assure proper chip operation. ONCE Mode A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up. Ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above VIH1 is applied to RESET. The ONCE (“On-Circuit Emulation”) Mode facilitates testing and debugging of systems using the 8XC58 without the 8XC58 having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the 8XC58 is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied. Idle Mode In the idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the Table 2. External Pin Status During Idle and Power-Down Mode PROGRAM MEMORY ALE PSEN Idle Internal 1 Idle External 1 Power-down Internal 0 Power-down External 0 MODE 1996 Aug 16 PORT 0 PORT 1 1 Data 1 Float 0 0 3-221 PORT 2 PORT 3 Data Data Data Data Address Data Data Data Data Data Float Data Data Data Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers 87C54/87C58 address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Programmable Clock-Out The 87C54/87C58 has a new feature. A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed (1) to input the external clock for Timer/Counter 2 or (2) to output a 50% duty cycle clock ranging from 61Hz to 4MHz at a 16MHz operating frequency. Slave 0 SADDR = SADEN = Given = 1100 0000 1111 1101 1100 00X0 To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. Slave 1 SADDR = SADEN = Given = 1100 0000 1111 1110 1100 000X The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation: In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. OscillatorFrequency 4 (65536 RCAP2H, RCAP2L) In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Enhanced UART The UART operates in all of the usual modes that are described in the first section of this book for the 80C51. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The 87C54/87C58 UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 1). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 2. SADDR = SADEN = Given = 1100 0000 1111 1001 1100 0XX0 Slave 1 SADDR = SADEN = Given = 1110 0000 1111 1010 1110 0X0X Slave 2 SADDR = SADEN = Given = 1110 0000 1111 1100 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary t make bit 2 = 1 to exclude slave 2. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 3. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are teated as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are loaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. this effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Reduced EMI Mode The AO bit (AUXR.0) in the AUXR register, when set, disables the ALE output. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “|Given” 1996 Aug 16 Slave 0 8XC58 Reduced EMI Mode AUXR (0X8E) 7 6 5 4 3 2 1 0 – – – – – – – AO AO: Turns off ALE output. 3-222 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers 87C54/87C58 equal or higher priority is not already being serviced. If an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed. Interrupt Priority Structure The 87C54/87C58 has a 6-source two-level interrupt structure. There are 3 SFRs associated with the interrupts. They are the IE and IP which are identical in function to those on the 80C51. The priority scheme for servicing the interrupts is the same as that for the 80C51. An interrupt will be serviced as long as an interrupt of Table 3. Interrupt Table SOURCE POLLING PRIORITY REQUEST BITS HARDWARE CLEAR? VECTOR ADDRESS X0 1 IE0 N (L) Y (T) 03H T0 2 TP0 Y 0B X1 3 IE1 N (L) Y (T) 13 T1 4 TF1 Y 1B SP 5 R1, TI N 23 T2 6 TF2, EXF2 N 2B SCON Address = 98H Reset Value = 0000 0000B Bit Addressable SM0/FE Bit: SM1 7 6 (SMOD0 = 0/1)* SM2 REN TB8 RB8 Tl Rl 5 4 3 2 1 0 Symbol Function FE Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. SM0 Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0) SM1 Serial Port Mode Bit 1 SM0 SM1 Mode 0 0 1 1 0 1 0 1 0 1 2 3 Description Baud Rate** shift register 8-bit UART 9-bit UART 9-bit UART fOSC/12 variable fOSC/64 or fOSC/32 variable SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Tl Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Rl Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. NOTE: *SMOD0 is located at PCON6. **fOSC = oscillator frequency SU00043 Figure 1. SCON: Serial Port Control Register 1996 Aug 16 3-223 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers D0 D1 D2 D3 START BIT 87C54/87C58 D4 D5 D6 D7 D8 DATA BYTE ONLY IN MODE 2, 3 STOP BIT SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL SM0 / FE SM1 SM2 REN TB8 RB8 TI RI SCON (98H) SMOD1 SMOD0 OSF POF LVF GF0 GF1 IDL PCON (87H) 0 : SCON.7 = SM0 1 : SCON.7 = FE SU00044 Figure 2. UART Framing Error Detection D0 D1 D2 D3 D4 SM0 SM1 1 1 1 0 D5 SM2 1 D6 D7 D8 REN TB8 RB8 1 X TI RI SCON (98H) RECEIVED ADDRESS D0 TO D7 COMPARATOR PROGRAMMED ADDRESS IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS” – WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. SU00045 Figure 3. UART Multiprocessor Communication, Automatic Address Recognition ABSOLUTE MAXIMUM RATINGS1, 2, 3 PARAMETER Operating temperature under bias Storage temperature range Voltage on EA/VPP pin to VSS Voltage on any other pin to VSS RATING UNIT 0 to +70 or –40 to +85 °C –65 to +150 °C 0 to +13.0 V –0.5 to +6.5 V Maximum IOL per I/O pin 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 1996 Aug 16 3-224 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers 87C54/87C58 DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V TEST SYMBOL PARAMETER VIL Input low voltage, except EA VIL1 Input low voltage to EA VIH1 Input high voltage, XTAL1, RST VOL Output low voltage, ports 1, 2, 37 PSEN7 CONDITIONS LIMITS MIN TYP1 MAX UNIT –0.5 0.2VCC–0.1 V 0 0.2VCC–0.3 V 0.7VCC VCC+0.5 V 0.45 V 0.45 V IOL = 1.6mA2 VOL1 Output low voltage, port 0, ALE, VOH Output high voltage, ports 1, 2, 3 3 IOH = –30µA VCC – 0.7 V VOH1 Output high voltage (port 0 in external bus mode), ALE8, PSEN3 IOH = –3.2mA VCC – 0.7 V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4V –50 µA ITL Logical 1-to-0 transition current, ports 1, 2, 35 See note 4 –650 µA ILI Input leakage current, port 0 0.45 VIN < VCC – 0.3 ±10 µA ICC Power supply current (See Figure 11): Active mode @ 16MHz Idle mode @ 16MHz Power-down mode Tamb = 0 to +70°C Tamb = –40 to +85°C 32 5 75 100 mA mA µA µA RRST Internal reset pull-down resistor 225 kΩ 15 pF CIO Pin capacitance9 IOL = 3.2mA2 See note 10 15 3 10 40 (except EA) NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. This value applies to Tamb = 0°C to +70°C. For Tamb = –40°C to 85°C, ITL = –750µA. 6. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 7. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15mA Maximum IOL per port pin: 26mA Maximum IOL per 8-bit port: 71mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 8. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. 9. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA it is 25pF). 10. See Figures 12 through 15 for ICC test condition. 1996 Aug 16 3-225 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers 87C54/87C58 AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 16MHz CLOCK SYMBOL FIGURE 1/tCLCL 4 PARAMETER Oscillator frequency Speed versions MIN MAX VARIABLE CLOCK MIN MAX UNIT 3.5 16 MHz :E tLHLL 4 ALE pulse width 85 2tCLCL–40 ns tAVLL 4 Address valid to ALE low 22 tCLCL–40 ns tLLAX 4 Address hold after ALE low 32 tCLCL–30 ns tLLIV 4 ALE low to valid instruction in tLLPL 4 ALE low to PSEN low 32 tPLPH 4 PSEN pulse width 142 tPLIV 4 PSEN low to valid instruction in tPXIX 4 Input instruction hold after PSEN tPXIZ 4 Input instruction float after PSEN 37 tCLCL–25 ns tAVIV 4 Address to valid instruction in 207 5tCLCL–105 ns tPLAZ 4 PSEN low to address float 10 10 ns 150 4tCLCL–100 tCLCL–30 ns 3tCLCL–45 82 0 ns ns 3tCLCL–105 0 ns ns Data Memory tRLRH 5, 6 RD pulse width 275 6tCLCL–100 ns tWLWH 5, 6 WR pulse width 275 tRLDV 5, 6 RD low to valid data in tRHDX 5, 6 Data hold after RD tRHDZ 5, 6 Data float after RD 65 2tCLCL–60 ns tLLDV 5, 6 ALE low to valid data in 350 8tCLCL–150 ns tAVDV 5, 6 Address to valid data in 9tCLCL–165 ns tLLWL 5, 6 ALE low to RD or WR low 137 3tCLCL+50 ns tAVWL 5, 6 Address valid to WR low or RD low 122 4tCLCL–130 ns tQVWX 5, 6 Data valid to WR transition 13 tCLCL–50 ns tWHQX 5, 6 Data hold after WR 13 tCLCL–50 ns tQVWH 6 Data valid to WR high 287 7tCLCL–150 ns tRLAZ 5, 6 RD low to address float tWHLH 5, 6 RD or WR high to ALE high 23 6tCLCL–100 147 0 ns 5tCLCL–165 0 397 239 3tCLCL–50 0 103 ns ns 0 ns tCLCL–40 tCLCL+40 ns 20 tCLCL+tCLCX ns 20 External Clock tCHCX 8 High time 20 tCLCX 8 Low time 20 tCLCL+tCHCX ns tCLCH 8 Rise time 20 20 ns tCHCL 8 Fall time 20 20 ns tXLXL 7 Serial port clock cycle time 750 12tCLCL ns tQVXH 7 Output data setup to clock rising edge 492 10tCLCL–133 ns tXHQX 7 Output data hold after clock rising edge 8 2tCLCL–117 ns tXHDX 7 Input data hold after clock rising edge 0 0 ns Shift Register tXHDV 7 Clock rising edge to input data valid 492 10tCLCL–133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 8XC58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 1996 Aug 16 3-226 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers 87C54/87C58 AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 24MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX VARIABLE CLOCK4 MIN MAX UNIT 3.5 24 MHz 1/tCLCL 4 Oscillator frequency Speed versions : I tLHLL 4 ALE pulse width 43 2tCLCL–40 ns tAVLL 4 Address valid to ALE low 17 tCLCL–25 ns tLLAX 4 Address hold after ALE low 17 tLLIV 4 ALE low to valid instruction in tLLPL 4 ALE low to PSEN low 17 tCLCL–25 ns tPLPH 4 PSEN pulse width 80 3tCLCL–45 ns tPLIV 4 PSEN low to valid instruction in tPXIX 4 Input instruction hold after PSEN tPXIZ 4 Input instruction float after PSEN 17 tCLCL–25 ns tAVIV 4 Address to valid instruction in 128 5tCLCL–80 ns tPLAZ 4 PSEN low to address float 10 10 ns tCLCL–25 102 65 0 ns 4tCLCL–65 3tCLCL–60 0 ns ns ns Data Memory tRLRH 5, 6 RD pulse width 150 6tCLCL–100 ns tWLWH 5, 6 WR pulse width 150 6tCLCL–100 ns tRLDV 5, 6 RD low to valid data in tRHDX 5, 6 Data hold after RD tRHDZ 5, 6 Data float after RD 55 2tCLCL–28 ns tLLDV 5, 6 ALE low to valid data in 183 8tCLCL–150 ns tAVDV 5, 6 Address to valid data in 210 9tCLCL–165 ns tLLWL 5, 6 ALE low to RD or WR low 75 3tCLCL+50 ns tAVWL 5, 6 Address valid to WR low or RD low 92 4tCLCL–75 ns tQVWX 5, 6 Data valid to WR transition 12 tCLCL–30 ns tWHQX 5, 6 Data hold after WR 17 tCLCL–25 ns Data valid to WR high 162 118 0 tQVWH 6 tRLAZ 5, 6 RD low to address float tWHLH 5, 6 RD or WR high to ALE high 17 5tCLCL–90 0 175 3tCLCL–50 ns 7tCLCL–130 0 67 tCLCL–25 ns ns 0 ns tCLCL+25 ns External Clock tCHCX 8 High time 17 17 tCLCL–tCLCX ns tCLCX 8 Low time 17 17 tCLCL–tCHCX ns tCLCH 8 Rise time 5 5 ns tCHCL 8 Fall time 5 5 ns tXLXL 7 Serial port clock cycle time 505 12tCLCL ns tQVXH 7 Output data setup to clock rising edge 283 10tCLCL–133 ns tXHQX 7 Output data hold after clock rising edge 3 2tCLCL–80 ns tXHDX 7 Input data hold after clock rising edge 0 0 ns Shift Register tXHDV 7 Clock rising edge to input data valid 283 10tCLCL–133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 87C58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Variable clock is specified for oscillator frequencies greater than 16MHz to 24MHz. For frequencies equal or less than 16MHz, see 16MHz “AC Electrial Characteristics”, page 3-226. 1996 Aug 16 3-227 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers 87C54/87C58 EXPLANATION OF THE AC SYMBOLS P – PSEN Q – Output data R – RD signal t – Time V – Valid W – WR signal X – No longer a valid logic level Z – Float Examples: tAVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low. Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A – Address C – Clock D – Input data H – Logic level high I – Instruction (program memory contents) L – Logic level low, or ALE tLHLL ALE tAVLL tLLPL tPLPH tLLIV tPLIV PSEN tLLAX A0–A7 PORT 0 tPXIZ tPLAZ tPXIX A0–A7 INSTR IN tAVIV PORT 2 A0–A15 A8–A15 SU00006 Figure 4. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL tRLRH RD tAVLL tLLAX tRLAZ PORT 0 tRHDZ tRLDV tRHDX A0–A7 FROM RI OR DPL DATA IN A0–A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH SU00025 Figure 5. External Data Memory Read Cycle 1996 Aug 16 3-228 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers 87C54/87C58 ALE tWHLH PSEN tWLWH tLLWL WR tLLAX tAVLL tWHQX tQVWX tQVWH A0–A7 FROM RI OR DPL PORT 0 DATA OUT A0–A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH SU00026 Figure 6. External Data Memory Write Cycle INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE tXLXL CLOCK tXHQX tQVXH OUTPUT DATA 0 1 2 WRITE TO SBUF 3 4 5 6 7 tXHDX tXHDV SET TI INPUT DATA VALID VALID VALID VALID VALID VALID VALID VALID CLEAR RI SET RI SU00027 Figure 7. Shift Register Mode Timing VCC–0.5 0.45V 0.7VCC 0.2VCC–0.1 tCHCL tCHCX tCLCH tCLCX tCLCL SU00009 Figure 8. External Clock Drive 1996 Aug 16 3-229 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers VCC–0.5 87C54/87C58 VLOAD+0.1V 0.2VCC+0.9 TIMING REFERENCE POINTS VLOAD 0.45V 0.2VCC–0.1 VLOAD–0.1V VOH–0.1V VOL+0.1V NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL ≥ ±20mA. NOTE: AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. SU00717 SU00718 Figure 9. AC Testing Input/Output Figure 10. Float Waveform 45 MAX ACTIVE MODE ICCMAX = 1.50 X FREQ. + 8 40 35 30 TYP ACTIVE MODE 0.9 X FREQ. + 2.5 25 ICC mA 20 15 10 MAX IDLE MODE 5 TYP IDLE MODE 4MHz 8MHz 12MHz 16MHz 20MHz 24MHz FREQ AT XTAL1 SU00046 Figure 11. ICC vs. Frequency 1996 Aug 16 3-230 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers 87C54/87C58 VCC VCC ICC ICC VCC VCC VCC VCC RST RST VCC P0 P0 EA EA (NC) XTAL2 (NC) XTAL2 CLOCK SIGNAL XTAL1 CLOCK SIGNAL XTAL1 VSS VSS SU00719 SU00720 Figure 12. ICC Test Condition, Active Mode All other pins are disconnected VCC–0.5 Figure 13. ICC Test Condition, Idle Mode All other pins are disconnected 0.7VCC 0.45V 0.2VCC–0.1 tCHCL tCHCX tCLCH tCLCX tCLCL SU00015 Figure 14. Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns VCC ICC VCC VCC RST P0 EA (NC) XTAL2 XTAL1 VSS SU00016 Figure 15. ICC Test Condition, Power Down Mode All other pins are disconnected. VCC = 2V to 5.5V 1996 Aug 16 3-231 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers shown in Figure 18. The other pins are held at the ‘Verify Code Data’ levels indicated in Table 4. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. EPROM CHARACTERISTICS The 87C58 is programmed by using a modified Improved Quick-Pulse Programming algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. If the 32 byte encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. The 87C58 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87C58 manufactured by Philips. Table 4 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 16 and 17. Figure 18 shows the circuit configuration for normal program memory verification. Program/Verify Algorithms Any algorithm in agreement with the conditions listed in Table 4, and which satisfies the timing specifications, is suitable. Erasure Characteristics Erasure of the EPROM begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadvertent erasure. For this and secondary effects, it is recommended that an opaque label be placed over the window. For elevated temperature or environments where solvents are being used, apply Kapton tape Fluorglas part number 2345–5, or equivalent. Quick-Pulse Programming The setup for microcontroller quick-pulse programming is shown in Figure 16. Note that the 87C58 is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 16. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 2 and 3 specified in Table 4 are held at the ‘Program Code Data’ levels indicated in Table 4. The ALE/PROG is pulsed low 5 times as shown in Figure 17. The recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrated dose of at least 15W-s/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000µW/cm2 rating for 20 to 39 minutes, at a distance of about 1 inch, should be sufficient. To program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 1FH, using the ‘Pgm Encryption Table’ levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. Erasure leaves the array in an all 1s state. To program the security bits, repeat the 25 pulse programming sequence using the ‘Pgm Security Bit’ levels. After one security bit is programmed, further programming of the code memory and encryption table is disabled. However, the other security bit can still be programmed. Security Bits With none of the security bits programmed the code in the program memory can be verified. If the encryption table is programmed, the code will be encrypted when verified. When only security bit 1 (see Table 5) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory, EA is latched on Reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot. Program Verification If security bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 1 and 2 as Encryption Array 32 bytes of encryption array are initially unprogrammed (all 1s). Trademark phrase of Intel Corporation. 1996 Aug 16 87C54/87C58 3-232 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers 87C54/87C58 Table 4. EPROM Programming Modes RST PSEN ALE/PROG EA/VPP P2.7 P2.6 P3.7 P3.6 P3.3 Read signature MODE 1 0 1 1 0 0 0 0 0 Program code data 1 0 0* VPP 1 0 1 1 1 Verify code data 1 0 1 1 0 0 1 1 0 Pgm encryption table 1 0 0* VPP 1 0 1 0 1 Pgm security bit 1 1 0 0* VPP 1 1 1 1 1 Pgm security bit 2 1 0 0* VPP 1 1 0 0 1 NOTES: 1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin. 2. VPP = 12.75V ±0.25V. 3. VCC = 5V±10% during programming and verification. * ALE/PROG receives 5 programming pulses (only for user array; 25 pulses for encryption or security bits) while VPP is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high for a minimum of 10µs. Table 5. Program Security Bits PROGRAM LOCK BITS1, 2 SB1 SB2 PROTECTION DESCRIPTION 1 U U No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.) 2 P U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled. 3 P P Same as 2, also verify is disabled. NOTES: 1. P – programmed. U – unprogrammed. 2. Any other combination of the security bits is not defined. 1996 Aug 16 3-233 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers 87C54/87C58 +5V A0–A7 VCC P1 P0 1 RST 1 P3.6 EA/VPP 1 P3.7 ALE/PROG 1 P3.3 87C54 87C58 XTAL2 4–6MHz XTAL1 PGM DATA +12.75V 5 100µs PULSES TO GROUND PSEN 0 P2.7 1 P2.6 0 A8–A13 P2.0–P2.5 VSS A14 P3.4 SU00183A Figure 16. Programming Configuration 5 PULSES 1 ALE/PROG: 0 10µs MIN 100µs+10 1 ALE/PROG: 0 SU00179 Figure 17. PROG Waveform +5V VCC A0–A7 P0 P1 1 RST 1 P3.6 1 P3.7 0 P3.3 87C54 87C58 XTAL2 4–6MHz XTAL1 EA/VPP 1 ALE/PROG 1 PSEN 0 P2.7 0 P2.6 0 P2.0–P2.5 VSS PGM DATA P3.4 A8–A13 A14 SU00185B Figure 18. Program Verification 1996 Aug 16 3-234 Philips Semiconductors Preliminary specification CMOS single-chip 8-bit microcontrollers 87C54/87C58 EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS Tamb = 21°C to +27°C, VCC = 5V±10%, VSS = 0V (See Figure 19) PARAMETER SYMBOL MIN MAX UNIT 12.5 13.0 V 50 1 mA 6 MHz VPP Programming supply voltage IPP Programming supply current 1/tCLCL Oscillator frequency tAVGL Address setup to PROG low 48tCLCL tGHAX Address hold after PROG 48tCLCL tDVGL Data setup to PROG low 48tCLCL tGHDX Data hold after PROG 48tCLCL tEHSH P2.7 (ENABLE) high to VPP 48tCLCL tSHGL VPP setup to PROG low 10 µs tGHSL VPP hold after PROG 10 µs tGLGH PROG width 90 tAVQV Address to data valid 48tCLCL tELQZ ENABLE low to data valid 48tCLCL tEHQZ Data float after ENABLE 0 tGHGL PROG high to PROG low 10 4 110 µs 48tCLCL µs NOTE: 1. Not tested. PROGRAMMING* VERIFICATION* P1.0–P1.7 P2.0–P2.5 P3.4 (A0 – A14) ADDRESS ADDRESS PORT 0 P0.0 – P0.7 (D0 – D7) DATA IN tAVQV DATA OUT tDVGL tAVGL tGHDX tGHAX ALE/PROG tGLGH tSHGL tGHGL tGHSL LOGIC 1 LOGIC 1 EA/VPP LOGIC 0 tEHSH tELQV tEHQZ P2.7 ENABLE SU00180 * FOR PROGRAMMING VERIFICATION SEE FIGURE 16. FOR VERIFICATION CONDITIONS SEE FIGURE 18. Figure 19. EPROM Programming and Verification 1996 Aug 16 3-235