PD - 94162
Advanced Process Technology
Surface Mount (IRL3103S)
l Low-profile through-hole (IRL3103L)
l 175°C Operating Temperature
l Fast Switching
l Fully Avalanche Rated
Description
IRL3103S
IRL3103L
l
HEXFET® Power MOSFET
l
Advanced HEXFET® Power MOSFETs from International
D
VDSS = 30V
RDS(on) = 12mΩ
G
Rectifier utilize advanced processing techniques to
achieve extremely low on-resistance per silicon area.
This benefit, combined with the fast switching speed and
ruggedized device design that HEXFET power MOSFETs
are well known for, provides the designer with an
extremely efficient and reliable device for use in a wide
variety of applications.
ID = 64A
S
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible onresistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of its
low internal connection resistance and can dissipate up to
2.0W in a typical surface mount application.
The through-hole version (IRL3103L) is available for lowprofile applications.
D2Pak
IRL3103S
TO-262
IRL3103L
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 srew
Max.
Units
64
45
220
94
0.63
± 16
34
22
5.0
-55 to + 175
A
W
W/°C
V
A
mJ
V/ns
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθJA
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Junction-to-Case
Junction-to-Ambient (PCB mount)**
Typ.
Max.
Units
–––
–––
1.6
40
°C/W
1
02/14/02
IRL3103S/IRL3103L
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
30
–––
–––
–––
1.0
22
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
LS
Internal Source Inductance
–––
Ciss
Coss
Crss
EAS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Single Pulse Avalanche Energy
–––
–––
–––
–––
V(BR)DSS
IGSS
Typ.
–––
0.028
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
8.9
120
14
9.1
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
12
VGS = 10V, ID = 34A
mΩ
16
VGS = 4.5V, ID = 28A
–––
V
VDS = VGS, ID = 250µA
–––
S
VDS = 25V, ID = 34A
25
VDS = 30V, VGS = 0V
µA
250
VDS = 24V, VGS = 0V, TJ = 150°C
100
VGS = 16V
nA
-100
VGS = -16V
33
ID = 34A
5.9
nC
VDS = 24V
17
VGS = 4.5V, See Fig. 6 and 13
–––
VDD = 15V
–––
ID = 34A
–––
RG = 1.8Ω
–––
VGS = 4.5V, See Fig. 10
Between lead,
4.5 –––
6mm (0.25in.)
nH
G
from package
7.5 –––
and center of die contact
1650 –––
VGS = 0V
650 –––
VDS = 25V
110 –––
pF
ƒ = 1.0MHz, See Fig. 5
1320
130 mJ IAS = 34A, L = 0.22mH
D
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
64
––– –––
showing the
A
G
integral reverse
––– ––– 220
S
p-n junction diode.
––– ––– 1.2
V
TJ = 25°C, IS = 34A, VGS = 0V
––– 57
86
ns
TJ = 25°C, IF = 34A
––– 110 170
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)
Starting TJ = 25°C, L = 220µH
RG = 25Ω, IAS = 34A, VGS=10V (See Figure 12)
ISD ≤ 34A, di/dt ≤ 120A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
2
Pulse width ≤ 400µs; duty cycle ≤ 2%.
This is a typical value at device destruction and represents
operation outside rated limits.
This is a calculated value limited to TJ = 175°C .
**When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint and soldering techniques refer to
application note #AN-994
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IRL3103S/IRL3103L
1000
1000
VGS
15V
10V
4.5V
3.7V
3.5V
3.3V
3.0V
BOTTOM 2.7V
VGS
15V
10V
4.5V
3.7V
3.5V
3.3V
3.0V
BOTTOM 2.7V
100
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
100
10
2.7V
20µs PULSE WIDTH
T = 25 C
°
J
1
0.1
1
10
2.7V
10
100
Fig 1. Typical Output Characteristics
TJ = 25 ° C
TJ = 175 ° C
10
V DS = 15V
20µs PULSE WIDTH
4.0
5.0
6.0
7.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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8.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
2.5
3.0
1
10
100
Fig 2. Typical Output Characteristics
1000
1
2.0
°
J
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
100
20µs PULSE WIDTH
T = 175 C
1
0.1
ID = 56A
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRL3103S/IRL3103L
VGS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
C, Capacitance (pF)
2500
Ciss
2000
Coss
1500
1000
500
C
rss
15
VGS , Gate-to-Source Voltage (V)
3000
0
1
10
ID = 34A
12
VDS = 24V
VDS = 15V
9
6
3
FOR TEST CIRCUIT
SEE FIGURE 13
0
100
0
VDS , Drain-to-Source Voltage (V)
1000
30
40
1000
OPERATION IN THIS AREA
LIMITED BY R DS (on)
100
ID , Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
20
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
TJ = 175 ° C
10
TJ = 25 ° C
1
0.1
0.0
V GS = 0 V
0.4
0.8
1.2
1.6
2.0
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10
Q G , Total Gate Charge (nC)
2.4
100
100µsec
10
1msec
Tc = 25°C
Tj = 175°C
Single Pulse
1
1
10msec
10
100
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRL3103S/IRL3103L
70
VDS
I D , Drain Current (A)
60
VGS
RD
D.U.T.
RG
50
+
-VDD
40
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
30
20
Fig 10a. Switching Time Test Circuit
VDS
10
90%
0
25
50
75
100
125
TC , Case Temperature
150
175
( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
0.05
0.1
0.02
0.01
P DM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRL3103S/IRL3103L
L
VD S
D .U .T
RG
IA S
2V0GS
V
tp
D R IV E R
+
- VD D
A
0 .0 1 Ω
Fig 12a. Unclamped Inductive Test Circuit
V (B R )D SS
tp
EAS , Single Pulse Avalanche Energy (mJ)
240
1 5V
ID
14A
24A
34A
TOP
200
BOTTOM
160
120
80
40
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature ( °C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
VGS
QGS
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
IG
Charge
Fig 13a. Basic Gate Charge Waveform
6
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRL3103S/IRL3103L
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
RG
VGS
*
+
-
VDD
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
[ ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 14. For N-channel HEXFET® power MOSFETs
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7
IRL3103S/IRL3103L
D2Pak Package Outline
1 0.54 (.415 )
1 0.29 (.405 )
1.4 0 (.055 )
M AX.
-A-
1.3 2 (.05 2)
1.2 2 (.04 8)
2
1.7 8 (.07 0)
1.2 7 (.05 0)
1
10 .1 6 (.4 00 )
R E F.
-B-
4 .6 9 (.18 5)
4 .2 0 (.16 5)
6.47 (.2 55 )
6.18 (.2 43 )
3
1 5.49 (.6 10)
1 4.73 (.5 80)
2.7 9 (.110 )
2.2 9 (.090 )
2.61 (.1 03 )
2.32 (.0 91 )
5.28 (.2 08 )
4.78 (.1 88 )
3X
1.40 (.0 55)
1.14 (.0 45)
5 .08 (.20 0)
0.55 (.0 22)
0.46 (.0 18)
0.9 3 (.0 37 )
3X
0.6 9 (.0 27 )
0.25 (.0 10 )
M
8.8 9 (.3 50 )
R E F.
1.3 9 (.0 55 )
1.1 4 (.0 45 )
B A M
M IN IM U M R EC O M M E ND E D F O O TP R IN T
1 1.43 (.4 50 )
NO TE S:
1 D IM EN S IO N S A FTER SO LD E R D IP .
2 D IM EN S IO N IN G & TO LE R AN C IN G P ER AN S I Y1 4.5M , 19 82 .
3 C O N TRO L LIN G D IM EN S IO N : IN C H.
4 H E ATSINK & L EA D D IM E N SIO N S DO N O T IN C LU D E B U R RS .
LE AD AS SIG N M E N TS
1 - G ATE
2 - D RA IN
3 - SO U R C E
8 .89 (.35 0)
17 .78 (.70 0)
3.81 (.1 5 0)
2.0 8 (.08 2)
2X
2.5 4 (.100 )
2X
D2Pak Part Marking Information
IN TE R N A TIO N A L
R E C T IF IE R
LO G O
A S S E M B LY
LO T C O D E
8
A
PART NUM BER
F530S
9 24 6
9B
1M
DATE CODE
(Y YW W )
YY = Y E A R
W W = W EEK
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IRL3103S/IRL3103L
TO-262 Package Outline
TO-262 Part Marking Information
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9
IRL3103S/IRL3103L
D2Pak Tape & Reel Information
TR R
1 .6 0 (.0 6 3 )
1 .5 0 (.0 5 9 )
4 .1 0 ( .1 6 1 )
3 .9 0 ( .1 5 3 )
F E E D D IR E C TIO N 1 .8 5 ( .0 7 3 )
1 .6 5 ( .0 6 5 )
1 .6 0 (.0 6 3 )
1 .5 0 (.0 5 9 )
0.3 6 8 (.01 4 5 )
0.3 4 2 (.01 3 5 )
1 1.6 0 (.4 57 )
1 1.4 0 (.4 49 )
1 5 .42 (.60 9 )
1 5 .22 (.60 1 )
2 4 .3 0 (.9 5 7 )
2 3 .9 0 (.9 4 1 )
TRL
1 0.9 0 (.4 2 9)
1 0.7 0 (.4 2 1)
1 .75 (.06 9 )
1 .25 (.04 9 )
4 .7 2 (.1 3 6)
4 .5 2 (.1 7 8)
16 .1 0 (.63 4 )
15 .9 0 (.62 6 )
F E E D D IR E C T IO N
13.50 (.532 )
12.80 (.504 )
2 7.4 0 (1.079 )
2 3.9 0 (.9 41)
4
3 30 .00
( 14.1 73 )
MAX.
6 0.0 0 (2.36 2)
M IN .
N O TE S :
1 . CO M F OR M S TO E IA -418 .
2 . CO N TR O L LIN G D IM E N SIO N : M IL LIM E T ER .
3 . DIM E NS IO N M EA S UR E D @ H U B.
4 . IN C LU D ES FL AN G E DIST O R T IO N @ O UT E R E D G E.
26 .40 (1 .03 9)
24 .40 (.9 61 )
3
30.4 0 (1.19 7)
M A X.
4
Data and specifications subject to change without notice.
This product has been designed and qualified for the industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.02/02
10
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