SAE 81C52 256 x 8-Bit Static CMOS RAM NMOS-Compatible Preliminary DataCMOS IC PFeatures ● ● ● ● ● ● ● ● 256 x 8-bit organization Standby mode Compatible with the NMOS and CMOS versions of the microprocessor/microcontroller families SAB 8086, SAB 8051 Very low power dissipation Data retention up to VDD ≥ 1 V Three different chip select inputs for two chip select modes No increasing power consumption in standby mode if the control inputs are on undefined potential Temperature range – 40 to 110 °C P-DIP-16-1 P-DSO-20-1 Type Ordering Code Package SAE 81C52 P Q67100-H9017 P-DIP-16-1 SAE 81C52 G Q67100-H9015 P-DSO-20-1 (SMD) The SAE 81C52 is a CMOS-silicon gate, static random access memory (RAM), organized as 256 words by 8 bits. The multiplexed address and data bus interfaces directly to 8-bit microprocessors/microcontrollers without any timing or level problems, e.g. the families SAB 8086, SAB 8051. All inputs and outputs are fully compatible with NMOS circuits, except CS1. Data retention is ensured up to VDD ≥ 1.0 V. The SAE 81C52 has three different inputs for two chip select modes which allow to inhibit either the address/data lines (AD 0 … AD 7) and the control lines (WR, RD, ALE, CS2, CS3), or only the control lines RD, WR. The power consumption is max. 5.5 µW in standby mode and max. 16.5 mW in operation. In standby mode, the power consumption will not increase if the control inputs are on undefined potential. Semiconductor Group 1 09.94 SAE 81C52 Pin Configurations (top view) SAE 81C52 P Semiconductor Group SAE 81C52 G 2 SAE 81C52 Pin Definitions and Functions SAE 81C52 G SAE 81C52 P Symbol Function Pin No. Pin No. 1, 2, 4, 5, 6 7, 12, 14 1…6 10, 11 AD0 … 7 Address/data lines 15 12 CS1 Chip select 1 (standby) active low; inhibits all lines including control lines 16 13 ALE Address latch enable 17 19 14 15 WR RD Write enable Read enable 20 16 VDD Power supply 9 7 VSS GND (0 V) 10 8 CS2 11 9 CS3 Chip select 2; inhibits control inputs RD, WR Counterpart to CS2 Semiconductor Group 3 SAE 81C52 Block Diagram Semiconductor Group 4 SAE 81C52 Logic Symbol Truth Table CS1 CS2 CS3 ALE RD WR AD0 … AD7 Function L H H H H H * X H H L X * X L L X H * H L L L L * H L H X X * H H L X X Floating (tristate) Addresses to memory Data from memory Data to memory Floating (tristate) Floating (tristate) Standby Store addresses Read Write None None *: Level = VSS … VDD X: Level = low or high Semiconductor Group 5 SAE 81C52 Absolute Maximum Ratings TA = – 40 to 110 °C Parameter Symbol Limit Values Unit Supply voltage referred to GND (VSS) All input and output voltages VDD VIM 0 to 6 VSS – 0.3 VDD + 0.3 V V V Total power dissipation Power dissipation for each output Ptot PQ 250 50 mW mW Junction temperature Storage temperature Tj Tstg 125 – 55 to 125 °C °C Thermal resistance system - air P-DIP-16-1 P-DSO-20-1 Rth SA Rth SA 70 95 K/W K/W Supply voltage VDD 4.5 to 5.5 V Ambient temperature TA – 40 to 110 °C Operating Range Semiconductor Group 6 SAE 81C52 DC Characteristics TA = – 40 to 110 °C; VDD = 4.25 V to 5.5 V; VSS = 0 V Parameter Symbol Limit Values min. Unit Test Condition VDD = 5.5 V; TA = 25 °C; VCS1 = 0 V ∆tcyc = 1 µs; VDD = 5.5 V; CL = 100 pF max. Standby supply current IDD 1 µA Supply current IDD 3 mA Standby voltage for data retention VDD L-input current (for each input) Output leakage current IIL 1 µA VI = 0 to VDD IQLK 1 µA VQ = 0 to VDD 1.0 V tristate L-input voltage H-input voltage VIL VIH L-output voltage H-output voltage VQL VQH 2.6 L-input voltage CS1 H-input voltage CS1 VIL VIH VSS VDD – 1 Semiconductor Group VSS 0.8 2.2 VDD 7 V V 0.4 V V 1 V V VDD IQL = 1 mA IQL = 1 mA SAE 81C52 AC Characteristics TA = – 40 to 110 °C; VDD = 4.5 to 5.5 V; VSS = 0 V Parameter Symbol Limit Values min. Unit max. ALE pulse width ALE low before RD low RD high before ALE high ALE low before WR low WR high before ALE high tLHLL tLLRL tRHLH tLLWL tWHLH 100 50 18 50 18 ns ns ns ns ns Address setup before ALE Address hold after ALE WR or RD pulse width tAVLL tLLAX tWLWH 18 30 250 ns ns ns Data setup before WR Data hold after WR Data hold after RD tQVWH tWHQX tRHDX 50 18 ns ns ns Chip select (2, 3) before RD, WR Chip select (2, 3) after RD, WR Chip select 1 before ALE Chip select 1 after RD, WR tCS tSC tCSLH tCSWH 50 18 20 50 Output delay time tRLDV 200 ns Input capacitance to VSS (for each input) CI 10 pF Semiconductor Group 8 90 ns ns ns ns SAE 81C52 Timing Diagram Semiconductor Group 9 SAE 81C52 Application Circuit SAE 81C52 with the µC SAB 8051 Semiconductor Group 10