INFINEON SAB-C161O-L16M

Microcomputer Components
16-Bit CMOS Single-Chip Microcontroller
ht
Data Sheet 03.97 Preliminary
tp
:/
Se /ww
m w
ic .s
on ie
du me
ct ns
or .d
/ e/
C161V/C161K/C161O
C166-Family of
High-Performance CMOS 16-Bit Microcontrollers
Preliminary
C161V, C161K, C161O
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
C161
16-Bit Microcontrollers
High Performance 16-bit CPU with 4-Stage Pipeline
125 ns Instruction Cycle Time at 16-MHz CPU Clock
625 ns Multiplication (16 × 16 bits), 1,25 µs Division (32 / 16 bit)
Enhanced Boolean Bit Manipulation Facilities
Additional Instructions to Support HLL and Operating Systems
Register-Based Design with Multiple Variable Register Banks
Single-Cycle Context Switching Support
Clock Generation via Prescaler or via Direct Clock Input
Up to 4 MBytes Linear Address Space for Code and Data
1 KByte On-Chip RAM on C161V and C161K, 2 KBytes On-Chip RAM on C161O
Programmable External Bus Characteristics for Different Address Ranges
8-Bit or 16-Bit External Data Bus
Multiplexed or Demultiplexed External Address/Data Buses (MUX Bus only on C161V)
Programmable Chip-Select Signals (not on C161V)
1024 Bytes On-Chip Special Function Register Area
Idle and Power Down Modes (not on C161V)
8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event
Controller (PEC)
16-Priority-Level Interrupt System with 14 Sources on C161V, 20 Sources on C161K, C161O
Multi-Functional General Purpose Timer Unit(s)
Synchronous/Asynchronous Serial Channel
High-Speed-Synchronous Serial Channel
Programmable Watchdog Timer
Up to 63 General Purpose I/O Lines
Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler
Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer
Disassemblers, Programming Boards
Ambient Temperature Range 0 to 70 ˚C
80-Pin MQFP Package (0.65 mm pitch)
This document describes the SAB-C161V-L16M, the SAB-C161K-L16M and the
SAB-C161O-L16M.
For simplicity all versions are referred to by the term C161 throughout this document whenever
possible.
Semiconductor Group
1
09.96
C161
1996 Intermediate Version
Introduction
The C161 is a new derivative of the Siemens SAB 80C166 family of single-chip CMOS
microcontrollers. It combines high CPU performance (up to 8 million instructions per second) with
high peripheral functionality and enhanced IO-capabilities. The C161 derivatives are especially
suited for cost sensitive applications.
Figure 1
Logic Symbol
Ordering Information
Type
Ordering Code
Package
Function
SAB-C161V-L16M Q67121-C1007
P-MQFP-80-1
16-bit microcontroller with
1 KByte RAM
Temperature range 0 to +70 ˚C
SAB-C161K-L16M Q67121-C1060
P-MQFP-80-1
16-bit microcontroller with
1 KByte RAM
Temperature range 0 to +70 ˚C
SAB-C161O-L16M Q67121-C1061
P-MQFP-80-1
16-bit microcontroller with
2 KByte RAM
Temperature range 0 to +70 ˚C
Semiconductor Group
2
1996 Intermediate Version
C161
Figure 2
Pin Configuration Square MQFP-80 Package (top view)
Note: The marked signals are not available on all C161 derivatives. Please refer to the detailed
description below.
Semiconductor Group
3
1996 Intermediate Version
C161
Pin Definitions and Functions
Symbol
Pin
Input
Number Output
Function
XTAL1
2
I
XTAL1:
XTAL2
3
O
P3.2 –
P3.13
5–
16
I/O
I/O
Port 3 is a 12-bit bidirectional I/O port. It is bit-wise programmable
for input or output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state.
The following Port 3 pins also serve for alternate functions:
5
I
P3.2
CAPIN
GPT2 Register CAPREL Capture Input
This function is only available on the C161O.
6
7
8
O
I
I
P3.3
P3.4
P3.5
T3OUT
T3EUD
T4IN
9
10
I
I
11
12
13
14
15
P3.8
P3.9
P3.10
P3.11
P3.12
16
I/O
I/O
O
I/O
O
O
I/O
MRST
MTSR
TxD0
RxD0
BHE
WRH
SCLK
17-20,
23, 24
I/O
I/O
17
...
24
O
...
O
Port 4 is a 6-bit bidirectional I/O port. It is bit-wise programmable
for input or output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state.
In case of an external bus configuration, Port 4 can be used to
output the segment address lines:
P4.0
A16
Least Significant Segment Addr. Line
...
...
...
P4.5
A21
Most Significant Segment Addr. Line
25
O
P4.0 –
P4.5
RD
Semiconductor Group
Input to the oscillator amplifier and input to the internal
clock generator
XTAL2:
Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1, while
leaving XTAL2 unconnected. Minimum and maximum high/low
and rise/fall times specified in the AC Characteristics must be
observed.
GPT1 Timer T3 Toggle Latch Output
GPT1 Timer T3 Ext.Up/Down Ctrl.Input
GPT1 Timer T4 Input for
Count/Gate/Reload/Capture
P3.6
T3IN
GPT1 Timer T3 Count/Gate Input
P3.7
T2IN
GPT1 Timer T2 Input for
Count/Gate/Reload/Capture
These functions are only available on the C161K and the C161O.
P3.13
SSC Master-Rec./Slave-Transmit I/O
SSC Master-Transmit/Slave-Rec. O/I
ASC0 Clock/Data Output (Asyn./Syn.)
ASC0 Data Input (Asyn.) or I/O (Syn.)
Ext. Memory High Byte Enable Signal,
Ext. Memory High Byte Write Strobe
SSC Master Clock Outp./Slave Cl. Inp.
External Memory Read Strobe. RD is activated for every external
instruction or data read access.
4
C161
1996 Intermediate Version
Pin Definitions and Functions (cont’d)
Symbol
Pin
Input
Number Output
Function
WR/
WRL
26
O
External Memory Write Strobe. In WR-mode this pin is activated
for every external data write access. In WRL-mode this pin is
activated for low byte data write accesses on a 16-bit bus, and for
every data write access on an 8-bit bus. See WRCFG in register
SYSCON for mode selection.
ALE
27
O
Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
EA
28
I
External Access Enable pin. A low level at this pin during and after
Reset forces the C161 to begin instruction execution out of
external memory. A high level forces execution out of the internal
ROM. The C161 must have this pin tied to ‘0’.
I/O
PORT0 consists of the two 8-bit bidirectional I/O ports P0L and
P0H. It is bit-wise programmable for input or output via direction
bits. For a pin configured as input, the output driver is put into
high-impedance state.
In case of an external bus configuration, PORT0 serves as the
address (A) and address/data (AD) bus in multiplexed bus modes
and as the data (D) bus in demultiplexed bus modes.
PORT0:
P0L.0 –
P0L.7,
P0H.0 P0H.7
29 –
36
39 –
46
Demultiplexed bus modes:
Data Path Width:
8-bit
16-bit
P0L.0 – P0L.7:
D0 - D7
D0 - D7
P0H.0 – P0H.7:
I/O
D8 - D15
Demux bus is only available on the C161K and the C161O.
Multiplexed bus modes:
Data Path Width:
8-bit
P0L.0 – P0L.7:
AD0 - AD7
P0H.0 – P0H.7:
A8 - A15
PORT1:
P1L.0 –
P1L.7,
P1H.0 P1H.7
47 54
55 62
RSTIN
65
16-bit
AD0 - AD7
AD8 - AD15
I/O
PORT1 consists of the two 8-bit bidirectional I/O ports P1L and
P1H. It is bit-wise programmable for input or output via direction
bits. For a pin configured as input, the output driver is put into
high-impedance state.
The C161K and the C161O use PORT1 as the 16-bit address bus
(A) in demultiplexed bus modes and also after switching from a
demultiplexed bus mode to a multiplexed bus mode.
I
Reset Input with Schmitt-Trigger characteristics. A low level at this
pin for a specified duration while the oscillator is running resets the
C161. An internal pullup resistor permits power-on reset using
only a capacitor connected to VSS.
Semiconductor Group
5
C161
1996 Intermediate Version
Pin Definitions and Functions (cont’d)
Symbol
Pin
Input
Number Output
Function
RSTOUT 66
O
Internal Reset Indication Output. This pin is set to a low level when
the part is executing either a hardware-, a software- or a watchdog
timer reset. RSTOUT remains low until the EINIT (end of
initialization) instruction is executed.
NMI
I
Non-Maskable Interrupt Input. A high to low transition at this pin
causes the CPU to vector to the NMI trap routine.
67
When the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C161 to go into power down
mode. If NMI is high, when PWRDN is executed, the part will
continue to run in normal mode.
Power Down is only available on the C161K and the C161O.
If not used, pin NMI should be pulled high externally.
P6.0 –
P6.3
P2.9 –
P2.15
P5.14 –
P5.15
68 71
I/O
I/O
Port 6 is a 4-bit bidirectional I/O port. It is bit-wise programmable
for input or output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state.
The Port 6 pins also serve for alternate functions:
68
69
70
71
O
O
O
O
P6.0
CS0
Chip Select 0 Output (C161O, C161K)
P6.1
CS1
Chip Select 1 Output (C161O, C161K)
P6.2
CS2
Chip Select 2 Output (C161O)
Chip Select 3 Output (C161O)
P6.3
CS3
The C161V does not provide CS outputs.
72 78
I/O
I/O
72
...
75
I
...
I
Port 2 is a 7-bit bidirectional I/O port. It is bit-wise programmable
for input or output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state.
The following Port 2 pins also serve for alternate functions:
P2.9
EX1IN
Fast External Interrupt 1 Input
...
...
...
P2.12
EX4IN
Fast External Interrupt 4 Input
76
...
78
I
...
I
P2.13
EX5IN
Fast External Interrupt 5 Input
...
...
...
P2.15
EX7IN
Fast External Interrupt 7 Input
These ext. interrupts are only available on the C161O.
79
80
I
I
Port 5 is a 2-bit
characteristics.
I
I
The pins of Port 5 also serve as timer inputs:
P5.14
T4EUD
GPT1 Timer T4 Ext.Up/Down Ctrl.Input
P5.15
T2EUD
GPT1 Timer T2 Ext.Up/Down Ctrl.Input
These functions are only available on the C161K and the C161O.
79
80
Semiconductor Group
6
input-only
port
with
Schmitt-Trigger
1996 Intermediate Version
Pin Definitions and Functions (cont’d)
Symbol
Pin
Input
Number Output
Function
VCC
4, 22,
37, 64
-
Digital Supply Voltage:
+ 5 V during normal operation and idle mode.
≥ 2.5 V during power down mode
VSS
1, 21,
38, 63
-
Digital Ground.
Semiconductor Group
7
C161
C161
1996 Intermediate Version
Device Cross-Reference
The table below describes the differences between the three derivatives described in this data
sheet. This table provides an overview on the capabilities of each derivative for a quick comparison.
Feature
C161V
C161K
C161O
Internal RAM Size (IRAM)
1 KByte
1 KByte
2 KBytes
Chip Select Signals
---
2
4
Bus Modes
MUX
MUX / Demux
MUX / Demux
Power Saving Modes
---
yes
yes
Fast External Interrupts
4
4
7
General Purpose Timer Unit 1 (GPT1)
yes
yes
yes
Input / Output Functionality of GPT1
---
yes
yes
General Purpose Timer Unit 2 (GPT2)
with Capture Input (CAPIN) Functionality
---
---
yes
Semiconductor Group
8
1996 Intermediate Version
C161
Functional Description
The architecture of the C161 combines advantages of both RISC and CISC processors and of
advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an
overview of the different on-chip components and of the advanced, high bandwidth internal bus
structure of the C161.
Note: All time specifications refer to a CPU clock of 16 MHz
(see definition in the AC Characteristics section).
Figure 3
Block Diagram
Semiconductor Group
9
C161
1996 Intermediate Version
Memory Organization
The memory space of the C161 is configured in a Von Neumann architecture which means that
code memory, data memory, registers and I/O ports are organized within the same linear address
space which includes 4 MBytes. The entire memory space can be accessed bytewise or wordwise.
Particular portions of the on-chip memory have additionally been made directly bit addressable.
The C161 is prepared to incorporate on-chip mask-programmable ROM for code or constant data.
Currently no ROM is integrated.
On-chip RAM (2 KBytes in the C161O, 1 KByte in the C161V and the C161K) is provided as a
storage for user defined variables, for the system stack, general purpose register banks and even
for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL7, RH7) so-called General Purpose Registers (GPRs).
1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register
areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling
and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for
future members of the C161 family.
In order to meet the needs of designs where more memory is required than is provided on chip, up
to 4 MBytes of external RAM and/or ROM can be connected to the microcontroller.
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus Controller
(EBC). It can be programmed either to Single Chip Mode when no external memory is required, or
to one of four different external memory access modes, which are as follows:
– 16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed
(not in the C161V)
– 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed
– 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed
– 16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed
(not in the C161V)
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on
PORT0. In the multiplexed bus modes both addresses and data use PORT0 for input/output.
Note: The C161V only provides multiplexed bus modes.
Important timing characteristics of the external bus interface (Memory Cycle Time, Memory TriState Time, Length of ALE and Read Write Delay) have been made programmable to allow the user
the adaption of a wide range of different types of memories. In addition, different address ranges
may be accessed with different bus characteristics. External CS signals (0, 2, 4, depending on the
device) can be generated in order to save external glue logic.
For applications which require less than 4 MBytes of external memory space, this address space
can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no
address lines at all. It outputs all 6 address lines, if an address space of 4 MBytes is used.
Semiconductor Group
10
1996 Intermediate Version
C161
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C161’s instructions can be executed in just one
machine cycle which requires 125 ns at 16-MHz CPU clock. For example, shift and rotate
instructions are always processed during one machine cycle independent of the number of bits to
be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast
as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in
10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution
time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 4
CPU Block Diagram
Semiconductor Group
11
1996 Intermediate Version
C161
The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are
physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the
base address of the active register bank to be accessed by the CPU at a time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter passing,
a register bank may overlap others.
A system stack is provided as a storage for temporary data. The system stack is allocated in the onchip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate
SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack
access for the detection of a stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently be utilized
by a programmer via the highly efficient C161 instruction set which includes the following instruction
classes:
–
–
–
–
–
–
–
–
–
–
–
–
Arithmetic Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words.
A variety of direct, indirect or immediate addressing modes are provided to specify the required
operands.
Semiconductor Group
12
1996 Intermediate Version
C161
Interrupt System
With an interrupt response time within a range from just 315 ns to 750 ns (in case of internal
program execution), the C161 is capable of reacting very fast to the occurence of non-deterministic
events.
The architecture of the C161 supports several mechanisms for fast and flexible response to service
requests that can be generated from various sources internal or external to the microcontroller. Any
of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by
the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is suspended and
a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service. A PEC service implies a single byte or word data transfer between
any two memory locations with an additional increment of either the PEC source or the destination
pointer. An individual PEC transfer counter is implicity decremented for each PEC service except
when performing in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data. The C161
has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable flag and an
interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each
source can be programmed to one of sixteen interrupt priority levels. Once having been accepted
by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For
the standard interrupt processing, each of the possible interrupt sources has a dedicated vector
location.
Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling
edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
The following table shows all of the possible C161 interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:
Semiconductor Group
13
C161
1996 Intermediate Version
Source of Interrupt or
PEC Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
External Interrupt 1
CC9IR
CC9IE
CC9INT
00’0064H
19H
External Interrupt 2
CC10IR
CC10IE
CC10INT
00’0068H
1AH
External Interrupt 3
CC11IR
CC11IE
CC11INT
00’006CH
1BH
External Interrupt 4
CC12IR
CC12IE
CC12INT
00’0070H
1CH
External Interrupt 5
CC13IR
CC13IE
CC13INT
00’0074H
1DH
External Interrupt 6
CC14IR
CC14IE
CC14INT
00’0078H
1EH
External Interrupt 7
CC15IR
CC15IE
CC15INT
00’007CH
1FH
GPT1 Timer 2
T2IR
T2IE
T2INT
00’0088H
22H
GPT1 Timer 3
T3IR
T3IE
T3INT
00’008CH
23H
GPT1 Timer 4
T4IR
T4IE
T4INT
00’0090H
24H
GPT2 Timer 5
T5IR
T5IE
T5INT
00’0094H
25H
GPT2 Timer 6
T6IR
T6IE
T6INT
00’0098H
26H
GPT2 CAPREL Register
CRIR
CRIE
CRINT
00’009CH
27H
ASC0 Transmit
S0TIR
S0TIE
S0TINT
00’00A8H
2AH
ASC0 Transmit Buffer
S0TBIR
S0TBIE
S0TBINT
00’011CH
47H
ASC0 Receive
S0RIR
S0RIE
S0RINT
00’00ACH
2BH
ASC0 Error
S0EIR
S0EIE
S0EINT
00’00B0H
2CH
SSC Transmit
SCTIR
SCTIE
SCTINT
00’00B4H
2DH
SSC Receive
SCRIR
SCRIE
SCRINT
00’00B8H
2EH
SSC Error
SCEIR
SCEIE
SCEINT
00’00BCH
2FH
Note: The shaded interrupt nodes are only available in the C161O,
not in the C161V and the C161K.
Semiconductor Group
14
C161
1996 Intermediate Version
The C161 also provides an excellent mechanism to identify and to process exceptions or error
conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate
non-maskable system reaction which is similar to a standard interrupt service (branching to a
dedicated vector table location). The occurence of a hardware trap is additionally signified by an
individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in
progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap
services can normally not be interrupted by standard or PEC interrupts.
The following table shows all of the possible exceptions or error conditions that can arise during runtime:
Exception Condition
Trap
Flag
Trap
Vector
Vector
Location
Trap
Number
Trap
Priority
RESET
RESET
RESET
00’0000H
00’0000H
00’0000H
00H
00H
00H
III
III
III
NMI
STKOF
STKUF
NMITRAP 00’0008H
STOTRAP 00’0010H
STUTRAP 00’0018H
02H
04H
06H
II
II
II
UNDOPC
PRTFLT
BTRAP
BTRAP
00’0028H
00’0028H
0AH
0AH
I
I
ILLOPA
BTRAP
00’0028H
0AH
I
ILLINA
ILLBUS
BTRAP
BTRAP
00’0028H
00’0028H
0AH
0AH
I
I
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Class B Hardware Traps:
Undefined Opcode
Protected Instruction
Fault
Illegal Word Operand
Access
Illegal Instruction Access
Illegal External Bus
Access
Reserved
[2CH – 3CH] [0BH – 0FH]
Software Traps
TRAP Instruction
Any
[00’0000H –
00’01FCH]
in steps
of 4H
Semiconductor Group
15
Any
[00H – 7FH]
Current
CPU
Priority
1996 Intermediate Version
C161
General Purpose Timer (GPT) Units
The GPT units represent a very flexible multifunctional timer/counter structure which may be used
for many different time related tasks such as event timing and counting, pulse width and duty cycle
measurements, pulse generation, or pulse multiplication.
Two separate modules, GPT1 and GPT2, are available (GPT2 on C161O only). Each timer in each
module may operate independently in a number of different modes, or may be concatenated with
another timer of the same module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three
basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the
input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while
Counter Mode allows a timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of
a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has
one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the
timers in module GPT1 is 500 ns (@ 16-MHz CPU clock).
The count direction (up/down) for each timer is programmable by software or may additionally be
altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking.
Figure 5
Block Diagram of GPT1
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/
underflow. The state of this latch may be output on a port pin (T3OUT) e.g. for time out monitoring
of external hardware components, or may be used internally to clock timers T2 and T4 for
measuring long time periods with high resolution.
Semiconductor Group
16
1996 Intermediate Version
C161
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture
registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The
contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins
(TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or
by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to
alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM
signal, this signal can be constantly generated without software intervention.
Note: The C161V has no external connection for GPT1, ie. the related functions are not available.
Figure 6
Block Diagram of GPT2
With its maximum resolution of 250 ns (@ 16 MHz), the GPT2 module provides precise event
control and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via
a programmable prescaler. The count direction (up/down) for each timer is programmable by
software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5. The overflows/underflows of timer T6 can
cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer
T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may
optionally be cleared after the capture procedure. This allows absolute time differences to be
measured or pulse multiplication to be performed without software overhead.
Note: The GPT2 module is only available on the C161O.
Semiconductor Group
17
1996 Intermediate Version
C161
Parallel Ports
The C161 provides up to 63 I/O lines which are organized into six input/output ports and one input
port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise)
programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports
which are switched to high impedance state when configured as inputs. The output drivers of three
I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control
registers. During the internal reset, all port pins are configured as inputs.
All port lines have programmable alternate input or output functions associated with them. PORT0
and PORT1 may be used as address and data lines when accessing external memory, while Port 4
outputs the additional segment address bits A21/19/17...A16 in systems where segmentation is
enabled to access more than 64 KBytes of memory. Port 6 provides optional chip select signals.
Port 3 includes alternate functions of timers, serial interfaces and the optional bus control signal
BHE. Port 5 is used for timer control signals. All port lines that are not used for these alternate
functions may be used as general purpose I/O lines.
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to
prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time
interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up
procedure is always monitored. The software has to be designed to service the Watchdog Timer
before it overflows. If, due to hardware or software related failures, the software fails to do so, the
Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low
in order to allow external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128.
The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in
WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced
by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals
between 32 µs and 524 ms can be monitored (@ 16 MHz). The default Watchdog Timer interval
after reset is 8.19 ms (@ 16 MHz).
Semiconductor Group
18
1996 Intermediate Version
C161
Serial Channels
Serial communication with other microcontrollers, processors, terminals or external peripheral
components is provided by two serial interfaces with different functionality, an Asynchronous/
Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).
The ASC0 is upward compatible with the serial ports of the Siemens 8-bit microcontroller families
and supports full-duplex asynchronous communication at up to 500 KBaud and half-duplex
synchronous communication at up to 2 MBaud @ 16 MHz CPU clock.
A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning.
For transmission, reception and error handling 4 separate interrupt vectors are provided. In
asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and
terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish
address from data bytes has been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock
which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is
available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. A parity bit can automatically be generated on transmission or be
checked on reception. Framing error detection allows to recognize data frames with missing stop
bits. An overrun error will be generated, if the last character received has not been read out of the
receive buffer register at the time the reception of a new character is complete.
The SSC supports full-duplex synchronous communication at up to 4 Mbaud @ 16 MHz CPU clock.
It may be configured so it interfaces with serially linked peripheral components. A dedicated baud
rate generator allows to set up all standard baud rates without oscillator tuning. For transmission,
reception and error handling 3 separate interrupt vectors are provided.
The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock which
can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can
start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock
edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. Transmit and receive error supervise the correct handling of the data
buffer. Phase and baudrate error detect incorrect serial data.
Semiconductor Group
19
1996 Intermediate Version
C161
Instruction Set Summary
The table below lists the instructions of the C161 in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation of the
instructions, parameters for conditional execution of instructions, and the opcodes for each
instruction can be found in the “C16x Family Instruction Set Manual”.
This document also provides a detailled description of each instruction.
Instruction Set Summary
Mnemonic
Description
Bytes
ADD(B)
Add word (byte) operands
2/4
ADDC(B)
Add word (byte) operands with Carry
2/4
SUB(B)
Subtract word (byte) operands
2/4
SUBC(B)
Subtract word (byte) operands with Carry
2/4
MUL(U)
(Un)Signed multiply direct GPR by direct GPR (16-16-bit)
2
DIV(U)
(Un)Signed divide register MDL by direct GPR (16-/16-bit)
2
DIVL(U)
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)
2
CPL(B)
Complement direct word (byte) GPR
2
NEG(B)
Negate direct word (byte) GPR
2
AND(B)
Bitwise AND, (word/byte operands)
2/4
OR(B)
Bitwise OR, (word/byte operands)
2/4
XOR(B)
Bitwise XOR, (word/byte operands)
2/4
BCLR
Clear direct bit
2
BSET
Set direct bit
2
BMOV(N)
Move (negated) direct bit to direct bit
4
BAND, BOR, BXOR
AND/OR/XOR direct bit with direct bit
4
BCMP
Compare direct bit to direct bit
4
BFLDH/L
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
4
CMP(B)
Compare word (byte) operands
2/4
CMPD1/2
Compare word data to GPR and decrement GPR by 1/2
2/4
CMPI1/2
Compare word data to GPR and increment GPR by 1/2
2/4
PRIOR
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
2
SHL / SHR
Shift left/right direct word GPR
2
ROL / ROR
Rotate left/right direct word GPR
2
ASHR
Arithmetic (sign bit) shift right direct word GPR
2
Semiconductor Group
20
1996 Intermediate Version
C161
Instruction Set Summary (cont’d)
Mnemonic
Description
Bytes
MOV(B)
Move word (byte) data
2/4
MOVBS
Move byte operand to word operand with sign extension
2/4
MOVBZ
Move byte operand to word operand. with zero extension
2/4
JMPA, JMPI, JMPR
Jump absolute/indirect/relative if condition is met
4
JMPS
Jump absolute to a code segment
4
J(N)B
Jump relative if direct bit is (not) set
4
JBC
Jump relative and clear bit if direct bit is set
4
JNBS
Jump relative and set bit if direct bit is not set
4
CALLA, CALLI, CALLR
Call absolute/indirect/relative subroutine if condition is met
4
CALLS
Call absolute subroutine in any code segment
4
PCALL
Push direct word register onto system stack and call
absolute subroutine
4
TRAP
Call interrupt service routine via immediate trap number
2
PUSH, POP
Push/pop direct word register onto/from system stack
2
SCXT
Push direct word register onto system stack und update
register with word operand
4
RET
Return from intra-segment subroutine
2
RETS
Return from inter-segment subroutine
2
RETP
Return from intra-segment subroutine and pop direct
word register from system stack
2
RETI
Return from interrupt service subroutine
2
SRST
Software Reset
4
IDLE
Enter Idle Mode
4
PWRDN
Enter Power Down Mode
(supposes NMI-pin being low)
4
SRVWDT
Service Watchdog Timer
4
DISWDT
Disable Watchdog Timer
4
EINIT
Signify End-of-Initialization on RSTOUT-pin
4
ATOMIC
Begin ATOMIC sequence
2
EXTR
Begin EXTended Register sequence
2
EXTP(R)
Begin EXTended Page (and Register) sequence
2/4
EXTS(R)
Begin EXTended Segment (and Register) sequence
2/4
NOP
Null operation
2
Semiconductor Group
21
1996 Intermediate Version
C161
Special Function Registers Overview
The following table lists all SFRs which are implemented in the C161 in alphabetical order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended
SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”.
An SFR can be specified via its individual mnemonic name. Depending on the selected addressing
mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its
short 8-bit address (without using the Data Page Pointers).
Special Function Registers Overview
Name
Physical
Address
8-Bit
Description
Address
Reset
Value
ADDRSEL1
FE18H
0CH
Address Select Register 1
0000H
ADDRSEL2
FE1AH
0DH
Address Select Register 2
0000H
ADDRSEL3
FE1CH
0EH
Address Select Register 3
0000H
ADDRSEL4
FE1EH
0FH
Address Select Register 4
0000H
BUSCON0 b FF0CH
86H
Bus Configuration Register 0
0XX0H
BUSCON1 b FF14H
8AH
Bus Configuration Register 1
0000H
BUSCON2 b FF16H
8BH
Bus Configuration Register 2
0000H
BUSCON3 b FF18H
8CH
Bus Configuration Register 3
0000H
BUSCON4 b FF1AH
8DH
Bus Configuration Register 4
0000H
FE4AH
25H
GPT2 Capture/Reload Register
0000H
CC9IC
b FF8AH
C5H
EX1IN Interrupt Control Register
0000H
CC10IC
b FF8CH
C6H
EX2IN Interrupt Control Register
0000H
CC11IC
b FF8EH
C7H
EX3IN Interrupt Control Register
0000H
CC12IC
b FF90H
C8H
EX4IN Interrupt Control Register
0000H
CC13IC
b FF92H
C9H
EX5IN Interrupt Control Register
0000H
CC14IC
b FF94H
CAH
EX6IN Interrupt Control Register
0000H
CC15IC
b FF96H
CBH
EX7IN Interrupt Control Register
0000H
FE10H
08H
CPU Context Pointer Register
FC00H
b FF6AH
B5H
GPT2 CAPREL Interrupt Control Register
0000H
FE08H
04H
CPU Code Segment Pointer Register (read only)
0000H
CAPREL
CP
CRIC
CSP
DP0L
b F100H E 80H
P0L Direction Control Register
00H
DP0H
b F102H E 81H
P0H Direction Control Register
00H
Semiconductor Group
22
1996 Intermediate Version
C161
Special Function Registers Overview (cont’d)
Name
Physical
Address
8-Bit
Description
Address
Reset
Value
DP1L
b F104H E 82H
P1L Direction Control Register
00H
DP1H
b F106H E 83H
P1H Direction Control Register
00H
DP2
b FFC2H
E1H
Port 2 Direction Control Register
0000H
DP3
b FFC6H
E3H
Port 3 Direction Control Register
0000H
DP4
b FFCAH
E5H
Port 4 Direction Control Register
00H
DP6
b FFCEH
E7H
Port 6 Direction Control Register
00H
DPP0
FE00H
00H
CPU Data Page Pointer 0 Register (10 bits)
0000H
DPP1
FE02H
01H
CPU Data Page Pointer 1 Register (10 bits)
0001H
DPP2
FE04H
02H
CPU Data Page Pointer 2 Register (10 bits)
0002H
DPP3
FE06H
03H
CPU Data Page Pointer 3 Register (10 bits)
0003H
EXICON
b F1C0H E E0H
External Interrupt Control Register
0000H
MDC
b FF0EH
87H
CPU Multiply Divide Control Register
0000H
MDH
FE0CH
06H
CPU Multiply Divide Register – High Word
0000H
MDL
FE0EH
07H
CPU Multiply Divide Register – Low Word
0000H
ODP2
b F1C2H E E1H
Port 2 Open Drain Control Register
0000H
ODP3
b F1C6H E E3H
Port 3 Open Drain Control Register
0000H
ODP6
b F1CEH E E7H
Port 6 Open Drain Control Register
00H
FF1EH
8FH
Constant Value 1’s Register (read only)
FFFFH
P0L
b FF00H
80H
Port 0 Low Register (Lower half of PORT0)
00H
P0H
b FF02H
81H
Port 0 High Register (Upper half of PORT0)
00H
P1L
b FF04H
82H
Port 1 Low Register (Lower half of PORT1)
00H
P1H
b FF06H
83H
Port 1 High Register (Upper half of PORT1)
00H
P2
b FFC0H
E0H
Port 2 Register
0000H
P3
b FFC4H
E2H
Port 3 Register
0000H
P4
b FFC8H
E4H
Port 4 Register (8 bits)
00H
P5
b FFA2H
D1H
Port 5 Register (read only)
XXXXH
P6
b FFCCH
E6H
Port 6 Register (8 bits)
00H
PECC0
FEC0H
60H
PEC Channel 0 Control Register
0000H
PECC1
FEC2H
61H
PEC Channel 1 Control Register
0000H
ONES
Semiconductor Group
23
1996 Intermediate Version
C161
Special Function Registers Overview (cont’d)
Name
Physical
Address
8-Bit
Description
Address
Reset
Value
PECC2
FEC4H
62H
PEC Channel 2 Control Register
0000H
PECC3
FEC6H
63H
PEC Channel 3 Control Register
0000H
PECC4
FEC8H
64H
PEC Channel 4 Control Register
0000H
PECC5
FECAH
65H
PEC Channel 5 Control Register
0000H
PECC6
FECCH
66H
PEC Channel 6 Control Register
0000H
PECC7
FECEH
67H
PEC Channel 7 Control Register
0000H
88H
CPU Program Status Word
0000H
PSW
b FF10H
RP0H
b F108H E 84H
System Startup Configuration Register (Rd. only) XXH
FEB4H
5AH
Serial Channel 0 Baud Rate Generator Reload
Register
0000H
S0CON
b FFB0H
D8H
Serial Channel 0 Control Register
0000H
S0EIC
b FF70H
B8H
Serial Channel 0 Error Interrupt Control Register
0000H
FEB2H
59H
Serial Channel 0 Receive Buffer Register
(read only)
XXH
S0RIC
b FF6EH
B7H
Serial Channel 0 Receive Interrupt Control
Register
0000H
S0TBIC
b F19CH E CEH
S0BG
S0RBUF
Serial Channel 0 Transmit Buffer Interrupt Control 0000H
Register
FEB0H
58H
Serial Channel 0 Transmit Buffer Register
(write only)
00H
b FF6CH
B6H
Serial Channel 0 Transmit Interrupt Control
Register
0000H
SP
FE12H
09H
CPU System Stack Pointer Register
FC00H
SSCBR
F0B4H E 5AH
SSC Baudrate Register
0000H
S0TBUF
S0TIC
SSCCON
b FFB2H
D9H
SSC Control Register
0000H
SSCEIC
b FF76H
BBH
SSC Error Interrupt Control Register
0000H
SSC Receive Buffer (read only)
XXXXH
SSC Receive Interrupt Control Register
0000H
SSC Transmit Buffer (write only)
0000H
SSCRB
SSCRIC
SSCTB
F0B2H E 59H
b FF74H
BAH
F0B0H E 58H
SSCTIC
b FF72H
B9H
SSC Transmit Interrupt Control Register
0000H
STKOV
FE14H
0AH
CPU Stack Overflow Pointer Register
FA00H
Semiconductor Group
24
1996 Intermediate Version
C161
Special Function Registers Overview (cont’d)
Name
Physical
Address
8-Bit
Description
Address
Reset
Value
STKUN
FE16H
0BH
CPU Stack Underflow Pointer Register
FC00H
b FF12H
89H
CPU System Configuration Register
0xx0H*)
FE40H
20H
GPT1 Timer 2 Register
0000H
T2CON
b FF40H
A0H
GPT1 Timer 2 Control Register
0000H
T2IC
b FF60H
B0H
GPT1 Timer 2 Interrupt Control Register
0000H
FE42H
21H
GPT1 Timer 3 Register
0000H
T3CON
b FF42H
A1H
GPT1 Timer 3 Control Register
0000H
T3IC
b FF62H
B1H
GPT1 Timer 3 Interrupt Control Register
0000H
FE44H
22H
GPT1 Timer 4 Register
0000H
T4CON
b FF44H
A2H
GPT1 Timer 4 Control Register
0000H
T4IC
b FF64H
B2H
GPT1 Timer 4 Interrupt Control Register
0000H
FE46H
23H
GPT2 Timer 5 Register
0000H
T5CON
b FF46H
A3H
GPT2 Timer 5 Control Register
0000H
T5IC
b FF66H
B3H
GPT2 Timer 5 Interrupt Control Register
0000H
FE48H
24H
GPT2 Timer 6 Register
0000H
T6CON
b FF48H
A4H
GPT2 Timer 6 Control Register
0000H
T6IC
b FF68H
B4H
GPT2 Timer 6 Interrupt Control Register
0000H
TFR
b FFACH
D6H
Trap Flag Register
0000H
WDT
FEAEH
57H
Watchdog Timer Register (read only)
0000H
WDTCON
FFAEH
D7H
Watchdog Timer Control Register
0000H
b FF1CH
8EH
Constant Value 0’s Register (read only)
0000H
SYSCON
T2
T3
T4
T5
T6
ZEROS
*) The system configuration is selected during reset.
Note: The shaded registers are only available in the C161O, not in the C161V and the C161K.
Semiconductor Group
25
C161
1996 Intermediate Version
Absolute Maximum Ratings
Ambient temperature under bias (TA):
SAB-C161V-L16M, SAB-C161K-L16M, SAB-C161O-L16M............................................ 0 to +70 ˚C
Storage temperature (TST) ........................................................................................ – 65 to +150 ˚C
Voltage on VCC pins with respect to ground (VSS) ....................................................... –0.5 to +6.5 V
Voltage on any pin with respect to ground (VSS) ...................................................–0.5 to VCC +0.5 V
Input current on any pin during overload condition.................................................... –10 to +10 mA
Absolute sum of all input currents during overload condition ..............................................|100 mA|
Power dissipation..................................................................................................................... 1.5 W
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (VIN>VCC or VIN<VSS) the
voltage on pins with respect to ground (VSS) must not exceed the values defined by the
Absolute Maximum Ratings.
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the C161 and partly its
demands on the system. To aid in interpreting the parameters right, when evaluating them for a
design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the C161 will provide signals with the respective timing characteristics.
SR (System Requirement):
The external system must provide signals with the respective timing characteristics to the C161.
DC Characteristics
VCC = 5 V ± 10 %;
VSS = 0 V;
fCPU = 16 MHz;
Reset active
TA = 0 to +70 ˚C
for SAB-C161V-L16M, SAB-C161K-L16M, SAB-C161O-L16M
Parameter
Symbol
Limit Values
min.
Unit
Test Condition
max.
Input low voltage
VIL
SR – 0.5
0.2 VCC
– 0.1
V
–
Input high voltage
(all except RSTIN and XTAL1)
VIH
SR 0.2 VCC
+ 0.9
VCC + 0.5
V
–
Input high voltage RSTIN
VIH1 SR 0.6 VCC
VCC + 0.5
V
–
Input high voltage XTAL1
VIH2 SR 0.7 VCC
VCC + 0.5
V
–
Semiconductor Group
26
C161
1996 Intermediate Version
Parameter
Symbol
Limit Values
min.
Unit
Test Condition
max.
Output low voltage
VOL CC –
(PORT0, PORT1, Port 4, ALE, RD,
WR, BHE, CLKOUT, RSTOUT)
0.45
V
IOL = 2.4 mA
VOL1 CC –
0.45
V
IOL1 = 1.6 mA
–
V
IOH = – 500 µA
IOH = – 2.4 mA
–
V
V
IOH = – 250 µA
IOH = – 1.6 mA
Output low voltage
(all other outputs)
VOH CC 0.9 VCC
Output high voltage
2.4
(PORT0, PORT1, Port 4, ALE, RD,
WR, BHE, CLKOUT, RSTOUT)
1)
Output high voltage
(all other outputs)
VOH1 CC 0.9 VCC
2.4
Input leakage current (Port 5)
IOZ1 CC –
±200
nA
0 V < VIN < VCC
Input leakage current (all other)
IOZ2 CC –
±500
nA
0 V < VIN < VCC
RSTIN pullup resistor
RRST CC 50
150
kΩ
–
IRWH
2)
–
-40
µA
VOUT = 2.4 V
IRWL
3)
-500
–
µA
VOUT = VOLmax
IALEL
2)
–
40
µA
VOUT = VOLmax
IALEH
3)
500
–
µA
VOUT = 2.4 V
Read/Write inactive current
Read/Write active current
ALE inactive current
ALE active current
4)
4)
4)
4)
Port 6 inactive current
Port 6 active current
4)
4)
PORT0 configuration current
4)
XTAL1 input current
5)
IP6H
2)
–
-40
µA
VOUT = 2.4 V
IP6L
3)
-500
–
µA
VOUT = VOL1max
IP0H
2)
–
-10
µA
VIN = VIHmin
IP0L
3)
-100
–
µA
VIN = VILmax
±20
µA
0 V < VIN < VCC
IIL
CC –
Pin capacitance
(digital inputs/outputs)
CIO CC –
10
pF
f = 1 MHz
TA = 25 ˚C
Power supply current
ICC
–
10 +
4 * fCPU
mA
RSTIN = VIL2
fCPU in [MHz] 6)
Idle mode supply current
IID
–
2+
1.2 * fCPU
mA
RSTIN = VIH1
fCPU in [MHz] 6)
Power-down mode supply current
IPD
–
50
µA
VCC = 5.5 V 7)
Semiconductor Group
27
1996 Intermediate Version
C161
Notes
1)
This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
2)
The maximum current may be drawn while the respective signal line remains inactive.
3)
The minimum current must be drawn in order to drive the respective signal line active.
4)
This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if
they are used for CS output and the open drain function is not enabled.
5)
Not 100% tested, guaranteed by design characterization.
6)
The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.
These parameters are tested at VCCmax and 16 MHz CPU clock with all outputs disconnected and all inputs at
VIL or VIH.
7)
This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at VCC – 0.1 V to VCC, VREF = 0 V, all outputs (including pins configured as outputs) disconnected.
Figure 7
Supply/Idle Current as a Function of Operating Frequency
Semiconductor Group
28
1996 Intermediate Version
C161
Testing Waveforms
AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’.
Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.
Figure 8
Input Output Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load
voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs
(IOH/IOL = 20 mA).
Figure 9
Float Waveforms
Semiconductor Group
29
C161
1996 Intermediate Version
AC Characteristics
External Clock Drive XTAL1
VCC = 5 V ± 10 %;
VSS = 0 V
TA = 0 to +70 ˚C
for SAB-C161V-L16M, SAB-C161K-L16M, SAB-C161O-L16M
Parameter
Symbol
Max. CPU Clock
= 16 MHz
min.
Variable CPU Clock
1/2TCL = 1 to 16 MHz
max.
min.
max.
Unit
Oscillator period
TCL SR 31
31
31
500
ns
High time
t1
SR 8
–
8
–
ns
Low time
t2
SR 8
–
8
–
ns
Rise time
t3
SR –
6
–
6
ns
Fall time
t4
SR –
6
–
6
ns
Figure 10
External Clock Drive XTAL1
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes, how these variables are to be computed.
Description
Symbol Values
ALE Extension
tA
TCL * <ALECTL>
Memory Cycle Time Waitstates
tC
2TCL * (15 - <MCTC>)
Memory Tristate Time
tF
2TCL * (1 - <MTTC>)
Semiconductor Group
30
C161
1996 Intermediate Version
AC Characteristics (cont’d)
Multiplexed Bus
VCC = 5 V ± 10 %;
VSS = 0 V
TA = 0 to +70 ˚C
for SAB-C161V-L16M, SAB-C161K-L16M, SAB-C161O-L16M
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
CL (for Port 6, CS) = 100 pF
ALE cycle time = 6 TCL + 2tA + tC + tF (186 ns at 16-MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 16 MHz
min.
Variable CPU Clock
1/2TCL = 1 to 16 MHz
max.
min.
Unit
max.
CC 21 + tA
–
TCL - 10 + tA –
ns
Address setup to ALE
t5
t6
CC 16 + tA
–
TCL - 15 + tA –
ns
Address hold after ALE
t7
CC 21 + tA
–
TCL - 10 + tA –
ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC 21 + tA
–
TCL - 10 + tA –
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC -10 + tA
–
-10 + tA
–
ns
Address float after RD,
WR (with RW-delay)
t10
CC –
5
–
5
ns
Address float after RD,
WR (no RW-delay)
t11
CC –
36
–
TCL + 5
ns
RD, WR low time
(with RW-delay)
t12
CC 53 + tC
–
2TCL - 10
+ tC
–
ns
RD, WR low time
(no RW-delay)
t13
CC 84 + tC
–
3TCL - 10
+ tC
–
ns
RD to valid data in
(with RW-delay)
t14
SR –
43 + tC
–
2TCL - 20
+ tC
ns
RD to valid data in
(no RW-delay)
t15
SR –
74 + tC
–
3TCL - 20
+ tC
ns
ALE low to valid data in
t16
SR –
74
+ tA + tC
–
3TCL - 20
+ tA + tC
ns
Address to valid data in
t17
SR –
95
+ 2tA + tC
–
4TCL - 30
+ 2tA + tC
ns
Data hold after RD
rising edge
t18
SR 0
–
0
–
ns
Data float after RD
t19
SR –
48 + tF
–
2TCL - 15
+ tF
ns
Data valid to WR
t22
SR 48 + tC
–
2TCL - 15
+ tC
–
ns
ALE high time
Semiconductor Group
31
C161
1996 Intermediate Version
Parameter
Symbol
Max. CPU Clock
= 16 MHz
min.
Variable CPU Clock
1/2TCL = 1 to 16 MHz
max.
min.
max.
Unit
Data hold after WR
t23
CC 48 + tF
–
2TCL - 15
+ tF
–
ns
ALE rising edge after RD,
WR
t25
CC 48 + tF
–
2TCL - 15
+ tF
–
ns
Address hold after RD,
WR
t27
CC 48 + tF
–
2TCL - 15
+ tF
–
ns
ALE falling edge to CS
t38
CC -5 - tA
10 - tA
-5 - tA
10 - tA
ns
CS low to Valid Data In
t39
SR –
74
+ tC + 2tA
–
3TCL - 20
+ tC + 2tA
ns
CS hold after RD, WR
t40
CC 79 + tF
–
3TCL - 15
+ tF
–
ns
ALE fall. edge to RdCS,
WrCS (with RW delay)
t42
CC 26 + tA
–
TCL - 5
+ tA
–
ns
ALE fall. edge to RdCS,
WrCS (no RW delay)
t43
CC -5 + tA
–
-5
+ tA
–
ns
Address float after RdCS,
WrCS (with RW delay)
t44
CC –
0
–
0
ns
Address float after RdCS,
WrCS (no RW delay)
t45
CC –
31
–
TCL
ns
RdCS to Valid Data In
(with RW delay)
t46
SR –
38 + tC
–
2TCL - 25
+ tC
ns
RdCS to Valid Data In
(no RW delay)
t47
SR –
69 + tC
–
3TCL - 25
+ tC
ns
RdCS, WrCS Low Time
(with RW delay)
t48
CC 53 + tC
–
2TCL - 10
+ tC
–
ns
RdCS, WrCS Low Time
(no RW delay)
t49
CC 84 + tC
–
3TCL - 10
+ tC
–
ns
Data valid to WrCS
t50
CC 48 + tC
–
2TCL - 15
+ tC
–
ns
Data hold after RdCS
t51
SR 0
–
0
–
ns
Data float after RdCS
t52
SR –
43 + tF
–
2TCL - 20
+ tF
ns
Address hold after
RdCS, WrCS
t54
CC 43 + tF
–
2TCL - 20
+ tF
–
ns
Data hold after WrCS
t56
CC 43 + tF
–
2TCL - 20
+ tF
–
ns
Semiconductor Group
32
1996 Intermediate Version
Figure 11-1
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE
Semiconductor Group
33
C161
1996 Intermediate Version
Figure 11-2
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE
Semiconductor Group
34
C161
1996 Intermediate Version
Figure 11-3
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE
Semiconductor Group
35
C161
1996 Intermediate Version
Figure 11-4
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE
Semiconductor Group
36
C161
C161
1996 Intermediate Version
AC Characteristics (cont’d)
Demultiplexed Bus
VCC = 5 V ± 10 %;
VSS = 0 V
TA = 0 to +70 ˚C
for SAB-C161K-L16M, SAB-C161O-L16M
(SAB-C161V-L16M does not provide the demultiplexed bus modes)
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
CL (for Port 6, CS) = 100 pF
ALE cycle time = 4 TCL + 2tA + tC + tF (125 ns at 16-MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 16 MHz
min.
Variable CPU Clock
1/2TCL = 1 to 16 MHz
max.
min.
Unit
max.
t5
t6
CC 21 + tA
–
TCL - 10 + tA –
ns
CC 16 + tA
–
TCL - 15 + tA –
ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC 21 + tA
–
TCL - 10
+ tA
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC -10 + tA
–
-10
+ tA
–
ns
RD, WR low time
(with RW-delay)
t12
CC 53 + tC
–
2TCL - 10
+ tC
–
ns
RD, WR low time
(no RW-delay)
t13
CC 84 + tC
–
3TCL - 10
+ tC
–
ns
RD to valid data in
(with RW-delay)
t14
SR –
43 + tC
–
2TCL - 20
+ tC
ns
RD to valid data in
(no RW-delay)
t15
SR –
74 + tC
–
3TCL - 20
+ tC
ns
ALE low to valid data in
t16
SR –
74
+ tA + tC
–
3TCL - 20
+ tA + tC
ns
Address to valid data in
t17
SR –
95
+ 2tA + tC
–
4TCL - 30
+ 2tA + tC
ns
Data hold after RD
rising edge
t18
SR 0
–
0
–
ns
Data float after RD rising
edge (with RW-delay)
t20
SR –
48 + tF
–
2TCL - 15
+ tF
ns
Data float after RD rising
edge (no RW-delay)
t21
SR –
21 + tF
–
TCL - 10
+ tF
ns
Data valid to WR
t22
CC 48 + tC
–
2TCL - 15
+ tC
–
ns
Data hold after WR
t24
CC 21 + tF
–
TCL - 10 + tF –
ns
ALE rising edge after RD,
WR
t26
CC -10 + tF
–
-10
+ tF
ns
ALE high time
Address setup to ALE
Semiconductor Group
37
–
C161
1996 Intermediate Version
Parameter
Symbol
Max. CPU Clock
= 16 MHz
min.
Variable CPU Clock
1/2TCL = 1 to 16 MHz
max.
min.
max.
Unit
Address hold after RD,
WR
t28
CC 0 + tF
–
0
+ tF
–
ns
ALE falling edge to CS
t38
CC -5 - tA
10 - tA
-5 - tA
10 - tA
ns
CS low to Valid Data In
t39
SR –
74
+ tC + 2tA
–
3TCL - 20
+ tC + 2tA
ns
CS hold after RD, WR
t41
CC 16 + tF
–
TCL - 15
+ tF
–
ns
ALE falling edge to RdCS,
WrCS (with RW-delay)
t42
CC 26 + tA
–
TCL - 5
+ tA
–
ns
ALE falling edge to RdCS,
WrCS (no RW-delay)
t43
CC -5 + tA
–
-5
+ tA
–
ns
RdCS to Valid Data In
(with RW-delay)
t46
SR –
38 + tC
–
2TCL - 25
+ tC
ns
RdCS to Valid Data In
(no RW-delay)
t47
SR –
69 + tC
–
3TCL - 25
+ tC
ns
RdCS, WrCS Low Time
(with RW-delay)
t48
CC 53 + tC
–
2TCL - 10
+ tC
–
ns
RdCS, WrCS Low Time
(no RW-delay)
t49
CC 84 + tC
–
3TCL - 10
+ tC
–
ns
Data valid to WrCS
t50
CC 48 + tC
–
2TCL - 15
+ tC
–
ns
Data hold after RdCS
t51
SR 0
–
0
–
ns
Data float after RdCS
(with RW-delay)
t53
SR –
43 + tF
–
2TCL - 20
+ tF
ns
Data float after RdCS
(no RW-delay)
t68
SR –
11 + tF
–
TCL - 20
+ tF
ns
Address hold after
RdCS, WrCS
t55
CC -5 + tF
–
-5
+ tF
–
ns
Data hold after WrCS
t57
CC 16 + tF
–
TCL - 15
+ tF
–
ns
Semiconductor Group
38
1996 Intermediate Version
Figure 12-1
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE
Semiconductor Group
39
C161
1996 Intermediate Version
Figure 12-2
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE
Semiconductor Group
40
C161
1996 Intermediate Version
Figure 12-3
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE
Semiconductor Group
41
C161
1996 Intermediate Version
Figure 12-4
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE
Semiconductor Group
42
C161