INFINEON TUA6045

D a ta S he et , R ev i s i on 3. 1, D e c em be r 20 0 6
TUA 6045-2
Low P ow er 3 -Ba nd D i gita l T V / Po r tab le
Tu ne r IC
TA IF UN 3
Co mmu nicat i on So lutio ns
Edition 2006-12-19
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of noninfringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
D a ta S he et , R ev i s i on 3. 1, D e c em be r 20 0 6
TUA 6045-2
Low P ow er 3 -Ba nd D i gita l T V / Po r tab le
Tu ne r IC
TA IF UN 3
Co mmu nicat i on So lutio ns
TUA 6045-2
TUA 6045-2 ’TAIFUN 3’
Revision History:
2006-12-19
Data Sheet, Revision 3.1
Previous Version:
2006-09-12
Preliminary Specification, Revision 3.0
Page
Subjects (major changes since last revision)
9 - 11, 28, L-Band application added. Operating range and AC/DC Characteristics
30 - 41
extended for L-Band.
31 - 41
Table Footnote added with description for impedance measurement.
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Data Sheet
4
Revision 3.1, 2006-12-19
Table of Contents
Page
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1
Product Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.2
2.2.1
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mixer/Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAW Filter Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IF AGC Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IF switch and Loop through for tuner alignment . . . . . . . . . . . . . . . . . .
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended band limits in MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
10
10
11
11
11
11
11
12
3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mixer-Oscillator-block, SAW filter driver . . . . . . . . . . . . . . . . . . . . . . . .
RF AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IF AGC amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL block, XTAL oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC/DC clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-on Reset, Stand-by Condition . . . . . . . . . . . . . . . . . . . . . . . . . .
IF switch, Loop thru . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
21
22
22
22
22
23
23
24
24
25
4
4.1
4.2
4.3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tuner application block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application circuit for hybrid application . . . . . . . . . . . . . . . . . . . . . . . . . .
Application circuit for L-Band application . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
27
28
5
5.1
5.1.1
5.1.2
5.1.3
5.2
5.3
5.4
5.5
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Byte Specification, Function and Defaults . . . . . . . . . . . . . . . . . . . . .
29
29
29
30
31
41
43
45
48
Data Sheet
5
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
5.5.1
5.5.2
5.6
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
5.6.8
Write Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gain (GV) measurement in LOW band . . . . . . . . . . . . . . . . . . . . . . . . .
Gain (GV) measurement in MID and HIGH bands . . . . . . . . . . . . . . . .
Matching circuit for optimum noise figure in LOW band . . . . . . . . . . . .
Noise figure (NF) measurement in LOW band . . . . . . . . . . . . . . . . . . .
Noise figure (NF) measurement in MID and HIGH bands . . . . . . . . . . .
Cross modulation measurement in LOW band . . . . . . . . . . . . . . . . . . .
Cross modulation measurement in MID and HIGH bands . . . . . . . . . . .
Ripple susceptibility measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Package PG-VQFN-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Data Sheet
6
48
56
59
59
59
60
60
61
61
62
62
Revision 3.1, 2006-12-19
TUA 6045-2
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Data Sheet
ATSC tuners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DVB-T and analog tuners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISDB-T tuners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC/DC Characteristics, TA = 25°C, VCC = 3.3V . . . . . . . . . . . . . . . . . .
Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Address Organization in I2C Mode . . . . . . . . . . . . . . . . . . . . . . .
Address selection in I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sub Addresses of Write Data Registers . . . . . . . . . . . . . . . . . . . . . . .
Sub Addresses of Read Data Registers . . . . . . . . . . . . . . . . . . . . . . .
Bus Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subaddress 00H, Main Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subaddress 01H, Control Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subaddress 02H, Reference Divider R and Crystal Oscillator Control
Subaddress 03H, AGC control and IF Signal Processing Control . . . .
Subaddress 04H, DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . .
Subaddress 06H, Mode Bytes, Test Mode and Standby Control . . . .
Subaddress 80H, Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subaddress 8EH, Chip Code “6045” . . . . . . . . . . . . . . . . . . . . . . . . . .
Subaddress 8FH, Revision Code, advanced with design steps . . . . .
7
12
12
12
29
30
31
41
42
42
42
43
43
46
48
49
50
52
54
55
56
57
58
Revision 3.1, 2006-12-19
TUA 6045-2
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Data Sheet
Pin Configuration TUA 6045-2 in VQFN-48 Package . . . . . . . . . . . . .
Block Diagram TUA 6045-2 in VQFN-48 package. . . . . . . . . . . . . . . .
Functional Block Diagram of IF switch and Loop thru . . . . . . . . . . . . .
Tuner application block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Circuit diagram for hybrid application (DVB-T / PAL). . . . . . . . . . . . . .
Circuit diagram for L-Band application. . . . . . . . . . . . . . . . . . . . . . . . .
I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-Wire Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gain (GV) measurement in LOW band . . . . . . . . . . . . . . . . . . . . . . . .
Gain (GV) measurement in MID and HIGH bands. . . . . . . . . . . . . . . .
Matching circuit for optimum noise figure in LOW band . . . . . . . . . . .
Noise figure (NF) measurement in LOW band. . . . . . . . . . . . . . . . . . .
Noise figure (NF) measurement in MID and HIGH bands . . . . . . . . . .
Cross modulation measurement in LOW band . . . . . . . . . . . . . . . . . .
Cross modulation measurement in MID and HIGH bands . . . . . . . . . .
Ripple susceptibility measurement . . . . . . . . . . . . . . . . . . . . . . . . . . .
PG-VQFN-48 Vignette . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PG-VQFN-48 Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
13
21
25
26
27
28
45
45
59
59
60
60
61
61
62
62
63
63
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Product Info
1
Product Info
General Description
The TUA 6045-2 integrates the mixer-oscillator, AGC amplifier and a digitally
programmable phase lock loop (PLL). This makes the TUA 6045-2 an ideal product for
applications where size and low power consumption are required design key factors.
Typical applications include TV's, VCR's, Set Top Boxes (STB) and also a range of
portable products.
Features
General
PLL
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Suitable for PAL, NTSC, SECAM,
DVB, DMB, DAB, ISDB-T and ATSC
High band covers frequency range for
L-Band up to 1.5 GHz
Supply voltage range from 3 to 5.5 V
Combined small - wide AGC detection
AGC + AGC buffer output
Low phase noise
Full ESD protection
Qualified according to JEDEC for
consumer applications
•
I2C / three wire combi bus
4 independent I2C addresses
High voltage VCO tuning output
Two PMOS ports
One voltage referred port
Internal LOW/MID/HIGH band switch
Xtal oscillator, range from 4 to 16 MHz
Xtal buffer output with programmable
level and output divider
Clock generator for DC/DC converter
with programmable low and high time
Mixer/Oscillator
Power management
•
•
•
•
•
•
•
Three band tuner
Unbalanced highohmic LOW band
input
Balanced lowohmic MID band input
Balanced lowohmic HIGH band input
Two pin oscillators for LOW/MID band
Four pin oscillator for HIGH band
Bus controlled stand by mode
Application
•
The IC is suitable for PAL, NTSC,
SECAM, DVB-C, DVB-T, DVB-H,
DMB-T, DAB, ISDB-T, ATSC and LBand tuners.
IF-Amplifier
•
•
•
4 IF pins to connect a 2 pole bandpass
Symmetrical SAW driver
Fully balanced IF AGC amplifier
Ordering Information
Type
Ordering Code
Package
TUA 6045-2
SP000250164
PG-VQFN-48
Data Sheet
9
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Product Description
2
Product Description
The TUA 6045-2 integrates the mixer-oscillator, variable AGC output amplifier and a
digitally programmable phase lock loop (PLL) not requiring an external high voltage
buffer. Furthermore, the TUA 6045-2 integrates a buffered RF AGC and programmable
clock signals for an external DC-DC up converter.
The integrated mixer oscillator function comprises of three balanced mixers. The first
mixer has an unbalanced high impedance input while the other two have balance low
impedance inputs. The tuner also has firstly, 2-pin asymmetric oscillators for both Low
and Mid bands and secondly a 4-pin symmetrical oscillator for High band operations
including a band selector switch.
The output signal from the mixer is amplified via a SAW filter driver followed by variable
gain amplifier stage in order to achieve a constant output level used for A/D conversion.
All functions can be programmed with up to four different IC addresses. Also, the PLL
connected to a 4-16 MHz reference crystal which is buffered on-chip, allows the setting
of the tuner oscillator with a minimum step size of 20 kHz. A Lock flag will be set once
the PLL is locked and communicated via the I2C/3-Wire bus.
The complete control setting of the IC is done by a microprocessor via the I2C/3-Wire
bus. The device also has three output ports of which P2 can be configured as a
programmable output voltage port.
2.1
Features
2.1.1
General
•
•
•
•
•
Supply voltage range 3 to 5.5 V.
Suitable for PAL, NTSC, SECAM, DVB-T/H/C, DAB, ISDB-T, ATSC and L-Band.
Wideband and Narrow AGC detectors for tuner RF AGC
− 5 programmable take-over points
− 2 programmable time constants.
Low phase noise.
Full ESD protection.
2.1.2
•
•
•
•
•
•
•
Mixer/Oscillator
High impedance mixer input (common emitter) for LOW band.
Low impedance mixer input (common base) for MID band.
Low impedance mixer input (common base) for HIGH band.
2 pin oscillator for LOW band.
2 pin oscillator for MID band.
4 pin oscillator for HIGH band.
Oscillator for HIGH band divided by 3 available for MID band mixer.
Data Sheet
10
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Product Description
2.1.3
•
2.1.4
•
•
•
•
•
•
•
•
IF switch and Loop through for tuner alignment
2 programmable switches to bypass the bandpass/SAW filter to facilitate the tuner
pre-stage alignment.
2.2
•
PLL
4 independent I2C addresses, or 3-Wire bus mode.
I2C bus protocol compatible with 3.3 V and 5V micro-controllers up to 400 kHz.
High voltage VCO tuning output.
3 PNP ports, one of them realized as programmable voltage output.
1 clock output for external DC/DC upconversion to generate the tuning supply
voltage, may be used as NPN port.
Stand-by programmable for functional blocks allows customized ramping.
Internal LOW/MID/HIGH band switch.
Lock-in flag.
4 to 16 MHz crystal oscillator with programmable output buffer.
programmable reference divider ratios.
4 charge pump currents, programmable in 15 steps.
2.1.6
•
IF AGC Amplifier
Symmetrical variable gain IF output amplifier with low noise, high linearity,
high dynamic range.
2.1.5
•
•
•
•
•
SAW Filter Driver
Symmetrical IF preamplifier with low output impedance able to drive a compensated
SAW filter (500 Ω//40 pF).
Application
The IC is suitable for PAL, NTSC, SECAM, DVB-T/H/C, DAB, ISDB-T, ATSC and LBand tuners.
The integrated RF AGC control has wide band detectors at the mixer inputs and
a narrowband detector at the saw filter driver output.
Data Sheet
11
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Product Description
2.2.1
Table 1
Recommended band limits in MHz
ATSC tuners
RF input
Oscillator
Band
min.
max.
min.
max.
LOW
55.25
157.25
101
203
MID
163.25
451.25
201
479
HIGH
457.25
861.25
503
907
Table 2
DVB-T and analog tuners
RF input
Band
Oscillator
min.
max.
min.
max.
LOW
48.25
MID
161.25
154.25
87.15
193.15
439.25
200.15
478.15
HIGH
447.25
863.25
486.15
902.15
Table 3
ISDB-T tuners
RF input
Band
Oscillator
min.
max.
min.
max.
LOW
93
167
150
224
MID
173
467
230
524
HIGH
473
767
530
824
Note: Tuning margin of 3 MHz not included.
Data Sheet
12
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
37 MIXOUT
38 MIXOUT
39 n.c.
40 n.c.
41 n.c.
43 LOWIN
44 MIDIN
45 MIDIN
Pin Configuration
46 HIGHIN
3.1
47 HIGHIN
Functional Description
48 OSCLOWIN
3
42 RFGND
Functional Description
OSCLOWOUT 1
36 SAWIN
OSCGND 2
35 SAWIN
OSCMIDIN 3
34 P2, VRF
OSCMIDOUT 4
33 P1
OSCHIGHIN 5
32 P0
OSCHIGHOUT 6
31 RFAGC
TUA 6045-2
VQFN-48 package
OSCHIGHOUT 7
30 RFAGC Buffer
OSCHIGHIN 8
29 SDA
VCC 9
28 SCL
SAWOUT 10
27 CAS/EN
SAWOUT 11
26 Busmode
Data Sheet
X_TAL Buff 23
DC/DC Clock 22
DC/DC_GND 21
VDD 20
CP 19
VT 18
IFOUT 17
IFOUT 16
IFAMPAGC 15
IFIN 14
IFIN 13
Figure 1
X_TAL OUT 24
49
GND 12
25 X_TAL IN
GND
package
Pin Configuration TUA 6045-2 in VQFN-48 Package
13
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Functional Description
3.2
•
Pin Definition and Functions
Pin Definition and Functions
Pin Symbol
No.
Equivalent I/O Schematic
Average DC voltage
at VCC = 3.3V
LOW
48
OSCLOWIN
2.3 V
1
OSCLOWOUT
1.8 V
MID
HIGH
0.0 V
0.0 V
1
48
2
OSCGND
Oscillator ground
0.0 V
3
OSCMIDIN
2.3 V
4
OSCMIDOUT
1.8 V
4
3
Data Sheet
14
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Functional Description
Pin Symbol
No.
Equivalent I/O Schematic
Average DC voltage
at VCC = 3.3V
LOW
MID
HIGH
5
OSCHIGHIN
2.3 V
6
OSCHIGOUT
2.25 V
7
OSCHIGOUT
8
OSCHIGHIN
6
7
5
8
Supply voltage
2.25 V
2.3 V
9
VCC
3.3 V
3.3 V
3.3 V
10
SAWOUT
1.65 V 1.65 V 1.65 V
11
SAWOUT
1.65 V 1.65 V 1.65 V
10, 11
12
GND
0.0 V
13
IFIN
2.64 V 2.64 V 2.64 V
14
IFIN
2.64 V 2.64 V 2.64 V
13
Data Sheet
0.0 V
0.0 V
14
15
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Functional Description
Pin Symbol
No.
15
Equivalent I/O Schematic
Average DC voltage
at VCC = 3.3V
IFAMPAGC
LOW
MID
HIGH
n.a.
n.a.
n.a.
15
16
IFOUT
1.6 V
1.6 V
1.6 V
17
IFOUT
1.6 V
1.6 V
1.6 V
16
17
18
VT
VT
VT
VT
19
CP
1.7 V
1.7 V
1.7 V
3.3 V
3.3 V
3.3 V
18
19
20
VDD
Supply voltage
21
DC/DC_GND
0.0 V
0.0 V
0.0 V
22
DC/DC Clock
n.a.
n.a.
n.a.
22
21
Data Sheet
16
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Functional Description
Pin Symbol
No.
23
Equivalent I/O Schematic
Average DC voltage
at VCC = 3.3V
LOW
MID
HIGH
0.9 V
0.9 V
0.9 V
0.9 V
0.9 V
0.9 V
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
XTAL Buffer
23
24
XTAL Out
25
XTAL In
25
24
26
Busmode
26
27
CAS/EN
27
V ref
Data Sheet
17
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Functional Description
Pin Symbol
No.
28
Equivalent I/O Schematic
SCL
Average DC voltage
at VCC = 3.3V
LOW
MID
HIGH
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
28
29
SDA
29
30
RFAGC Buffer
3.2 V
3.2 V
3.2 V
31
RFAGC
3.2 V
3.2 V
3.2 V
31
+
30
disable
32
P0
33
P1
0 V or 0 V or 0 V or
VCC- VCC- VCCVCE
VCE
VCE
32, 33
Data Sheet
18
0 V or 0 V or 0 V or
VCC- VCC- VCCVCE
VCE
VCE
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Functional Description
Pin Symbol
No.
34
Equivalent I/O Schematic
Average DC voltage
at VCC = 3.3V
P2, VRF
LOW
MID
HIGH
VRF
VRF
VRF
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
0.0 V
0.0 V
0.0 V
34
35
SAWIN
36
SAWIN
37
MIXOUT
38
MIXOUT
35
36
37
38
Oscillator
39
n. c.
40
n. c.
41
n. c.
42
RFGND
Data Sheet
IF ground
19
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Functional Description
Pin Symbol
No.
Equivalent I/O Schematic
Average DC voltage
at VCC = 3.3V
LOW
43
LOWIN
MID
HIGH
2
43
44
MIDIN
1
45
MIDIN
1
44
45
46
HIGHIN
1
47
HIGHIN
1
46
49
47
GND package Exposed pad ground (Die pad)
Data Sheet
20
0.0 V
0.0 V
0.0 V
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Functional Description
OSCLOWOUT
1
OSCGND
2
OSCMIDIN
3
OSCMIDOUT
LOWIN
RFGND
n.c.
n.c.
n.c.
MIXOUT
MIXOUT
46
MIDIN
47
MIDIN
48
HIGHIN
HIGHIN
Functional Block Diagram
OSCLOWIN
3.3
45
44
43
42
41
40
39
38
37
Oscillator
MID
Mixer
HIGH
RF Input
HIGH
Mixer
MID
RF Input
MID
4
Oscillator
HIGH
OSCHIGHIN
36
SAWIN
35
SAWIN
34
P2, VRF
33
P1
32
P0
31
RFAGC
30
RFAGC Buffer
Oscillator
LOW
Mixer
LOW
5
RF Input
LOW
PORTS
OSCHIGHOUT
6
OSCHIGHOUT
7
OSCHIGHIN
8
SAW
Filter
Driver
Lock
Detector
AGC
Detector
Prog.
Divider
AGC
VCC
I2C Bus
9
fdiv
VCC
Phase/
Freq
Comp
1/N
Divider
SAWOUT 10
29
SDA
28
SCL
27
CAS / EN
26
Busmode
FL
fref
Reference
Divider
SAWOUT 11
DC / DC
Signal
Crystal
Oscillator
R
12
25
X_TAL IN
Figure 2
Data Sheet
15
16
17
18
19
20
21
22
IFIN
IFAMPAGC
IFOUT
IFOUT
VT
CP
VDD
DC/DC_GND
DC/DC
Clock
23
24
X_TAL OUT
14
X_TAL Buff
13
IFIN
VDD
GND
Charge
Pump
IF AGC
Amplifier
TUA 6045-2
Block Diagram TUA 6045-2 in VQFN-48 package
21
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Functional Description
3.4
Circuit Description
3.4.1
Mixer-Oscillator-block, SAW filter driver
The mixer-oscillator block includes three balanced mixers (one mixer with an unbalanced
high-impedance input and two mixers with a balanced low-impedance input), two 2-pin
asymmetrical oscillators for the LOW and the MID band, one 4-pin symmetrical oscillator
for the HIGH band, a reference voltage, and a band switch.
Filters between tuner input and IC separate the TV frequency signals into three bands.
The band switching in the tuner front-end is done by using three PNP port outputs. In the
selected band, the signal passes through a tuner input stage with a MOSFET amplifier,
a double-tuned bandpass filter and is finally fed to the mixer input of the IC. The
impedance of the mixer at LOW band has high ohmic, while MID or HIGH band has a
low ohmic input. The input signal is mixed there with the signal from the activated on chip
oscillator to the IF frequency.
The IF is filtered by means of an external SAW filter (Surface Acoustic Waves filter) in
between the 2 mixer output pins and the 2 input pins of the following SAW filter driver.
The SAW filter driver has a low output impedance to drive the SAW filter directly.
3.4.2
RF AGC
The RF AGC stage combines a wide band and a narrow band detection. The wide band
detector (WB) detects the input signal directly at the RF input for each band. The narrow
band detector (NB) detects the level of the SAW filter driver output signal. If both
detected levels are below the RF AGC take-over points, a external capacity will be
charged with the source current of 300 nA or 9 µA (release current). If one of the
detected levels is above the RF AGC take-over points, the external capacity will be
discharged with the sink current of 100 µA (attack current). The integrated current
generates an AGC voltage for gain control of the tuners input transistors. The AGC takeover and the time constant are selectable by the I2C bus as shown in Table 17
"Subaddress 03H, AGC control and IF Signal Processing Control" on Page 52.
An integrated RF AGC buffer allows to monitor the AGC voltage without any influence
on the tuner gain control. This buffer can be disabled as shown in Table 16
"Subaddress 02H, Reference Divider R and Crystal Oscillator Control" on Page 50
3.4.3
IF AGC amplifier
Coming out of the SAW filter the IF signal is sent through a VGA (Variable Gain Amplifier)
which will set the differential IF output signal to the desired level (preferably 1 Vpp). The
gain of the VGA is determined by the DC-voltage at pin IFAMPAGC
Data Sheet
22
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Functional Description
3.4.4
PLL block, XTAL oscillator
The VCO frequency fOSC is stabilized by a digital CMOS PLL (Phase Locked Loop,
Frequency Synthesizer). The oscillator signal is internally DC-coupled as a differential
signal to the programmable divider input. The signal subsequently passes through a
programmable divider (N) and then the divided VCO signal:
f OSC
f div = ------------, ( N = 240…65535 )
N
is compared in a digital frequency/phase detector (PD, frequency detector) with a
programmable reference frequency:
f XTAL
f ref = ---------------, ( R = 2…1023 )
R
which is derived from a quartz reference fXTAL divided by a programmable reference
divider (R).
The phase detector has a linear operating range without a dead zone for very small
phase deviations. A programmable ABL pulse width (Anti BackLash) works against the
delay of the charge pump cell. The selectable ABL pulse width values have been
implemented for test purpose only and have no performance effects.
The phase detector has two outputs (up & down) that drive two current sources of
opposite polarity as charge pump (CP). If the negative edge of the divided VCO signal
appears prior to the negative edge of the reference signal, the positive current source
(Isource) pulses for the duration of the phase difference. In the reverse case the negative
current source (Isink) pulses. If the two signals are in phase (PLL is locked), the integrated
charge pump current is approximately zero. In case of active closed loop control the
charge pump provides programmable output current drive capability to optimize the loop
requirements. The charge pump currents are programmable from 0 to 1.125 mA in steps
of 75 µA.
The PLL contains an integrated lock detector. A lock-in flag is set when the loop is
locked. It can be read by the processor via the common I2C/3-Wire bus.
The crystal oscillator (XTAL) is an unbalanced Pierce oscillator which operates in parallel
resonance with quartz crystals from 4...16 MHz. By programming it’s possible to pass
the oscillator frequency fXTAL through a divider stage to a buffered output pin or to use an
external quartz clock for the reference oscillator via a switchable preamplifier for test
purpose only.
3.4.5
Bus Interface
The programming of the CMOS frequency synthesizer is done via a combined serial
I2C/3-Wire bus interface. The choice of the desired bus is made by a bus mode select
signal at pin BUSMODE.
Data Sheet
23
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Functional Description
In I2C-bus mode four different chip addresses can be set by appropriate DC levels at pin
CAS (Chip Address Select), while in 3-Wire mode the chip is addressed by a low active
enable signal at pin EN.
The content of the bus telegram (serial data format) is controlled by software
programming and assigned to the registers of the functional units according to the
several sub addresses. The most significant bit (MSB) of the data protocol is shifted in
first.
The clock is generated by the processor (input pin SCL/Clock), while pin SDA/Data
functions as an input or an output (open drain, external pull-up resistor) depending on
the direction of the data (write or read mode). Both inputs have schmitt-trigger circuits
with hysteresis and furthermore a low-pass characteristic, which suppress a certain
noise level on the bus lines and enhance so the noise immunity of the combi-bus.
A detailed description of the chip address organization in I2C-mode as well as the used
sub addresses of the data registers is given in chapter 5.2 "Bus Interface" on page 41
- and the programmable I2C/3-Wire bus data format is shown in chapter 5.3 "Bus Data
Format" on page 43.
3.4.6
DC/DC clock output
To drive a bipolar NPN switching transistor of an external DC/DC converter directly, a
programmable DC/DC clock generator is integrated. The clock frequency and the duty
cycle of the DC/DC clock generator can be set over the I2C/3-Wire bus as shown in
Table 18 "Subaddress 04H, DC-DC Converter" on Page 54.
3.4.7
Power-on Reset, Stand-by Condition
While applying the supply voltage, integrated power-on reset circuits ensure a defined
state after initial power-up. The required programming data will be set to default values.
When VCC fall below approximately 1.2 V (typ.) the power-on resets go active and tie all
write data registers to their power-on defaults (= power-down reset). While power-on
reset is active no programming is possible.
The power-on flags (POFx) are set at power-on and when VVCCx falls below appr. 1.2 V
(typ.). They will be reset at the end of a READ operation of the status register.
By programmable stand-by control bits it’s possible to reduce the current consumption
of the IC up to 99%. In the full stand-by mode only bus interface is staying active and the
current consumption is reduced below 200 µA. After power-on reset only bus interface
and XTAL-oscillator with bandgap are active and the current consumption is about
2.6 mA (typ.).
Data Sheet
24
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Functional Description
3.4.8
IF switch, Loop thru
For the alignment procedure of the tuner module two programmable switches are
integrated to bypass the bandpass, the SAW driver and the SAW filter. The first switch
called “IF switch” can switch between the mixer output signal and the bandpass output
signal. The second switch called “Loop thru” can switch between the signal after the first
stage of the IF AGC amplifier and the SAW filter output signal.
IF switch control = bit 15 of sub address 03H
Loop thru control = bit 14 of sub address 03H
Bandpass
IF AGC amplifier
IF switch
MIXER
input
IF
output
Loop thru
MIXER
SAW
Filter
SAWDRV
Figure 3
Data Sheet
Functional Block Diagram of IF switch and Loop thru
25
Revision 3.1, 2006-12-19
Figure 4
Data Sheet
LOW band
MID band
HIGH band
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3
3
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9ROWDJH
Tuner application block diagram
/2:
a
a
a
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'HFRGHU
4.1
a
a
a
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TUA 6045-2
TAIFUN 3
Applications
Tuner application block diagram
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Applications
Application circuit for hybrid application
X6
HICH
X5
MID
2
3
4
TR3
TR2
C50 100n
X4
LOW
R27 50R
C56
C54
C53
C52
C51
22p
22p
1n
1n
1n
GND
R25
0R
C55
C1 2p7
R26
C49
np
np
R24
38
OSCLOWOUT
2
GND
37
C47
5p6
0R
MIXOUT
39
/MIXOUT
40
n.c
41
n.c
42
RFGND
43
LOWIN
MIDIN
44
/MIDIN
1
45
/HIGHIN
C2 2p2
46
HIGHIN
OSCLOWIN
47
D1 BB659C
R2 2k7
C48
GND
np
2p2
48
C10
100p
GND
GND
L1 8,5 turns
R1 12R
GND
GND
GND
L9
6
np
1
L10
3
4
390nH
6
L11
2
1
390nH
GND
VCC
GND
GND
MACOM 1:1(ETC1-1-13)
MACOM 1:1(ETC1-1-13)
GND
n.c
4.2
SAWIN
OSCGND
/SAWIN
OSCMIDIN
P2,VRF
36
C46 22p
35
C45 22p
GND
GND
D2 BB659C
R3 2k7
C3 1p5
3
34
P2,VRF
C11
R4 8R2
GND
GND
C15
22n
L2 2,5 turns
82p
R5 2k2
C44 4n7
C4 1p2
C12 22p
C5
4
1p2
5
OSCMIDOUT
IC1
OSCHIGHIN
P1
C43 4n7
3n3
P0
C42 4n7
L3
2 turns
C6 1p2
D3
BB555
R9
2k2
6
C7 1p2
7
C8 1p2
8
/OSCHIGHOUT
31
RF AGC
TUA6045-2 (VQFN48)
OSCHIGHOUT
C41 100n
R6 2k2
0R
RF AGC Buffer
L4
30
RF AGC Buffer
C13
C40 4n7
R23 220R
29
SDA
GND
9
VCC
SCL
28
R22 220R
27
R21 100R
C39
R10 0R
/SAWOUT
Busmode
C38 100p
13
14
15
16
17
18
19
20
21
X_TAL Buff
X_TAL OUT
DC/DC Clock
GND
VDD
OUT
GND
CP
GND
GND
VT
3
12
22
23
X_tal in
IF
C18
7
2p7
GND
6
X1
SMA
GND
/IFOUT
GND
TR1
TOKO(A1010)-TRANSFORMER
4
GND
GND
nc.
5
IFOUT
C20
C21
C23
10n
1n
1n
6n8
C37 47p
GND
GND
Busmode
J1
JUMPER 1X2
GND
GND
C32
39p
GND
X2
GND
SMA
R19 np
L8
220nH
VCC
L7 1mH
V1
BC847
C29
np
R18
100n
R12
10k
SMA
GND2
100k 33p
12p
3
4n7
GND
C24
C22
2
X3
np
4MHz
1n
C28
100n
L6
68nH
GND
R13
C34
Q1
C31
GND
GND
1
25
C33 39p
R17
0R
GND2
VCC
4
np
C16
GND
C19
GND
26
R20
0R
24
C17
2p7
GND
CAS/EN
GND
C36 47p
11
2
GND
SIP5D
5
CAS/EN
C35
GND
OUT
SAW1
X6966D
R11 0R
IN
IN
1
L5 1u2H
SAWOUT
IFOUT
GND
10
100p
SCL
68nH
100n
GND
SDA
C9 100n
/IFOUT
VCC
/OSCHIGHIN
IFAMPAGC
GND
R7
IFIN
GND
IFIN
C57
GND
GND
Vt
270p
GND
32
PO
C14
R8
150k
GND
33
P1
D4
BAS 70-02W
C30
100n
GND2
GND
GND
IFAMPAGC
R14
R16
R15
10K
100n
GND
PLL
33k
10K
C25
D5
Z33
C26
C27
100n
22n
GND2
GND2
GND2
J3
SDA
SCL
GND
CAS/EN
STOCKO 4pol
Figure 5
Data Sheet
Circuit diagram for hybrid application (DVB-T / PAL)
27
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Applications
Application circuit for L-Band application
X6
HICH
X5
MID
GND
4
TR3
TR2
C50 100n
X4
LOW
R27 50R
C56
C54
C53
C52
C51
22p
22p
1n
1n
1n
GND
R25
0R
C55
C1 2p7
C48
GND
np
np
R24
39
38
OSCLOWOUT
2
GND
37
C47
5p6
0R
MIXOUT
40
/MIXOUT
41
n.c
42
n.c
43
RFGND
1
44
LOWIN
C2 2p2
45
MIDIN
R2 2k7
46
/MIDIN
D1 BB659C
/HIGHIN
47
OSCLOWIN
100p
R26
C49
np
2p2
48
C10
HIGHIN
R1 12R
GND
GND
GND
L1 8,5 turns
GND
GND
L9
6
3
np
4
2
L10
1
390nH
6
3
L11
2
1
390nH
GND
MACOM 1:1(ETC1-1-13)
PULSE 1:1(CX2156)
GND
VCC
GND
n.c
4.3
SAWIN
OSCGND
/SAWIN
OSCMIDIN
P2,VRF
36
C46 22p
35
C45 22p
GND
GND
D2 BB659C
R3 2k7
C3 1p5
3
34
P2,VRF
C11
R4 8R2
GND
C15
22n
R5 2k2
C12 1p8
C5
C14
3n3
R8
1M
C4 1p2
L3
2 turns (small)
GND
L2 2,5 turns
82p
D3
BB555
R9
2k2
C44 4n7
4
1p2
5
C6 1p2
6
OSCMIDOUT
IC1
OSCHIGHIN
P1
C43 4n7
P0
C42 4n7
C7 1p2
7
C8 1p2
8
31
RF AGC
TUA6045-2 (VQFN48)
OSCHIGHOUT
C41 100n
R6 2k2
0R
RF AGC Buffer
L4
30
RF AGC Buffer
C13
C40 4n7
R23 220R
29
SDA
GND
9
VCC
SCL
28
R22 220R
27
R21 100R
C39
R10 0R
Busmode
/SAWOUT
C38 100p
13
14
15
16
17
18
19
20
21
X_TAL Buff
X_TAL OUT
DC/DC Clock
GND
VDD
OUT
GND
CP
GND
VT
GND
12
22
23
X_tal in
4
np
C16
GND
/IFOUT
TR1
TOKO(A1010)-TRANSFORMER
GND
GND
4
GND
C21
C23
1n
1n
6n8
IFOUT
R17
0R
GND2
C37 47p
C34
GND
C32
39p
GND
GND
SMA
R19 np
L8
220nH
VCC
12p
L7 1mH
V1
BC847
C29
np
R18
100n
R12
10k
GND
GND
GND2
100k 33p
Busmode
J1
JUMPER 1X2
X2
100n
L6
68nH
GND
3
4n7
SMA
GND
C24
C22
2
X3
np
4MHz
1n
R13
GND
1
GND
Q1
C31
C28
VCC
IF
nc.
5
C20
10n
25
C33 39p
GND
2p7
7
6
X1
SMA
GND
GND
C19
C18
GND
26
R20
0R
24
C17
2p7
GND
CAS/EN
GND
C36 47p
11
2
3
SIP5D
5
CAS/EN
C35
GND
GND
OUT
SAW1
X6966D
R11 0R
IN
IN
1
L5 1u2H
SAWOUT
IFOUT
GND
10
100p
SCL
68nH
100n
GND
SDA
C9 100n
/IFOUT
VCC
/OSCHIGHIN
IFAMPAGC
GND
R7
IFIN
GND
IFIN
C57
GND
GND
Vt
270p
GND
32
PO
/OSCHIGHOUT
GND
33
P1
D4
BAS 70-02W
C30
100n
GND2
GND
GND
IFAMPAGC
R14
R16
R15
10K
100n
GND
PLL
33k
10K
C25
D5
Z33
C26
C27
100n
22n
GND2
GND2
GND2
J3
SDA
SCL
GND
CAS/EN
STOCKO 4pol
Figure 6
Data Sheet
Circuit diagram for L-Band application
28
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
5
Reference
5.1
Electrical Data
5.1.1
Absolute Maximum Ratings
Attention: The maximum ratings may not be exceeded under any circumstances,
not even momentarily and individually, as permanent damage to the IC
will result.
Table 4
#
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
Unit Remarks
max.
1.
Supply voltage
VCC
-0.3
5.5
V
2.
Ambient temperature
TA
-40
+85
°C
3.
Junction temperature
TJ
-40
+125
°C
4.
Storage temperature
TStg
-40
+125
5.
Thermal resistance
junction to ambient
RTHJA
CP
VCP
exposed GND pad
soldered
°C
39
K/W
-0.3
3
V
-0.3
5.5
V
10
mA
exposed GND pad
soldered
PLL
6.
7.
ICP
8.
Bus input/output SDA
9.
Bus output current SDA ISDA(L)
10. Bus input SCL
VSDA
VSCL
1
mA
open drain
-0.3
5.5
V
11. Chip address switch AS VAS
-0.3
5.5
V
12. VCO tuning output (loop VVT
filter)
-0.3
35
V
13. PMOS port output
current of P0, P1
IP(L)
-10
0
mA
open drain
14. PMOS port output
current of P2,VRF
IP(L)
-2
-10
2
0
mA
mA
analog voltage
digital switch
-20
0
mA
tmax = 0.1 s at 5.5 V
20
mA
15. Total port output current ΣIP(L)
of PMOS ports
16. DC/DC output current
Data Sheet
IDC/DC
29
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
#
Parameter
Symbol
Limit Values
min.
Unit Remarks
max.
Mixer-Oscillator
17. Mix inputs LOW band
VLOW
18. Mix inputs MID/HIGH
19. band
VMID/HIGH
20. VCO base voltage
VB
21. VCO collector voltage
VC
-0.3
3
V
2
V
-5
6
mA
-0.3
3
V
LOW, MID and
HIGH band
oscillators
5.5
V
LOW, MID and
HIGH band
oscillators
VCC
V
2
kV
IMID/HIGH
22. Voltage on all other
Vmax
inputs, outputs, except
GNDs
-0.3
ESD-Protection
23. all pins
5.1.2
Table 5
#
VESD
Operating Range
Operating Range
Parameter
Symbol
Limit Values
min.
max.
Unit Remarks
1.
Supply voltage
VCC
+3.0
+5.5
V
nominal 3.3 V
2.
Ambient temperature
TA
-20
+85
°C
exposed GND pad
soldered
3.
Programmable divider
factor
N
240
65535
4.
LOW mixer input
frequency range
fMIXL
30
200
MHz
5.
MID band mixer input
frequency range
fMIXM
130
500
MHz
Data Sheet
30
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
#
Parameter
Symbol
Limit Values
min.
max.
Unit Remarks
6.
HIGH band mixer input fMIXH
frequency range
350
1500
MHz
7.
LOW oscillator
frequency range
fOL
65
250
MHz
8.
MID band oscillator
frequency range
fOM
165
530
MHz
9.
HIGH band oscillator
frequency range
fOH
400
1550
MHz
5.1.3
Table 6
#
AC/DC Characteristics
AC/DC Characteristics, TA = 25°C, VCC = 3.3V
Parameter1)
Symbol
Limit Values
min.
typ.
Unit Test Conditions
■
max.
Supply
10. Current
consumption in
11. active mode
IVCC
39
mA
VGA V1,V0=11,
SAW S1,S0=11
47
mA
VGA V1,V0=10,
SAW S1,S0=10
12.
54
mA
VGA V1,V0=01,
SAW S1,S0=01
13.
64
mA
VGA V1,V0=00,
SAW S1,S0=00
14.
IMIX
7
mA
Mixer current
15.
IVDD
8
mA
Digital part
16. Current
consumption in
stand-by mode
Istby
2.6
mA
bias, bus-interface
and crystal
oscillator active
17.
170
µA
full standby
IIC mode
18.
7
µA
full standby
3-wire mode
Data Sheet
31
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
#
Parameter1)
Symbol
Limit Values
min.
typ.
Unit Test Conditions
■
max.
Digital Part
PLL
Crystal oscillator connections XTAL
19. Crystal frequency
fXTAL
20. Crystal resistance
RXTAL
3.2
4.0
21.
16
MHz
270
Ω
4 MHz, 2x39pF
90
Ω
16 MHz, 2x18pF
22. Crystal oscillator
transconductance
gm,XTAL
-850
23. Oscillator
24. impedance
YXTALOSC
-150
µA/V 4 MHz, 2x39pF
-200
µA/V 16 MHz, 2x18pF
25. Buffer output
frequency
fXTALIO
26. XTAL Buffer output Vlow
low voltage
27. Buffer signal
28. voltage
0.4
0
50
VAC
29.
30. External input
31. signal voltage
-600 µA/V VOUT = 0.9V
VIN = 0.8 to 1.0V
16
MHz Divider ratios 1, 2,
4, 8
100
mV
200
mVpp XTAL3,XTAL2=0,1
400
mVpp XTAL3,XTAL2=1,0
800
VACin
1
3
50
200
mVpp XTAL3,XTAL2=1,1
Vpp
Amp off
mVpp Amp on
Tuning voltage output VT (open collector)
32. Output voltage
VTL
when the loop is
closed, (test mode
in normal
operation)
0.4
32.7 V
Ports
33. Standard Ports
(PMOS)
Imax
34. Output saturation
voltage
Vmax
35. Voltage refered
port
Imax
Data Sheet
-10
mA
0.25
-2
0.4
V
mA
32
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
#
Parameter1)
Symbol
Limit Values
min.
36. Voltage refered
port
typ.
V0
V1 ...
V26
V27
Unit Test Conditions
■
max.
0
0.1
2.6
2.7
V
V
V
V
DC/DC clock generator
THigh
1
127
Multiple of crystal
oscillator period
38. Programmable low TLow
1
127
Multiple of crystal
oscillator period
37. Programmable
high
39. Output high current Ihigh
250
µA
40. Output low
impedance
10
Ω
Rlow
Functional Range
0-2V
Analog Part without IF AGC
LOW band mixer and SAW driver at power level S1,S0=10
41. RF frequency
fRF
44.25
42. Voltage gain
GV
21
43. Noise figure
NF
170.25 MHz picture carrier2)
24
27
dB
8
10
dB
fRF = 48.25 MHz to
154.25 MHz
see 5.6.1 on page 59
fRF = 48.25 MHz to
154.25 MHz
see 5.6.4 on page 60
44. SAWOUT output
Vo
voltage causing
0.8% of
crossmodulation in
channel
111
45. Input IP3
120
dBµV fRF1 = 48.25 MHz,
fRF2 = 49.25 MHz,
PRF1 = PRF2
120
dBµV fRF1 = 154.25 MHz,
fRF2 = 155.25 MHz,
PRF1 = PRF2
see 5.6.6 on page 61
IIP3
46.
Data Sheet
dBµV fRF = 48.25 MHz to
154.25 MHz
33
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
#
Parameter1)
Symbol
Limit Values
min.
typ.
47. Output voltage
Vo
causing
1 dB compression
N+5
- 1 MHz
50. Input impedance
51. Zi = (Rp || 1/jωCp)
dBµV fRF = 48.25 MHz to
154.25 MHz
2.12 kHz
77
■
max.
125
48. Local oscillator FM FMI2C
caused by I2C
communication
49. (N+5) - 1 MHz
pulling
Unit Test Conditions
fRF = 154.25 MHz3)
80
dBµV fRFw = 69.25 MHz,
fOSC = 108.15 MHz,
fRFu = 108.25 MHz4)
Rp
1
kΩ
Cp
2
pF
parallel equivalent
circuit at 100 MHz5)
Mid band mixer and SAW driver at power level S1,S0=10
52. RF frequency
fRF
154.25
53. Voltage gain
GV
31
54. Noise figure
(not corrected for
image)
NF
454.25 MHz picture carrier2)
34
37
dB
fRF = 161.25 MHz
to 439.25 MHz
6
8
dB
fRF = 161.25 MHz
to 439.25 MHz
see 5.6.2 on page 59
see 5.6.5 on page 61
55. SAWOUT output
Vo
voltage causing
0.8% of
crossmodulation in
channel
110
56. Input IP3
110
dBµV fRF1 = 161.25 MHz,
fRF2 = 162.25 MHz,
PRF1 = PRF2
57.
108
dBµV fRF1 = 439.25 MHz,
fRF2 = 440.25 MHz,
PRF1 = PRF2
58. Output voltage
Vo
causing
1 dB compression
125
dBµV fRF = 161.25 MHz
to 439.25 MHz
see 5.6.7 on page 62
IIP3
59. Local oscillator FM FMI2C
caused by I2C
communication
Data Sheet
dBµV fRF = 161.25 MHz
to 439.25 MHz
2.12 kHz
34
fRF = 439.25 MHz3)
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
#
Parameter1)
Symbol
Limit Values
min.
60. (N+5) - 1 MHz
pulling
N+5
- 1 MHz
61. Input impedance
62. Zi = (Rs + jωLs)
typ.
77
Unit Test Conditions
■
max.
80
dBµV fRFw = 359.25 MHz,
fOSC = 398.15 MHz,
fRFu = 398.25 MHz4)
Rs
35
Ω
Ls
8
nH
fRF = 161.25 MHz
to 439.25 MHz5)
HIGH band mixer and SAW driver at power level S1,S0=10
63. RF frequency
fRF
399.25
64. Voltage gain
GV
31
65. Noise figure
(not corrected for
image)
NF
863.25 MHz picture carrier2)
34
37
dB
fRF = 447.25 MHz
to 863.25 MHz
6
8
dB
fRF = 447.25 MHz
to 863.25 MHz
see 5.6.2 on page 59
see 5.6.5 on page 61
66. SAWOUT output
Vo
voltage causing
0.8% of
crossmodulation in
channel
110
67. Input IP3
106
dBµV fRF1 = 447.25 MHz,
fRF2 = 448.25 MHz,
PRF1 = PRF2
68.
108
dBµV fRF1 = 863.25 MHz,
fRF2 = 864.25 MHz,
PRF1 = PRF2
69. Output voltage
Vo
causing
1 dB compression
125
dBµV fRF = 447.25 MHz
to 863.25 MHz
see 5.6.7 on page 62
IIP3
2.12 kHz
70. Local oscillator FM FMI2C
caused by I2C
communication
71. (N+5) - 1 MHz
pulling
N+5
- 1 MHz
72. Input impedance
73. Zi = (Rs + jωLs)
Data Sheet
dBµV fRF = 447.25 MHz
to 863.25 MHz
77
fRF = 863.25 MHz3)
80
dBµV fRFw = 823.25 MHz,
fOSC = 862.15 MHz,
fRFu = 862.25 MHz4)
Rs
35
Ω
Ls
8
nH
35
fRF = 447.25 MHz
to 863.25 MHz5)
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
#
Parameter1)
Symbol
Limit Values
min.
typ.
Unit Test Conditions
■
max.
HIGH band mixer and SAW driver in L-Band application (see 4.3 on page 28)
74. RF frequency
fRF
1452
75. Voltage gain
GV
29
1492 MHz picture carrier2)
32
35
dB
fRF = 1452 MHz to
1492 MHz
see 5.6.2 on page 59
76. Noise figure
(not corrected for
image)
NF
8
10
dB
fRF = 1452 MHz to
1492 MHz
see 5.6.5 on page 61
LOW band oscillator
77. Oscillator
frequency
fOSC
78. Phase noise,
carrier to noise
sideband
ΦOSC
80
6)
210
MHz
-84
-77
dBc/ ±1 kHz frequency
Hz
offset, wide loop,
worst case in the
frequency range
79.
-92
-88
dBc/ ±10 kHz frequency
Hz
offset, narrow loop,
worst case in the
frequency range
80.
-112
-106 dBc/ ±100 kHz
Hz
frequency offset,
worst case in the
frequency range
RSC
81. Ripple
susceptibility of VCC
-22
dBc
VRipple = 20 mVpp,
fRipple = 1 kHz7)
82.
-50
dBc
VRipple = 20 mVpp,
fRipple = 100 kHz7)
MHz
6)
MID band oscillator
83. Oscillator
frequency
Data Sheet
fOSC
201
493
36
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
#
Parameter1)
Symbol
Limit Values
min.
typ.
■
max.
-82
-75
dBc/ ±1 kHz frequency
Hz
offset, wide loop,
worst case in the
frequency range
85.
-92
-88
dBc/ ±10 kHz frequency
Hz
offset, narrow loop,
worst case in the
frequency range
86.
-112
-106 dBc/ ±100 kHz
Hz
frequency offset,
worst case in the
frequency range
87. Ripple
RSC
susceptibility of VCC
-25
dBc
VRipple = 20 mVpp,
fRipple = 1 kHz7)
88.
-55
dBc
VRipple = 20 mVpp,
fRipple = 100 kHz7)
905
MHz
6)
-80
-73
dBc/ ±1 kHz frequency
Hz
offset, wide loop,
worst case in the
frequency range
91.
-90
-86
dBc/ ±10 kHz frequency
Hz
offset, narrow loop,
worst case in the
frequency range
92.
-110
-106 dBc/ ±100 kHz
Hz
frequency offset,
worst case in the
frequency range
RSC
93. Ripple
susceptibility of VCC
-30
dBc
VRipple = 20 mVpp,
fRipple = 1 kHz7)
94.
-55
dBc
VRipple = 20 mVpp,
fRipple = 100 kHz7)
84. Phase noise,
carrier to noise
sideband
ΦOSC
Unit Test Conditions
HIGH band oscillator
89. Oscillator
frequency
fOSC
90. Phase noise,
carrier to noise
sideband
ΦOSC
435
HIGH band oscillator in L-Band application (see 4.3 on page 28)
Data Sheet
37
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
#
Parameter1)
Symbol
Limit Values
min.
95. Oscillator
frequency
fOSC
typ.
1488
Unit Test Conditions
max.
1528 MHz
96. Phase noise,
carrier to noise
sideband
-85
■
-80
6)
dBc/ ±10 kHz frequency
Hz
offset, narrow loop,
fRF = 1452 MHz to
1492 MHz
SAW driver
97. Voltage gain
GV
20
dB
fIF = 36 MHz to
54 MHz
98. Input impedance
99. Zi = (Rp || 1/jωCp)
RP
450
Ω
parallel equivalent
circuit at 36 MHz5)
CP
5
pF
100. Output impedance RS
101. Zo = (Rs + jωLs)
LS
65
Ω
20
nH
series equivalent
circuit at 36 MHz5)
Rejection at the SAW driver output
102. Level of divider
INTDIV
interferences in the
IF signal
-66
-60
dBc
VOUT = 100 dBµV8)
103. Crystal oscillator
interferences
rejection
-66
-60
dBc
VOUT = 100 dBµV9)
104. Reference
INTREF
frequency rejection
-66
-60
dBc
VOUT = 100 dBµV10)
105. Channel S02 beat INTS02
-60
-57
dBc
fRFpix = 76.25 MHz,
VRFpix = 80 dBµV11)
INTXTAL
RF AGC output
106. RF AGC take-over AGCTOP
point wide band
wide
(RF input)
87
77
99
89
dBµV LOW Band
MID, HIGH Band
107. RF AGC take-over AGCTOP
point narrow band narrow
(SAWOUT)
103
115
dBµV
108. Source current 1
IAGCfast
9.0
µA
109. Source current 2
IAGCslow
300
nA
110. Peak sink to ground IAGCpeak
100
µA
Data Sheet
38
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
#
Parameter1)
Symbol
Limit Values
min.
typ.
Unit Test Conditions
max.
111. RF AGC leakage
current
AGCLEAK
-50
50
nA
0 < VAGC < VCC
112. RF AGC output
voltage
VAGCmax
VCC0.25
VCC
V
maximum level
113.
VAGCmin
0
0.25 V
minimum level
114. RF voltage range to AGCSLIP
switch the AGC
from active to
inactive mode
■
0.5
dB
2
mA
RF AGC buffer output
115. RF AGC buffer
output current
Imax
116. Saturation voltage VSat_low
117. low
100
mV
Iload = 1mA
200
mV
Iload = 2mA
118. Saturation voltage VSat_high
119. high
100
mV
Iload = 1mA
mV
Iload = 2mA
AGCOFF
0
V
Power down
121. Voltage gain
Gmax
65
dB
VIFAGC ≥ 2.5 V
122.
Gmin
9
dB
VIFAGC ≤ 0.2 V
123. Maximum IF input
level
VIF/IF
102
dBµV min. gain,
fIF/IF = 36 MHz
(sine),
VIFAGC = 0.2 V,
VOUT/OUT = 1 Vpp
124. Minimum IF input
level
VIF/IF
46
max. gain,
fIF/IF = 36 MHz
(sine),
VIFAGC = 2.5 V,
VOUT/OUT = 1 Vpp
125. Input impedance
RIF/IF
2
kΩ
126.
CIF/IF
1.5
pF
120. RF AGC Buffer
output voltage
200
IF amplifier
Data Sheet
39
fIF/IF = 36 MHz,
parallel equivalent
circuit5)
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
#
Parameter1)
Symbol
Limit Values
min.
127. Low end cutoff
frequency
(-1 dB)
fL
128. High end cutoff
frequency
(-1 dB)
fH
typ.
Unit Test Conditions
max.
25
MHz VIF/IF = 60 dBµV,
RLOAD ≥ 5 kΩ,
CLOAD ≤ 1.5 pF,
MHz VOUT/OUT = 1 Vpp at
fIF/IF = 36 MHz
(sine)
65
129. Intermodulation
V1,V0 = 00 (5.0mA) C/IM3
V1,V0 = 01 (3.6mA) C/IM3
V1,V0 = 10 (2.1mA) C/IM3
-59
-58
-56
-50
-50
-50
dBc
dBc
dBc
130. Intermodulation
V1,V0 = 11 (1.1mA) C/IM3
-56
-50
dBc
fIF/IF1 = 37 MHz,
fIF/IF2 = 38 MHz,
VIF/IF1 = 90 dBµV,
VIF/IF2 = 90 dBµV
RLOAD=1 kΩ,
CLOAD = 10pF,
VOUT/OUT = 1 Vpp
fIF/IF1 = 37 MHz,
fIF/IF2 = 38 MHz,
VIF/IF1 = 90 dBµV,
VIF/IF2 = 90 dBµV
RLOAD ≥ 15 kΩ,
CLOAD = 1.5pF,
VOUT/OUT = 1 Vpp
131. Third order output OIP3
intercept point
V1,V0 = 00 (5.0mA)
133
dBµV fIF/IF1 = 37 MHz,
fIF/IF2 = 38 MHz,
VIF/IF1 = 90 dBµV,
VIF/IF2 = 90 dBµV
RLOAD = 1 kΩ,
CLOAD =10 pF,
VOUT/OUT = 1 Vpp
132. Signal to noise ratio SNR
43
dB
fIF/IF = 36 MHz
(sine),
VIF/IF = 60 dBµV,
VOUT/OUT = 1 Vpp,
BW = 8 MHz
133. Noise figure
10
dB
max. gain
134. Output impedance RIF/IF
90
Ω
135.
120
fOUT/OUT = 36 MHz,
series equivalent
circuit5)
Data Sheet
LIF/IF
40
■
150
nH
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
1) Values are referred to Figure 4.2 "Application circuit for hybrid application" on Page 27 and fIF = 36 MHz,
unless stated otherwise.
2) The RF frequency range is defined by the oscillator frequency range and the intermediate frequency (IF).
3) Local oscillator FM modulation resulting from I2C communication is measured at the IF output using a
modulation analyzer with a peak to peak detector ((P+ + P-) / 2) and a post detection filter 20 Hz - 100 kHz. The
I2C messages are sent to the tuner in such a way that the tuner is addressed but the content of the PLL registers
are not altered. The refresh interval between each data set shall be 20 ms to 1 s.
4) (N+5) -1 MHz is defined as the input level of channel N+5, at frequency 1 MHz lower, causing 100 kHz FM
sidebands 30 dB below the wanted carrier.
5) Impedance measured with differential 2-port measurement at input or output. Input and output pins directly
connected to measurement equipment with 50 Ω strip lines.
6) Limits are related to the tank circuit used in the application board. Frequency bands may be adjusted by the
choice of external components.
7) The supply ripple susceptibility is a sideband measurement using a spectrum analyzer connected to the IF
output. An unmodulated RF signal with a level of 80 dBµV is applied to the test board RF input. A sinewave
signal with a defined frequency is superposed onto the supply voltage (see Figure 16 "Ripple susceptibility
measurement" on Page 62). The specified value is the worst case in the frequency range.
8) This is the level of divider interferences close to the IF frequency. For example channel S3: fOSC = 158.15 MHz,
1/4 fOSC = 39.5375 MHz. The rejection has to be greater than 60 dB for an SAW driver output of 100 dBµV.
9) Crystal oscillator interference means the 4 MHz sidebands caused by the crystal oscillator. The rejection has
to be greater than 60 dB for an SAW driver output of 100 dBµV.
10) The reference frequency rejection is the level of reference frequency sidebands (e.g. 62.5 kHz) related to the
carrier. The rejection has to be greater than 60 dB for an SAW driver output of 100dBµV.
11) Channel S02 beat is the interfering product of fRFpix, fIF and fOSC of channel S02, fBEAT = 37.35 MHz. The possible
mechanisms are fOSC - 2 x fIF or 2 x fRFpix - fOSC.
5.2
Bus Interface
Table 7
Pin Function
Pin Designation
BUSMODE
SDA / Data
SCL / Clock
CAS / EN
Function
bus mode
select
serial data
clock
I2C: chip address
select, 3-W: enable
I2C mode
0
data in/out
clock in
3-Wire mode
1 or open
four chip addresses 1)
0: chip is addressed
1) see Table 8 Chip Address Organization in I2C Mode on page 42,
see Table 9 Address selection in I2C Mode on page 42
Data Sheet
41
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
Table 8
Chip Address Organization in I2C Mode
Name
Byte
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
ADB
1
1
0
0
0
MA1
MA0
R/W=0
ADB
1
1
0
0
0
MA1
MA0
R/W=1
Write Mode
Address Byte
Read Mode
Address Byte
Table 9
Address selection in I2C Mode
Chip Address (Hex)
Voltage at pin CAS/EN
MA1
MA0
Write Mode
Read Mode
(0 to 0.1) x VVCCD
0
0
C0
C1
open circuit or (0.2 to 0.3) x VVCCD
0
1
C2
C3
(0.4 to 0.6) x VVCCD
1
0
C4
C5
(0.9 to 1) x VVCCD
1
1
C6
C7
Table 10
Sub Addresses of Write Data Registers
Function
S6
S5
S4
S3
S2
S1
LSB
Main Divider (N)
00
0
0
0
0
0
0
0
0
Control bytes
01
0
0
0
0
0
0
0
1
Ref. Divider (R)
02
0
0
0
0
0
0
1
0
AGC control, IF signal
processing control
03
0
0
0
0
0
0
1
1
DC-DC converter
04
0
0
0
0
0
1
0
0
not used
05
0
0
0
0
0
1
0
1
Mode bytes, stand by,
test
06
0
0
0
0
0
1
1
0
Data Sheet
Hex MSB
42
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
Table 11
Sub Addresses of Read Data Registers
Function
Hex MSB
S6
S5
S4
S3
S2
S1
LSB
Status
80
1
0
0
0
0
0
0
0
Chip Code
8E
1
0
0
0
1
1
1
0
Revision Code
8F
1
0
0
0
1
1
1
1
5.3
Bus Data Format
Table 12
Bus Data Format
I2C-bus Write Mode I2C-bus Read Mode 3W-bus Write Mode 3W-bus Read Mode
Bit
Function
STA
1
MSB
1
0
0
Bit
1
chip address
(Write)
0
0
0
MA0
MA0
MA1
S4
S3
0
S7
Function
S7
MSB
S7
MSB
MSB
chip address
(Write)
LSB
MSB
S6
sub address
(Write)
00H...06H
S5
S4
S3
S2
S2
S1
S1
S0
Bit
ACK
MSB
S6
S5
Function
MA1
LSB
ACK
S7
Bit
1
0
0
Function
STA
LSB
Data Sheet
S0
S6
S5
sub address
(Read)
80H,
8EH, 8FH
S4
S3
LSB
sub address
(Write)
00H...06H
S5
S4
S3
S2
S2
S1
S1
S0
43
S6
LSB
S0
sub address
(Read)
80H
8EH, 8FH
LSB
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
I2C-bus Write Mode I2C-bus Read Mode 3W-bus Write Mode 3W-bus Read Mode
Bit
Function
ACK
Bit
Function
Bit
Function
Bit
Function
DX
MSB
DX
MSB
ACK
STA restart
DX
MSB
1
MSB
...
1
...
...
D5
0
D5
D5
D4
D3
data in X...0
(X=7,15 or
23) 1)
D2
D1
D0
0
chip address
(Read)
D4
0
D3
MA0
D2
MA1
LSB
1
ACK
ACK
STO
DX
1)
after each byte an
acknowledge is
generated by TUA
6045.
data in X...0
(X=7,15 or
23)
D0
data out X...0
(X=7 or 15)
D3
D2
D1
LSB
D4
D1
LSB
D0
LSB
MSB
...
D5
D4
data out X...0
(X=7 or 15) 2)
D3
2)
after each byte an
acknowledge is
generated by the
processor. TUA
6045 keeps data line
high.
D2
D1
D0
LSB
1
STO
STA: Start condition, STO: Stop condition, ACK: Acknowledge from TUA 6045.
Data Sheet
44
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
5.4
Bus Timing
BUSMODE = 0
tBUF
SDA
tLOW tR
tSP
tF
SCL
S tHD.STA
P
tHD.DAT
tHIGH
tSU.DAT
tHD.STA
S
tSU.STA
tSU.STO
P
S - START condition
P - STOP condition
Figure 7
I2C Bus
BUSMODE = 1
DATA
tLOW tR
tSP
tF
CLOCK
tWHEN
tHD.STA
tHD.DAT
tHIGH
tSU.DAT
tSU.STO
ENABLE
S
P
tSU.SCLENA
tSU.SCLENA
Figure 8
Data Sheet
3-Wire Bus
45
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
Table 13
Bus Timing
# Parameter
Symbol
Limit Values
Unit
min.
max.
1. LOW level input voltage
(SDA, SCL, CAS/EN, BUSMODE)
VIL
-0.5
0.54
V
2. HIGH level input voltage
(SDA, SCL, CAS/EN, BUSMODE)
VIH
1.26
5.5
V
3. Hysteresis of Schmitt trigger inputs
VHys
0.15
4. Pulse width of spikes
tSP
which must be suppressed by the input
filter
5. LOW level output voltage (SDA),
only I2C-bus
at 3mA sink current
at 6mA sink current
VOL
6. Output fall time from VIH min to VIL max with tOF
a bus capacitance from 10pF to 400pF
with up to 3mA sink current at VOL
V
0
50
ns
0
0.4
0.6
V
V
20+0.1Cb1)
250
ns
7. SCL clock frequency
fSCL
0
400
kHz
8. Bus free time between a STOP and
START condition 2)
tBUF
1.3
-
µs
9. Hold time (repeated) START/ENABLE tHD.STA
ON condition. After this period, the first
clock pulse is generated.
0.6
-
µs
10. LOW period of the SCL clock pulse
tLOW
1.3
-
µs
11. HIGH period of the SCL clock pulse
tHIGH
0.6
-
µs
12. Set-up time for a repeated START
condition 2)
tSU.STA
0.6
-
µs
13. Data hold time
tHD.DAT
0
-
ns
14. Data set-up time
tSU.DAT
100
-
ns
20+0.1Cb1)
300
ns
0.6
-
µs
15. Rise time, fall time of SDA and SCL
signals
tR, tF
16. Set-up time for STOP/ENABLE OFF
condition
tSU.STO
Data Sheet
46
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
# Parameter
17. Setup time CAS/EN to SDA
Symbol
3)
tSU.ENASD
Limit Values
Unit
min.
max.
0.6
-
µs
0.6
-
µs
0.6
-
µs
--
400
pF
A
18. Setup time SCL to CAS/EN
tSU.SCLEN
A
19. H-pulse width (CAS/EN) for new data
protocol 3)
tWHEN
20. Capacitive load for each bus line
Cb
1) Cb = capacitance of one bus line in pF.
Note that the maximum tF for the SDA and SCL bus lines quoted in table above (300ns) is longer than the
specified maximum tOF for the output stages (250ns).This allows series protection resistors to be connected
between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tF.
2) only for I2C bus mode.
3) only for 3-Wire bus mode.
Data Sheet
47
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
5.5
Data Byte Specification, Function and Defaults
5.5.1
Write Data Registers
Table 14
Bit Symbol
15 N15
Subaddress 00H, Main Divider
Bits
V
2
15
14
Function
Description
Synthesizer
N-counter
programmable
divider bits:
Defaults
0
14 N14
2
13 N13
213
12 N12
2
12
11 N11
2
11
10 N10
210
9 N9
29
8 N8
28
7 N7
27
6 N6
26
5 N5
25
1
4 N4
4
0
3
0
3 N3
2 N2
1 N1
0 N0
2
0
0
1
1
15
N = 2 x N15
+ ... + N0
N = 240 ... 65535
2
22 (internal
A-counter
21 A = 0 ... 15))
20
Default
1 divider
1 ratio
0
N=
1
79061)
1
0
1
0
1) Default: fRF = 458MHz with fref = 62.5kHz, f IF = 36.125MHz.
Data Sheet
48
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
Table 15
Subaddress 01H, Control Bytes
Bit Symbol
Bits
15
P2_4 ... P2_0
V
Function
Description
not used
not used
Defaults
0
analog output
14 P2_4
00000
0V to 0V
1
13 P2_3
11011
2.7 to 2.7V
V
1
12 P2_2
111X1
on (Vcc)
standard port
function
1
11 P2_1
11110
off (50k to GND) standard port
function
1
10 P2_0
11100
off (switch to
GND)
1
9 P1
0
Portswitch
Port 1 current off
Portswitch
Port 0 current off
1
8 P0
0
Port 1 current on
1
7 BS1
6 BS0
BS1 BS0
0
1
Osc. 1 + Mix 1 on LOW
1
0
Osc. 2 + Mix 2 on MID
1
1
Osc. 3 + Mix 2 on MID, HIGH Osc.
/3
0
Synth. charge600 µA
pump current
300 µA
CP=CP0+CP1+C
150 µA
P2+CP3
75 µA
2 CP0
Data Sheet
BS1 BS0
Osc. 3 + Mix 3 on HIGH
3 CP1
0 ABL0
Band switch
selection
0
4 CP2
1 ABL1
0
Port 0 current on
0
5 CP3
0
ABL ABL
1
0
Anti-Backlash
pulse width of
phase detector
PD
0
0
1
1
0
4.4 ns
1
1
5.6 ns
49
0
0
1
0
Pulse width
0
0
ABL ABL
1
0
2.2 ns
3.2 ns
0
1
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
Table 16
Subaddress 02H, Reference Divider R and Crystal Oscillator Control
Bit Symbol
Function
Description
15
not used
not used
14 RFAGC
B_OFF
RF AGC buffer off disable RF AGC
buffer
13 XTAL3
12 XTAL2
11 XTAL1
10 XTAL0
Data Sheet
Bits
XTA XTA
L3 L2
V
0
XTAL I/O control
0
output off, input
on
0
1
output 200 mVpp
1
0
output 400 mVpp
1
1
output 800 mVpp
0
0
0
1
XTAL I/O control
output mode
XTAL3 OR
Fout/1
XTAL2 =1
Fout/2
1
0
Fout/4
1
1
Fout/8
XTA XTA
L1 L0
1
1
XTA XTA
L1 L0
0
XTAL I/O control
input mode
XTAL3=0
XTAL_IN
XTAL2=0
XTAL_IN
0
0
0
1
1
0
XTAL_Buff
1
1
XTAL_Buff+Amp
50
0
XTA XTA
L3 L2
0
XTA XTA
L1 L0
Defaults
0
XTA XTA
L1 L0
0
0
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
Bit Symbol
9 R9
Bits
V
2
9
8
8 R8
2
7 R7
27
6 R6
6
2
Function
Description
Synthesizer
R-counter
Synthesizer
R-counter
programmable
divider bits:
9
R= 2 x R9
+ ... + R0
Defaults
0
0
0
1 Default
div. ratio
0
5 R5
25
4 R4
2
4
3 R3
2
3
2 R2
22
1 R1
2
1
0
2
0
0
0 R0
Data Sheet
0 R=64
0
R = 2 ... 1023
51
0
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
Table 17
Subaddress 03H, AGC control and IF Signal Processing Control
Bit Symbol
Bits
15 SW
0
14 LP
13 V1
12 V0
V
V1
Function
IF Switch
Description
Defaults
normal mode
0
1
bypass mixer
output tank
0
Loop thru control normal mode
1
bypass SAW
driver stage
V0
VGA output
power control
quiescent current V1
of emitter follower
per side
0
0
5.0 mA
0
1
3.6 mA
1
0
2.1 mA
1
1
11 S1
S1
S0
10 S0
0
0
9.7 mA
0
1
6.7 mA
1
0
4.7 mA
1
1
2.1 mA
9 ATC
1.1 mA
1
0
1
7 AL2
6 AL1
Data Sheet
AL2 AL1 AL0
0
0
1
SAW driver power quiescent current S1
control
for SAW driver
stage per side
0
8 PU
0
1
RF-AGC time
constant bit
0.3 µA
RF-AGC time
standby mode if
RF-AGC in
standby (Bit6 in
register 06H is
set)
tristate
NB-AGC control
NB-AGC take
over point
0
V0
1
S0
1
0
9.0 µA
0
200 kΩ pull-up
AL2 AL1 AL0
don’t use
52
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
Bit Symbol
5 AL0
Bits
V
Function
0
0
1
115 dBµV
0
1
0
112 dBµV
(default)
0
1
1
don’t use
1
0
0
109 dBµV
1
0
1
106 dBµV
1
1
0
103 dBµV
1
1
1
4 NBE
3 WBE
Disable NB-AGC Narrowband level
detector
detector active
1
Narrowband level
detector does not
affect AGC
0
0
1
0
0
Disable WB-AGC Wideband level
detector
detector active
0
Wideband level
detector does not
affect AGC
WB WB WB
2
1
0
WB-AGC control LOW/MID/HIGH
take over point
1 WB1
0
0
0
87 / 77 / 77 dBµV
0 WB0
0
0
1
90 / 80 / 80 dBµV
0
1
0
93 / 83 / 83 dBµV
0
1
1
96 / 86 / 86 dBµV
1
0
0
99 / 89 / 89 dBµV
1
0
1
don’t use
1
1
0
don’t use
1
1
1
don’t use
Data Sheet
Defaults
don’t use
0
1
2 WB2
Description
53
WB WB WB
2
1
0
0
1
0
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
Table 18
Bit Symbol
15
Subaddress 04H, DC-DC Converter
Bits
V
1
Function
Output HIGH
14 DCh_6
26
13 DCh_5
5
2
12 DCh_4
24
11 DCh_3
3
2
2
Description
High current or
tristate
Output high time:
High count register
DCh=sum(DCh_i
*2i); 2i =1 to 127
tHigh = DCh / fCrystal
Defaults
0
0
0
0
0
10 DCh_2
2
9 DCh_1
21
0
8 DCh_0
0
0
7
2
1
Output LOW
6 DCl_6
26
5 DCl_5
5
2
4 DCl_4
24
3 DCl_3
3
2
2
If bit15 = 0, load
count registers;
Output low time:
Low count register
DCh=sum(DCl_i
*2i); 2i =1 to 127
tLow = DCl / fCrystal
1
0
0
0
1
0
2 DCl_2
2
1 DCl_1
21
0
0 DCl_0
0
0
2
0
Default fDCDC = 4 MHz / (4 +16) = 200 kHz, 20% duty cycle
Data Sheet
54
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
Table 19
Bit Symbol
15 CPT
14 CPP
13 PT
Subaddress 06H, Mode Bytes, Test Mode and Standby Control
Bits
0
V
Function
Charge pump test CP is in normal
mode control
mode (=bipolar)
1
CP current sink or
source
(=monopolar)
0
CP = sinking
current if CPT=1
1
CP = sourcing
current if CPT=1
0
Ports test mode
control
1
12 PTSEL
Description
0
Ports in normal
mode (=bits P0,
P1 to ports)
Defaults
0
0
0
Ports in test mode
(=RFAGC
Detector or fPD/2)
Ports test output RFAGC_WB,
select
RFAGC_NB to
P0, P1 if PT=1
1
0
fPD/2 to P0, P1 if
PT=11)
11
not used
not used
10
not used
not used
9 STBY9
1
Standby for:
Integrator
1
8 STBY8
1
Standby for:
IFAGC
1
7 STBY7
1
Standby for:
SAW driver
1
6 STBY6
1
Standby for:
Mixer + RFAGC
1
5 STBY5
1
Standby for:
Ports
1
4 STBY4
1
Standby for:
PLL (and Rfosc/3)
1
3 STBY3
1
Standby for:
RF oscillator
1
2 STBY2
1
Standby for:
DCDC converter
1
Data Sheet
55
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
Bit Symbol
Bits
1 STBY1
0 STBY0
V
Function
Description
Defaults
1
Standby for:
Crystal oscillator
0
1
Standby for:
BIAS (disables all
except bus)
0
1) P0, P1 are outputs for fref, fdiv.
P0 is output for fref divided by 2. P1 is output for fdiv divided by 2.
5.5.2
Read Data Registers
Table 20
Bit Symbol
7 POF
Subaddress 80H, Status
Bits
V
Function
Description
Power-on flag
=1 after power-on. Reset after first read of
register
6 LF
Lock-in flag
=1 if lock-in
5
not used
4 RFAGC
RFAGC flag
=1 if RFAGC is active (< 3V)
3 RFAGC
_NB
NB detector flag
=1 if NB detector is above
threshold
=0 if NB detector is below
threshold
2 RFAGC
_WB
WB detector flag =1 if WB detector is above
threshold
=0 if WB detector is below
threshold
1 P1
Port P1 input
=1 if P1 is high
0 P0
Port P0 input
=1 if P0 is high
Data Sheet
56
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
Table 21
Bit Symbol
Subaddress 8EH, Chip Code “6045”
Bits
V
Function
Description
Defaults
15 CC15
2
15
0
14 CC14
214
0
13 CC13
2
13
0
12 CC12
212
1
11 CC11
2
11
0
10 CC10
2
10
1
9 CC9
29
8 CC8
2
8
7 CC7
2
7
6 CC6
26
5 CC5
2
5
4 CC4
24
1
3 CC3
2
3
1
2 CC2
2
2
1
1 CC1
21
0
0 CC0
0
1
Data Sheet
2
1
Chip Code
(binary coded)
57
CC = 215 x CC15 +
214 x CC14
+ ... +
21 x CC1 + 20 x
CC0
1
1
0
0
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
Table 22
Bit Symbol
Subaddress 8FH, Revision Code, advanced with design steps
Bits
V
Function
Description
Defaults
15 RC15
14 RC14
13 RC13
12 RC12
first digit
11 RC11
10 RC10
9 RC9
8 RC8
7 RC7
Revision Code
(ASCII coded)
depends on
design step
6 RC6
5 RC5
4 RC4
second digit
3 RC3
2 RC2
1 RC1
0 RC0
Data Sheet
58
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
5.6
Measurement Circuits
5.6.1
Gain (GV) measurement in LOW band
LOWIN SAWOUT
50 Ω
Vmeas
50 Ω
V
RMS
Voltmeter
Vi
Device
under
Test
Transformer
N1
V0
N2
C
50 Ω
spectrum
analyser
V'meas
SAWOUT
N1 : N2 = 10 : 2 turns
Figure 9
•
•
•
•
Gain (GV) measurement in LOW band
Zi >> 50 Ω => Vi = 2 x Vmeas = 80 dBµV
Vi = Vmeas + 6dB = 80 dBµV
V0 = V’meas + 17 dB (transformer ratio N1:N2 and transformer loss)
Gv = 20 log(V0 / Vi)
5.6.2
Gain (GV) measurement in MID and HIGH bands
MIDIN
SAWOUT
HIGHIN
50 Ω
Vmeas
RMS
Voltmeter
V
50 Ω
Vi
Balun
1:1
Device
under
Test
Transformer
N1
N2
V0
C
V'meas
MIDIN
SAWOUT
HIGHIN
50 Ω
spectrum
analyser
N1 : N2 = 10 : 2 turns
Figure 10
•
•
•
Gain (GV) measurement in MID and HIGH bands
Vi = Vmeas = 70 dBµV
V0 = V’meas + 17 dB (transformer ratio N1:N2 and transformer loss
Gv = 20 log(V0 / Vi) + 1 dB (1 dB = insertion loss of balun)
Data Sheet
59
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
5.6.3
Matching circuit for optimum noise figure in LOW band
15p
22p
1n
1n
In
In
Out
Out
7 turns
wire Ε 0.5 mm
coil Ε 5.5 mm
22p
50 Ω semi rigid cable
300 mm long
96 pF/m
33dB/100m
22p
For fRF = 50 MHz
For fRF = 150 MHz
loss = 0 dB
loss = 1.3 dB
image suppression = 16 dB
image suppression = 13 dB
Figure 11
5.6.4
Matching circuit for optimum noise figure in LOW band
Noise figure (NF) measurement in LOW band
Noise
Source
IN
OUT
Matching
Circuit
LOWIN SAWOUT
Transformer
Device
under
Test
N1
N2
Noise
Figure
Meter
C
SAWOUT
N1 : N2 = 10 : 2 turns
NF = NFmeas - loss of matching circuit (dB)
Figure 12
Data Sheet
Noise figure (NF) measurement in LOW band
60
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
5.6.5
Noise figure (NF) measurement in MID and HIGH bands
Noise
Source
MIDIN
SAWOUT
HIGHIN
Balun
1:1
Noise
Figure
Meter
Transformer
Device
under
Test
N1
N2
C
MIDIN
SAWOUT
HIGHIN
N1 : N2 = 10 : 2 turns
loss of balun = 1 dB
NF = NFmeas - loss of balun (dB)
Figure 13
5.6.6
Noise figure (NF) measurement in MID and HIGH bands
Cross modulation measurement in LOW band
V'meas
unwanted
signal source
AM = 80%, 1 kHz
A
50 Ω
C
Hybrid
50 Ω
B
wanted
signal
source
Figure 14
•
•
•
50 Ω
V
RMS
Voltmeter
D
LOWIN SAWOUT
Device
under
Test
Transformer
N1
N2
Vo
IF filter
C
50 Ω
modulation
analyser
SAWOUT
N1 : N2 = 10 : 2 turns
50 Ω
Cross modulation measurement in LOW band
V’meas = V0 - 17 dB (transformer ratio N1:N2 and transformer loss)
wanted output signal at fpix, Vo = 100 dBµV
unwanted output signal at fsnd
Data Sheet
61
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Reference
5.6.7
Cross modulation measurement in MID and HIGH bands
V'meas
unwanted
signal source
AM = 80%, 1 kHz
A
50 Ω
MIDIN
SAWOUT
HIGHIN
C
Balun
1:1
Hybrid
50 Ω
B
wanted
signal
source
Figure 15
•
•
•
V
50 Ω
RMS
Voltmeter
Device
under
Test
Transformer
N1
N2
IF filter
Vo
C
MIDIN
SAWOUT
HIGHIN
D
50 Ω
modulation
analyser
N1 : N2 = 10 : 2 turns
50 Ω
Cross modulation measurement in MID and HIGH bands
V’meas = V0 - 17 dB (transformer ratio N1:N2 and transformer loss)
wanted output signal at fpix, Vo = 100 dBµV
unwanted output signal at fsnd
5.6.8
Ripple susceptibility measurement
IC supply
240
Stabilizer
DC Supply
5k
1u
1u
Ripple
50
Figure 16
Data Sheet
2* 22uF
Ripple susceptibility measurement
62
Revision 3.1, 2006-12-19
TUA 6045-2
TAIFUN 3
Package PG-VQFN-48
6
Package PG-VQFN-48
Figure 17
PG-VQFN-48 Vignette
Figure 18
PG-VQFN-48 Outline Drawing
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
63
Revision 3.1, 2006-12-19
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG