LTC4257-1 - IEEE 802.3af PD Power over Ethernet Interface Controller with Dual Current Limit

LTC4257-1
IEEE 802.3af PD
Power over Ethernet Interface
Controller with Dual Current Limit
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FEATURES
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DESCRIPTIO
Complete Power Interface Port for IEEE 802®.3af
Powered Devices (PDs)
Onboard 100V, 400mA Power MOSFET
Precision Dual Level Current Limit
Onboard 25k Signature Resistor with Disable
Programmable Classification Current (Class 0-4)
Undervoltage Lockout
Thermal Overload Protection
Power Good Signal
Available in 8-Pin SO and Low Profile (3mm × 3mm)
DFN Packages
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APPLICATIO S
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IP Phone Power Management
Wireless Access Points
Telecom Power Control
The LTC®4257-1 provides complete signature and power
interface functions for a device operating in an IEEE
802.3af Power over Ethernet (PoE) system. The LTC4257-1
simplifies Powered Device (PD) design by incorporating
the 25k signature resistor, classification current source,
input current limit, undervoltage lockout, thermal overload protection, signature disable and power good signalling, all in a single 8-pin package. The LTC4257-1 includes
a precision, dual level current limit circuit. This allows it to
charge large load capacitors and interface with legacy
Power over Ethernet systems while maintaining compatibility with the current IEEE 802.3af specification. By
incorporating a high voltage power MOSFET onboard, the
LTC4257-1 provides the system designer with reduced
cost while also saving board space.
The LTC4257-1 can interface directly with a variety of Linear Technology DC/DC converter products to provide a cost
effective power solution for IP phones, wireless access
points and other PDs. Linear Technology also provides
network power controllers for Power Sourcing Equipment
(PSE) applications.
The LTC4257-1 is available in the 8-pin SO and low profile
(3mm × 3mm) DFN packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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TYPICAL APPLICATIO
Powered Device (PD)
~
–48V FROM
POWER SOURCING
EQUIPMENT
(PSE)
+
DF01SA
~
–
LTC4257-1
GND
SMAJ58A
RCLASS SIGDISA
0.1µF
PWRGD
RCLASS
5µF
MIN
100k
+
VIN
SWITCHING
POWER SUPPLY
SHDN
RTN
VIN
VOUT
+
3.3V
TO LOGIC
42571 TA01
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LTC4257-1
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ABSOLUTE
RATI GS
(Notes 1, 2)
VIN Voltage ............................................. 0.3V to – 100V
VOUT, SIGDISA,
PWRGD Voltage ...................... VIN + 100V to VIN – 0.3V
RCLASS Voltage ............................ VIN + 7V to VIN – 0.3V
PWRGD Current .................................................. 10mA
RCLASS Current .................................................. 100mA
Operating Ambient Temperature Range
LTC4257C-1 ............................................ 0°C to 70°C
LTC4257I-1 ......................................... –40°C to 85°C
Storage Temperature Range
S8 Package ....................................... – 65°C to 150°C
DD Package ...................................... – 65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
NC 1
8
GND
NC
1
8
GND
RCLASS 2
7
SIGDISA
RCLASS
2
7
SIGDISA
NC 3
6
PWRGD
NC
3
6
PWRGD
VIN
4
5
VOUT
VIN 4
5
VOUT
S8 PACKAGE
8-LEAD PLASTIC SO
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 150°C/W
ORDER PART NUMBER
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD TO BE SOLDERED TO ELECTRICALLY ISOLATED PCB HEATSINK
S8 PART MARKING
LTC4257CS8-1
LTC4257IS8-1
42571
4257I1
ORDER PART NUMBER
DD PART MARKING*
LTC4257CDD-1
LTC4257IDD-1
LBFZ
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF
Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grades are identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIN
Supply Voltage
Maximum Operating Voltage
Signature Range
Classification Range
UVLO Turn-On Voltage
UVLO Turn-Off Voltage
Voltage with Respect to GND Pin (Notes 4, 5, 6)
IIN_ON
IC Supply Current when ON
VIN = – 48V, Pins 5, 6, 7 Floating
IIN_CLASS
IC Supply Current During Classification VIN = – 17.5V, Pins 2, 7 Floating, VOUT Tied to GND
(Note 7)
●
∆ICLASS
Current Accuracy During Classification 10mA < ICLASS < 40mA, – 12.5V ≤ VIN ≤ – 21V,
(Notes 8, 9)
●
RSIGNATURE
Signature Resistance
–1.5V ≤ VIN ≤ –9.5V, VOUT Tied to GND,
IEEE 802.3af 2-Point Measurement (Notes 4, 5)
●
RINVALID
Invalid Signature Resistance
– 1.5V ≤ VIN ≤ – 9.5V, SIGDISA and VOUT
Tied to GND, IEEE 802.3af 2-Point Measurement
(Notes 4, 5)
●
●
●
●
●
●
– 1.5
– 12.5
– 34.8
– 29.3
TYP
MAX
UNITS
–36.0
–30.5
– 57
– 9.5
– 21
– 37.2
– 31.5
V
V
V
V
V
●
0.35
0.50
23.25
9
3
mA
0.65
mA
±3.5
%
26.00
kΩ
11.8
kΩ
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LTC4257-1
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VIH
Signature Disable
High Level Input Voltage
With Respect to VIN,
High Level Invalidates Signature (Note 10)
●
Signature Disable
Low Level Input Voltage
With Respect to VIN,
Low Level Enables Signature
●
RINPUT
Signature Disable
Input Resistance
With Respect to VIN
VPG_OUT
Power Good Output Low Voltage
I = 1mA, VIN = – 48V, PWRGD Referenced to VIN
●
Power Good Trip Point
VIN = –48V, Voltage Between VIN and VOUT (Note 9)
VOUT Falling
VOUT Rising
●
●
VIL
VPG_THRES_FALL
VPG_THRES_RISE
MIN
●
TYP
3
MAX
57
V
0.45
V
100
1.3
2.7
UNITS
kΩ
1.5
3.0
0.5
V
1.7
3.3
V
V
1
µA
IPG_LEAK
Power Good Leakage
VIN = 0V, PWRGD FET Off, VPWRGD = 57V
●
RON
On-Resistance
I = 350mA, VIN = – 48V, Measured from VIN to VOUT
(Note 9)
●
1.6
2.0
Ω
Ω
150
µA
1.0
IOUT_LEAK
VOUT Leakage
VIN = 0V, Power MOSFET Off, VOUT = 57V (Note 11)
●
ILIMIT_HIGH
Input Current Limit, High Level
VIN = – 48V, VOUT = –43V (Notes 12, 13)
0°C ≤ TA ≤ 70°C
–40°C ≤ TA ≤ 85°C
●
●
350
340
375
375
400
400
mA
mA
●
100
140
180
mA
ILIMIT_LOW
Input Current Limit, Low Level
VIN = – 48V, VOUT = –43V (Notes 12, 13)
TSHUTDOWN
Thermal Shutdown Trip Temperature
(Notes 12, 14)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages are with respect to GND pin unless otherwise noted.
Note 3: The LTC4257-1 operates with a negative supply voltage in the
range of –1.5V to –57V. To avoid confusion, voltages in this data sheet are
always referred to in terms of absolute magnitude. Terms such as
“maximum negative voltage” refer to the largest negative voltage and a
“rising negative voltage” refers to a voltage that is becoming more
negative.
Note 4: The LTC4257-1 is designed to work with two polarity protection
diode drops between the PSE and PD. Parameter ranges specified in the
Electrical Characteristics are with respect to LTC4257-1 pins and are
designed to meet IEEE 802.3af specifications when these diode drops are
included. See Applications Information.
Note 5: Signature resistance is measured via the 2-point ∆V/∆I method as
defined by IEEE 802.3af. The LTC4257-1 signature resistance is offset
from 25k to account for diode resistance. With two series diodes, the total
PD resistance will be between 23.75kΩ and 26.25kΩ and meet IEEE
802.3af specifications. The minimum probe voltages measured at the
LTC4257-1 pins are –1.5V and –2.5V. The maximum probe voltages are
–8.5V and –9.5V.
Note 6: The LTC4257-1 includes hysteresis in the UVLO voltages to
preclude any start-up oscillation. Per IEEE 802.3af requirements, the
LTC4257-1 will power up from a voltage source with 20Ω series
resistance on the first trial.
Note 7: IIN_CLASS does not include classification current programmed at
Pin 2. Total supply current in classification mode will be IIN_CLASS + ICLASS
(see Note 8).
140
°C
Note 8: ICLASS is the measured current flowing through RCLASS.
∆ICLASS accuracy is with respect to the ideal current defined as
ICLASS = 1.237/RCLASS. The current accuracy specification does not
include variations in RCLASS resistance. The total classification current for
a PD also includes the IC quiescent current (IIN_CLASS). See Applications
Information.
Note 9: For the DD package, this parameter is assured by design and
wafer level testing.
Note 10: To disable the 25k signature, tie SIGDISA to GND (±0.1V) or hold
SIGDISA high with respect to VIN. See Applications Information.
Note 11: IOUT_LEAK includes current drawn at the VOUT pin by the power
good status circuit. This current is compensated for in the 25kΩ signature
resistance and does not affect PD operation.
Note 12: The LTC4257-1 includes thermal protection. In the event of an
overtemperature condition, the LTC4257-1 will turn off the power MOSFET
until the part cools below the overtemperature limit. The LTC4257-1 is
also protected against thermal damage from incorrect classification
probing by the PSE. If the LTC4257-1 exceeds the overtemperature trip
point, the classification load current is disabled.
Note 13: The LTC4257-1 includes dual level input current limit. At turn-on,
before C1 is charged, the LTC4257-1 current level is set to the low level.
After C1 is charged and the VOUT – VIN voltage difference is below the
power good threshold, the LTC4257-1 switches to high level current limit.
The LTC4257-1 stays in high level current limit until the input voltage
drops below the UVLO turn-off threshold.
Note 14: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
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LTC4257-1
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TYPICAL PERFOR A CE CHARACTERISTICS
Input Current vs Input Voltage
25k Detection Range
0.5
Input Current vs Input Voltage
50
TA = 25°C
Input Current vs Input Voltage
12.0
TA = 25°C
CLASS 4
11.5
0.3
0.2
INPUT CURRENT (mA)
40
INPUT CURRENT (mA)
INPUT CURRENT (mA)
0.4
CLASS 1 OPERATION
CLASS 3
30
CLASS 2
20
CLASS 1
0.1
10
11.0
85°C
10.5
–40°C
10.0
9.5
CLASS 0
0
–2
–4
–6
INPUT VOLTAGE (V)
–8
0
–10
0
–20
–30
–40
INPUT VOLTAGE (V)
–10
4357 G01
–50
–45
–55
INPUT VOLTAGE (V)
–60
26
LTC4257-1 + 2 DIODES
25
24
LTC4257-1 ONLY
IEEE LOWER LIMIT
23
22
V1: –1
V2: –2
–3
–4
–7
–5
–8
–6
INPUT VOLTAGE (V)
42571 G04
1
0
–1
–2
–40
–9
–10
–20
60
0
20
40
TEMPERATURE (°C)
Current Limit vs Input Voltage
400
VIN = 0V
TA = 25°C
TA = 25°C
85°C
–40°C
VOUT CURRENT (µA)
VPG_OUT (V)
2
CURRENT LIMIT (mA)
90
3
60
30
1
80
42571 G06
VOUT Leakage Current
120
–22
APPLICABLE TO TURN-ON
AND TURN-0FF THRESHOLDS
42571 G05
Power Good Output Low Voltage
vs Current
4
2
RESISTANCE = ∆V = V2 – V1
∆I I2 – I1
27 DIODES: S1B
TA = 25°C
IEEE UPPER LIMIT
SIGNATURE RESISTANCE (kΩ)
INPUT CURRENT (mA)
1
–20
–18
–16
INPUT VOLTAGE (V)
Normalized UVLO Threshold
vs Temperature
28
2
–14
42571 G03
Signature Resistance
vs Input Voltage
EXCLUDES ANY LOAD CURRENT
TA = 25°C
0
–40
9.0
–12
–60
42571 G02
Input Current vs Input Voltage
3
–50
NORMALIZED UVLO THRESHOLD (%)
0
HIGH CURRENT MODE
300
200
85°C
LOW CURRENT MODE
–40°C
0
0
0
2
6
4
CURRENT (mA)
8
10
42571 G07
0
20
40
VOUT PIN VOLTAGE (V)
60
42571 G08
100
–40
–50
–45
–55
INPUT VOLTAGE (V)
–60
42571 G09
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LTC4257-1
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PI FU CTIO S
NC (Pin 1): No Internal Connection.
RCLASS (Pin 2): Class Select Input. Used to set the current
value the LTC4257-1 maintains during classification. Connect a resistor between RCLASS and VIN (see Table 2).
NC (Pin 3): No Internal Connection.
VIN (Pin 4): Power Input. Tie to system – 48V through the
input diode bridge.
VOUT (Pin 5): Power Output. Supplies – 48V to the PD load
through an internal power MOSFET that limits input current. VOUT is high impedance until the input voltage rises
above the turn-on UVLO threshold. The output is then
current limited. See Applications Information.
PWRGD (Pin 6): Power Good Output, Open-Drain. Signals
to the PD load that the LTC4257-1 MOSFET is on and that
the PD’s DC/DC converter can start operation. Low impedance indicates power is good. PWRGD is high impedance
during detection, classification and in the event of a
thermal overload. PWRGD is referenced to VIN.
SIGDISA (Pin 7): Signature Disable Input. Allows the PD
to command the LTC4257-1 to present an invalid signature resistance and to remain inactive. Connecting SIGDISA
to GND lowers the signature resistance to an invalid value
and disables all functions of the LTC4257-1. If left floating,
SIGDISA is internally pulled to VIN. If unused, tie SIGDISA
to VIN.
GND (Pin 8): Ground. Tied to system ground and power
return through the input diode bridge.
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BLOCK DIAGRA
CLASSIFICATION
CURRENT LOAD
NC 1
1.237V
+
–
GND
7
SIGDISA
6
PWRGD
9k
25k SIGNATURE
RESISTOR
EN
SIGNATURE DISABLE
16k
RCLASS 2
POWER GOOD
NC 3
8
CONTROL
CIRCUITS
375mA
+
EN
INPUT
CURRENT
LIMIT
140mA
–
0.3Ω
VIN 4
5 VOUT
BOLD LINE INDICATES HIGH CURRENT PATH
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LTC4257-1
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APPLICATIO S I FOR ATIO
The LTC4257-1 is intended for use as the front end of a
Powered Device (PD) adhering to the IEEE 802.3af standard.
The LTC4257-1 includes a trimmed 25k signature resistor,
classification current source, and an input current limit circuit. With these functions integrated into the LTC4257-1,
the signature and power interface for a PD that meets all
the requirements of the IEEE 802.3af specification can be
built with a minimum of external components.
DETECTION V1
VIN (V)
10
20
50
TIME
τ = RLOAD C1
10
VOUT (V)
UVLO
OFF
20
30
The LTC4257-1 has several modes of operation depending on the applied input voltage as shown in Figure 1 and
UVLO
ON
UVLO
OFF
dV = ILIMIT
C1
dt
40
50
TIME
PWRGD (V)
10
POWER
BAD
20
POWER
GOOD
POWER
BAD
30
40
PWRGD TRACKS
VIN
50
CURRENT
LIMIT, ILIMIT
PD CURRENT
ILIMIT
LOAD, ILOAD
ICLASS
CLASSIFICATION
ICLASS
DETECTION I2
DETECTION I1
V1 – 2 DIODE DROPS
I1 =
25kΩ
V2 – 2 DIODE DROPS
25kΩ
ICLASS DEPENDENT ON RCLASS SELECTION
I2 =
ILIMIT = 140mA (NOMINAL)
ILOAD =
VIN
RLOAD
GND
IIN
PSE
VIN
2
RCLASS GND
8
LTC4257-1
RCLASS
PWRGD
4
Operation
UVLO
TURN-OFF
UVLO
TURN-ON
30
40
The LTC4257-1 has been specifically designed to interface
with legacy PoE PSEs which do not meet the inrush
current requirement of the IEEE 802.3af specification. By
setting the initial inrush current limit to a low level, a PD
using the LTC4257-1 minimizes the current drawn from
the PSE during start-up. After powering up, the LTC4257-1
switches to the high level current limit, thereby allowing
the PD to consume up to 12.95 watts if an 802.3af PSE is
present. This low level current limit also allows the
LTC4257-1 to charge arbitrarily large load capacitors
without exceeding the inrush limits of the IEEE 802.3af
specification. This dual level current limit provides the
system designer with flexibility to design PDs which are
compatible with legacy PSEs while also being able to take
advantage of the higher power allocation available in an
IEEE 802.3af system.
Using an LTC4257-1 for the power and signature interface functions of a PD provides several advantages. The
LTC4257-1 current limit circuit includes an onboard,
100V, 400mA power MOSFET with low leakage. This
onboard low leakage MOSFET avoids the possibility of
corrupting the 25k signature resistor while also saving
board space and cost. In addition, the inrush current limit
requirement of the IEEE 802.3af standard causes large
transient power dissipation in the PD. The LTC4257-1 is
designed to allow multiple turn-on sequences without
overheating the miniature 8-lead package. In the event of
excessive power cycling, the LTC4257-1 provides thermal overload protection to keep the onboard power
MOSFET within its safe operating area.
TIME
DETECTION V2
CLASSIFICATION
VIN
VOUT
6
R9
RLOAD
C1
VOUT
5
42571 F01
Figure 1. Output Voltage, PWRGD and PD Current
as a Function of Input Voltage
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LTC4257-1
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APPLICATIO S I FOR ATIO
summarized in Table 1. These various modes satisfy the
requirements defined in the IEEE 802.3af specification.
The input voltage is applied to the VIN pin and is with
reference to the GND pin. This input voltage is always
negative. To avoid confusion, voltages in this data sheet
are always referred to in terms of absolute magnitude.
Terms such as maximum negative voltage refer to the
largest negative voltage and a rising negative voltage
refers to a voltage that is becoming more negative. References to electrical parameters in this applications section
use the nominal value. Refer to the Electrical Characteristics section for the range of values a particular parameter
will have.
Table 1. LTC4257-1 Operational Mode
as a Function of Input Voltage
INPUT VOLTAGE
(VIN with RESPECT to GND)
0V to – 1.4V
Inactive
– 1.5V to – 10V
25k Signature Resistor Detection
– 11V to – 12.4V
Classification Load Current Ramps up from
0% to 100%
– 12.5V to UVLO*
Classification Load Current Active
UVLO* to –57V
Power Applied to PD Load
*UVLO includes hysteresis.
Rising input threshold ≅ – 36.0V
Falling input threshold ≅ – 30.5V
1
2
3
POWERED DEVICE (PD)
INTERFACE
AS DEFINED
BY IEEE 802.3af
6
TX +
During detection, the PSE will apply a voltage in the range
of –2.8V to –10V on the cable and look for a 25k signature
resistor. This identifies the device at the end of the cable
as a PD. With the terminal voltage in this range, the
LTC4257-1 connects an internal 25k resistor between GND
and the VIN pins. This precision, temperature compensated
resistor presents the proper characteristics to alert the
Power Sourcing Equipment (PSE) at the other end of the
cable that a PD is present and desires power to be applied.
T1
TX –
RX +
The IEEE 802.3af defined operating modes for a PD
reference the input voltage at the RJ45 connector on the
PD. However, PD circuitry must include diode bridges
between the RJ45 connector and the LTC4257-1 (Figure
2). The LTC4257-1 takes this into account by compensating for these diode drops in the threshold points for each
range of operation. Since the voltage ranges specified in
the LTC4257-1 electrical specifications are with respect to
the IC pins, for both the signature and classification
ranges, the LTC4257-1 lower end extends two diode drops
below the IEEE 802.3af specification. A similar adjustment
is made for the UVLO voltages.
Detection
LTC4257-1 MODE OF OPERATION
RJ45
Series Diodes
BR1
TO PHY
RX –
GND
4
SPARE +
LTC4257-1
BR2
5
D3
4
7
8
8
SPARE –
VIN
42571 F02
Figure 2. PD Front End Using Diode Bridges On Main and Spare Inputs
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APPLICATIO S I FOR ATIO
The power applied to a PD is allowed to use either of two
polarities and the PD must be able to accept this power so
it is common to install a diode bridge on the input. The
LTC4257-1 is designed to compensate for the voltage and
resistance effects of these two series diodes. The signature range extends below the IEEE range to accommodate
the voltage drop of the diodes. The IEEE specification
requires the PSE to use a ∆V/∆I measurement technique
to keep the DC offset of these diodes from affecting the
signature resistance measurement. However, the diode
resistance appears in series with the signature resistor
and must be included in the overall signature resistance
of the PD. The LTC4257-1 compensates for the two series
diodes in the signature path by offsetting the resistance
so that a PD built using the LTC4257-1 will meet the IEEE
specification.
Classification
Once the PSE has detected a PD, the PSE may optionally
classify the PD. Classification provides a method for more
efficient allocation of power by allowing the PSE to identify
lower-power PDs and allocate less power for these devices. The IEEE 802.3af specification defines five classes
(Table 2) with varying power levels. The designer selects
the appropriate classification based on the power consumption of the PD. For each class, there is an associated
load current that the PD asserts onto the line during
classification probing. The PSE measures the PD load
current to determine the proper classification and PD
power requirements.
Table 2. Summary of IEEE 802.3af Power Classifications and
LTC4257-1 RCLASS Resistor Selection
MAXIMUM
NOMINAL
LTC4257-1
POWER LEVELS
CLASSIFICATION
RCLASS
AT INPUT OF PD
LOAD CURRENT RESISTOR
CLASS USAGE
(W)
(mA)
(Ω, 1%)
0
Default
0.44 to 12.95
<5
Open
1
Optional
0.44 to 3.84
10.5
124
2
Optional
3.84 to 6.49
18.5
68.1
3
Optional
6.49 to 12.95
28
45.3
4
Reserved
Reserved*
40
30.9
*Class 4 is currently reserved and should not be used.
In some applications it is necessary to control whether or
not the PD is detected. In this case, the 25k signature can
be enabled and disabled with the use of the SIGDISA pin
(Figure 3). Disabling the signature via the SIGDISA pin will
change the signature resistor to 9k which is an invalid signature per the IEEE 802.3af specification. This invalid
signature is present for PD input voltages from –2.8V to
–10V. If the input rises above –10V, the signature resistor reverts to 25k to minimize power dissipation in the
LTC4257-1. To disable the signature, tie SIGDISA to GND.
Alternately, the SIGDISA pin can be driven high with respect to VIN. When SIGDISA is high, all functions of the
LTC4257-1 are disabled.
Early revisions of the IEEE 802.3af draft specification
defined two methods that a PSE could use in order to
perform PD classification. These methods are known as
Measured Current and Measured Voltage. The IEEE has
since removed the Measured Voltage method from the
LTC4257-1
TO
PSE
GND 8
9k
25k SIGNATURE
RESISTOR
16k
SIGNATURE DISABLE
SIGDISA
7
4 VIN
42571 F03
Figure 3. 25k Signature Resistor with Disable
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APPLICATIO S I FOR ATIO
specification. The LTC4257-1 is compatible with the IEEE
802.3af standard and also works with the obsolete Measured Voltage method.
In the Measured Current method (Figure 4), the PSE
presents a fixed voltage between –15.5V and –20.5V to the
PD. With the input voltage in this range, the LTC4257-1
asserts a load current from the GND pin through the
RCLASS resistor. The magnitude of the load current is set
with the selection of the RCLASS resistor. The resistor value
associated with each class is shown in Table 2.
In the Measured Voltage method (Figure 5), the PSE drives
a current into the PD and monitors the voltage across the
PD terminals. The PSE current steps between classification load current values in order to classify the PD under
test. For PSE probe currents below the PD load current, the
LTC4257-1 will keep the PD terminal voltage below the
classification voltage range. For PSE probe currents above
the PD load current, the LTC4257-1 will force the PD
terminal voltage above the classification voltage range.
During classification, a moderate amount of power is
dissipated in the LTC4257-1. The IEEE 802.3af specification limits the classification time to 75ms. The LTC4257-1
is designed to handle the power dissipation for this time
period. If the PSE probing exceeds 75ms, the LTC4257-1
may overheat. In this situation, the thermal protection
circuit will engage and disable the classification current
source in order to protect the part. The LTC4257-1 stays
in classification mode until the input voltage rises above
the UVLO turn-on voltage.
CURRENT PATH
PSE
PROBING
VOLTAGE
SOURCE
–15.5V TO –20.5V
LTC4257-1
2 RCLASS
GND 8
RCLASS
4 VIN
42571 F04
V
CONSTANT
LOAD
CURRENT
INTERNAL
TO LTC4257-1
PSE CURRENT MONITOR
PD
PSE
Figure 4. IEEE 802.3af Measured-Current Method
of Classification Probing
CURRENT PATH
PSE
PROBING
CURRENT
SOURCE
PSE
LTC4257-1
V VOLTAGE
MONITOR
2 RCLASS
RCLASS
4 VIN
PSE
GND 8
CONSTANT
LOAD
CURRENT
INTERNAL
TO LTC4257-1
PD
IF PSE PROBING CURRENT < LTC4257-1 LOAD CURRENT, PD TERMINAL VOLTAGE IS < 15V
IF PSE PROBING CURRENT > LTC4257-1 LOAD CURRENT, PD TERMINAL VOLTAGE IS > 20V
42571 F05
Figure 5. IEEE 802.af Measured-Voltage Method
of Classification Probing
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Undervoltage Lockout
The IEEE specification dictates a maximum turn-on voltage of 42V and a minimum turn-off voltage of 30V for the
PD. In addition, the PD must maintain large on-off hysteresis to prevent resistive losses in the wiring between the
PSE and the PD from causing start-up oscillation. The
LTC4257-1 incorporates an undervoltage lockout (UVLO)
circuit that monitors line voltage to determine when to
apply power to the PD load (Figure 6). Before power is
applied to the load, the VOUT pin is high impedance and
sitting at ground potential since there is no charge on
capacitor C1. When the input voltage rises above the UVLO
turn-on threshold, the LTC4257-1 removes the classification load current and turns on the internal power MOSFET.
C1 charges up under LTC4257-1 current limit control and
the VOUT pin transitions from 0V to VIN. This sequence is
shown in Figure 1. The LTC4257-1 includes a hysteretic
UVLO circuit that keeps power applied to the load until the
input voltage falls below the UVLO turn-off threshold.
LTC4257-1
TO
PSE
Once the input voltage drops below –30V, the internal
power MOSFET is turned off and the classification load
current is re-enabled. C1 will discharge through the PD
circuitry and the VOUT pin will go to a high impedance state.
Input Current Limit
IEEE 802.3af specifies a maximum inrush current and also
specifies a minimum load capacitor between the GND and
VOUT pins. To control turn-on surge current in the system,
the LTC4257-1 integrates a dual level current limit circuit
with an onboard power MOSFET and sense resistor to
provide a complete inrush control circuit without additional
external components. At turn on, the LTC4257-1 will limit
input current to the low level, allowing the load capacitor
to ramp up to the line voltage in a controlled manner.
The LTC4257-1 has been specifically designed to interface
with legacy PSEs which do not meet the inrush current
requirement of the IEEE 802.3af specification. This is
GND 8
C1
5µF
MIN
+
PD
LOAD
UNDERVOLTAGE
LOCKOUT
CIRCUIT
4 VIN
VOUT 5
INPUT
LTC4257-1
VOLTAGE
POWER MOSFET
0V TO UVLO*
OFF
>UVLO*
ON
*UVLO INCLUDES HYSTERESIS
RISING INPUT THRESHOLD ≅ –36V
FALLING INPUT THRESHOLD ≅ –30.5V
42571 F06
CURRENT-LIMITED
TURN ON
Figure 6. LTC4257-1 Undervoltage Lockout
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accomplished by a dual level current limit. At turn on
before C1 is charged, the LTC4257-1 current limit is set to
the low level. After C1 is charged up and the VOUT – VIN
voltage difference is below the power good threshold, the
LTC4257-1 switches to the high level current limit. The
dual level current limit allows legacy PSEs with limited
current sourcing capability to power up the PD while also
allowing the PD to draw full power from an IEEE 802.3af
PSE.
threshold. This dual level current limit provides the system designer with the flexibility to design PDs which are
compatible with legacy PSEs while also being able to take
advantage of the higher power allocation available in an
IEEE 802.3af system.
During the current limited turn on, a large amount of power
is dissipated in the power MOSFET. The LTC4257-1 is
designed to accept this thermal load and is thermally
protected to avoid damage to the onboard power MOSFET.
Note that in order to adhere to the IEEE 802.3af standard,
it is necessary for the PD designer to ensure the PD steadystate power consumption falls within the limits shown in
Table 2.
The dual level current limit also allows use of arbitrarily
large load capacitors. The IEEE 802.3af specification mandates that at turn on the PD not exceed the inrush current
limit for more than 50ms. The LTC4257-1 is not restricted
by the 50ms time limit because the load capacitor is
charged with a current below the IEEE inrush current limit
specification. Therefore, it is possible to use larger load
capacitors with the LTC4257-1.
Power Good
The LTC4257-1 includes a power good circuit (Figure 7)
that is used to indicate to the PD circuitry that load
capacitor C1 is fully charged and that the PD can start
DC/DC converter operation. The power good circuit monitors the voltage across the internal power MOSFET and
PWRGD is asserted when the voltage drops below 1.5V.
The power good circuit includes a large amount of hysteresis to allow the LTC4257-1 to operate near the current
limit point without inadvertently disabling PWRGD. The
MOSFET voltage must increase to 3V before PWRGD is
disabled.
As the LTC4257-1 switches from the low to the high level
current limit, a momenatry increase in current can be
observed. This current spike is a result of the LTC4257-1
charging the last 1.5V at the high level current limit. When
charging a 10µF capacitor, the current spike is typically
100µs wide and 125% of the nominal low level current
limit.
The LTC4257-1 stays in the high level current limit mode
until the input voltage drops below the UVLO turn-off
LTC4257-1
PWRGD 6
R9
100k
SHDN
PD
LOAD
THERMAL SHUTDOWN
UVLO
–
TO
PSE
+
C1
5µF
MIN
+
–
1.125V
300k
4 VIN
+
300k
VOUT 5
42571 F07
Figure 7. LTC4257-1 Power Good
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If a sudden increase in voltage appears on the input line,
this voltage step will be transferred through capacitor C1
and appear across the power MOSFET. The response of
the LTC4257-1 will depend on the magnitude of the
voltage step, the rise time of the step, the value of capacitor
C1 and the DC load. For fast rising inputs, the LTC4257-1
will attempt to quickly charge capacitor C1 using an
internal secondary current limit circuit. In this scenario,
the PSE current limit should provide the overall limit for
the circuit. For slower rising inputs, the 375mA current
limit in the LTC4257-1 will set the charge rate of capacitor
C1. In either case, the PWRGD signal may go inactive
briefly while the capacitor is charged up to the new line
voltage. In the design of a PD, it is necessary to determine
if a step in the input voltage will cause the PWRGD signal
to go inactive and how to respond to this event. In some
designs, the charge on C1 is sufficient to power the PD
through this event. In this case, it may be desirable to filter
the PWRGD signal so that intermittent power bad conditions are ignored. Figure 10 demonstrates methods to
insert a lowpass filter on the power good interface.
For PD designs that use a large load capacitor and also
consume a lot of power, it is important to delay activation
of the PD circuitry with the PWRGD signal. If the PD circuitry is not disabled during the current-limited turn-on sequence, the PD circuitry will rob current intended for charging up the load capacitor and create a slow rising input,
possibly causing the LTC4257-1 to go into thermal shutdown.
The PWRGD pin connects to an internal open-drain, 100V
transistor capable of sinking 1mA. Low impedance indicates power is good. PWRGD is high impedance during
signature and classification probing and in the event of a
thermal overload.
During turn-off, PWRGD is deactivated when the input
voltage drops below 30V. In addition, PWRGD may go
active briefly at turn-on for fast rising input waveforms.
PWRGD is referenced to the VIN pin and when active will
be near the VIN potential. The PD DC/DC converter will
typically be referenced to VOUT and care must be taken to
ensure that the difference in potential of the PWRGD signal
does not cause any detrimental effects. Use of diode clamp
D6, as shown in Figure 10, will alleviate any problems.
Thermal Protection
The LTC4257-1 includes thermal overload protection in
order to provide full device functionality in a miniature
package while maintaining safe operating temperatures.
Several factors create the possibility for tremendous
power dissipation within the LTC4257-1. At turn on,
before the load capacitor has charged up, the instantaneous power dissipated by the LTC4257-1 can be 10W. As
the load capacitor charges up, the power dissipation in the
LTC4257-1 will decrease until it reaches a steady-state
value dependent on the DC load current. The size of the
load capacitor determines how fast the power dissipation
in the LTC4257-1 will subside. At room temperature, the
LTC4257-1 can handle load capacitors as large as 800µF
without going into thermal shutdown. With a large load
capacitor like this, the LTC4257-1 die temperature will
increase by about 50°C during a single turn-on sequence.
If for some reason power were removed from the part and
then quickly reapplied so that the LTC4257-1 has to
charge up the load capacitor again, the temperature
rise would be excessive if safety precautions were not
implemented.
The LTC4257-1 protects itself from thermal damage by
monitoring the die temperature. If the die temperature
exceeds the overtemperature trip point, the current is
reduced to zero and very little power is dissipated in the
part until it cools below the overtemperature set point.
Once the LTC4257-1 has charged up the load capacitor
and the PD is powered and running, there will be some
residual heating due to the DC load current of the PD
flowing through the internal MOSFET. In some applications, the LTC4257-1 power dissipation may be significant and if dissipated in the S8 package, excessive package heating could occur. This problem can be solved with
the use of the DD package which has superior thermal
performance. The DD package includes an exposed pad
which should be soldered to an isolated heatsink on the
printed circuit board.
During classification, excessive heating of the LTC4257-1
can occur if the PSE violates the 75ms probing time limit.
To protect the LTC4257-1, thermal protection circuitry will
disable classification current if the die temperature exceeds
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the overtemperature trip point. When the die cools down
below the trip point, classification current is enabled again.
If the PD is designed to operate at a high ambient temperature and with the maximum allowable supply (57V), there
will be a limit to the size load capacitor that can be charged
up before the LTC4257-1 reaches the overtemperature trip
point. Hitting the overtemperature trip point intermittently
does not harm the LTC4257-1, but it will delay completion
of capacitor charging. Capacitors up to 200µF can be
charged without a problem.
Table 3. Power over Ethernet Transformer Vendors
VENDOR
Pulse Engineering
CONTACT INFORMATION
12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
FAX: 858-674-8262
http://www.pulseeng.com/
206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
FAX: 201-432-9542
http://www.belfuse.com/
308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
FAX: 650-361-2508
http://www.circuitprotection.com/
Bel Fuse Inc.
Tyco Electronics
EXTERNAL INTERFACE AND COMPONENT SELECTION
Transformer
Nodes on an Ethernet network commonly interface to the
outside world via an isolation transformer (Figure 8). For
powered devices, the isolation transformer must include
a center tap on the media (cable) side. Proper termination
is required around the transformer to provide correct
impedance matching and to avoid radiated and conducted
emissions. Transformer vendors such as Pulse, Bel Fuse,
Tyco and others (Table 3) can provide assistance with
selection of an appropriate isolation transformer and
proper termination methods. These vendors have transformers specifically designed for use in PD applications.
RJ45
1
2
3
6
4
TX +
2
TX –
14
3
RX +
11
6
10
7
9
8
8
BR1
DF01SA
TO PHY
PULSE H2019
SPARE +
5
7
IEEE 802.3af allows power wiring in either of two configurations on the TX/RX wires, plus power can be applied to
the PD via the spare wire pair in the RJ45 connector. The
PD is required to accept power in either polarity on both
the main and spare inputs; therefore, it is common to
install diode bridges on both inputs in order to accommodate the different wiring configurations. Figure 8 demonstrates an implementation of these diode bridges. The
specification also mandates that the leakage back through
the unused bridge be less than 28µA when the PD is
powered with 57V.
16 T1 1
15
RX –
Diode Bridges
SPARE –
GND
BR2
DF01SA
C14
0.1µF
100V
8
C1
LTC4257-1
D3
SMAJ58A
TVS
4
VIN
VOUT
5
42571 F08
VOUT
Figure 8. PD Front End with Isolation Transformer, Diode Bridges and Capacitor
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The IEEE standard includes an AC impedance requirement
in order to implement the AC disconnect function. Capacitor C14 in Figure 8 is used to meet this AC impedance
requirement. A 0.1µF capacitor is recommended for this
application.
The LTC4257-1 has several different modes of operation
based on the voltage present between the VIN and GND pins.
The forward voltage drop of the input diodes in a PD design
subtracts from the input voltage and will affect the transition point between modes. When using the LTC4257-1, it
is necessary to pay close attention to this forward voltage
drop. Selection of oversized diodes will help keep the PD
thresholds from exceeding IEEE specifications.
The input diode bridge of a PD can consume over 4% of the
available power in some applications. It may be desirable
to use Schottky diodes in order to reduce this power loss.
However, if the standard diode bridge is replaced with a
Schottky bridge, the transition points between modes will
be affected. The application circuit (Figure 11) shows a technique for using Schottky diodes while maintaining proper
threshold points to meet IEEE 802.3af compliance.
Auxiliary Power Source
In some applications, it may be desirable to power the PD
from an auxiliary power source such as a wall transformer.
The auxiliary power can be injected into the PD at several
locations and various trade-offs exist. Power can be
injected at the 3.3V or 5V output of the isolated power
supply with the use of a diode ORing circuit. This method
accesses the internal circuits of the PD after the isolation
barrier and therefore meets the 802.3af isolation safety
requirements for the wall transformer jack on the PD.
Power can also be injected into the PD interface portion of
the LT4257-1. In this case, it is necessary to ensure the
user cannot access the terminals of the wall transformer
jack on the PD since this would compromise the 802.3af
isolation safety requirements. Figure 9 demonstrates three
methods of diode ORing external power into a PD. Option
1 inserts power before the LTC4257-1 while options 2 and
3 apply power after the LTC4257-1.
If power is inserted before the LTC4257-1 (option 1), it is
necessary for the wall transformer to exceed the LTC4257-1
UVLO turn-on requirement and limit the maximum voltage
to 57V. This option provides input current limit for the
transformer, provides a valid power good signal and
simplifies power priority issues. As long as the wall
transformer applies power to the PD before the PSE, it will
take priority and the PSE will not power up the PD because
the wall power will corrupt the 25k signature. If the PSE is
already powering the PD, the wall transformer power will
be in parallel with the PSE. In this case, priority will be
given to the higher supply voltage. If the wall transformer
voltage is higher, the PSE should remove line voltage since
no current will be drawn from the PSE. On the other hand,
if the wall transformer voltage is lower, the PSE will
continue to supply power to the PD and the wall transformer power will not be used. Proper operation should
occur in either scenario.
If auxiliary power is applied after the LTC4257-1 (option 2),
a different set of tradeoffs arise. In this configuration, the
wall transformer does not need to exceed the LTC4257-1
turn-on UVLO requirement; however, it is necessary to
include diode D9 to prevent the transformer from applying
power to the LTC4257-1. The transformer voltage requirements will be governed by the needs of the PD switcher and
may exceed 57V. However, power priority issues require
more intervention. If the wall transformer voltage is below
the PSE voltage, then priority will be given to the PSE power.
The PD will draw power from the PSE while the transformer
will sit unused. This configuration is not a problem in a PoE
system. On the other hand, if the wall transformer voltage
is higher than the PSE voltage, the PD will draw power from
the transformer. In this situation, it is necessary to address
the issue of power cycling that may occur if a PSE is present.
The PSE will detect the PD and apply power. If the PD is being
powered by the wall transformer, then the PD will not meet
the minimum load requirement and the PSE will subsequently remove power. The PSE will again detect the PD and
power cycling will start. With a transformer voltage above
the PSE voltage, it is necessary to either disable the signature, as shown in option 2, or install a minimum load on the
output of the LTC4257-1 to prevent power cycling.
The third option also applies power after the LTC4257-1,
while omitting diode D9. With the diode omitted, the
transformer voltage is applied to the LTC4257-1 in addition to the load. For this reason, it is necessary to ensure
42571fb
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OPTION 1: AUXILARY POWER INSERTED BEFORE LTC4257-1
RJ45
1
2
3
6
TX +
TX
T1
~
–
RX +
BR1
DF01SA
TO PHY
~
RX –
D3
SMAJ58A
TVS
+
C14
0.1µF
100V
–
GND
4
SPARE +
~
5
7
8
PD
LOAD
C1
8
+
LTC4257-1
BR2
DF01SA
SPARE –
~
4
–
+
5
VOUT
VIN
D8
S1B
ISOLATED
WALL
38V TO 57V
TRANSFORMER
–
OPTION 2: AUXILARY POWER INSERTED AFTER LTC4257-1 WITH SIGNATURE DISABLED
RJ45
1
2
3
6
TX +
T1
~
TX –
RX +
~
–
SPARE
+
~
5
7
8
C1
BSS63
8
GND
4
100k
C14
0.1µF
100V
BR1
DF01SA
TO PHY
RX –
+
D3
SMAJ58A
TVS
7
SIGDISA
+
100k
LTC4257-1
BR2
DF01SA
SPARE –
~
ISOLATED
WALL
TRANSFORMER
–
PD
LOAD
4
VIN
D9
S1B
5
VOUT
+
D10
S1B
–
OPTION 3: AUXILARY POWER APPLIED TO LTC4257-1 AND PD LOAD
RJ45
1
2
3
6
TX +
T1
~
TX –
RX +
BR1
DF01SA
TO PHY
~
RX –
+
D3
SMAJ58A
TVS
C14
0.1µF
100V
–
C1
GND
4
SPARE +
~
5
7
8
+
8
PD
LOAD
LTC4257-1
BR2
DF01SA
SPARE –
~
ISOLATED
WALL
TRANSFORMER
+
38V TO 57V
–
4
VIN
VOUT
5
D10
S1B
–
42571 F09
Figure 9. Auxiliary Power Source for PD
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that the transformer maintain the voltage between 38V and
57V to keep the LTC4257-1 in its normal operating range.
The third option has the advantage of automatically disabling the 25k signature when the external voltage exceeds the PSE voltage.
Classification Resistor Selection (RCLASS)
The IEEE specification allows classifying PDs into four
distinct classes with class 4 being reserved for future use
(Table 2). An external resistor connected from RCLASS to
VIN (Figure 4) sets the value of the load current. The
designer should determine which power category the PD
falls into and then select the appropriate value of RCLASS
from Table 2. If a unique load current is required, the value
of RCLASS can be calculated as:
RCLASS = 1.237V/(IDESIRED – IIN_CLASS)
where IIN_CLASS is the LTC4257-1 IC supply current
during classification and is given in the electrical specifications. The RCLASS resistor must be 1% or better to
avoid degrading the overall accuracy of the classification
circuit. Resistor power dissipation will be 50mW maxi-
mum and is transient so heating is typically not a concern. In order to maintain loop stability, the layout should
minimize capacitance at the RCLASS node. The classification circuit can be disabled by floating the RCLASS pin. The
RCLASS pin should not be shorted to VIN as this would
force the LTC4257-1 classification circuit to attempt to
source very large currents. In this case, the LTC4257-1
will quickly go into thermal shutdown.
Power Good Interface
The PWRGD signal is controlled by a high voltage, opendrain transistor. Examples of active-high and active-low
interface circuits for controlling the PD load are shown in
Figure 10.
In some applications it is desirable to ignore intermittent
power bad conditions. This can be accomplished by
including capacitor C15 in Figure 10 to form a lowpass
filter. With the components shown, power bad conditions
less than about 200µs will be ignored. Conversely, in other
applications it may be desirable to delay assertion of
PWRGD to the PD load. The PWRGD signal can be delayed
with the addition of capacitor C17 in Figure 10.
ACTIVE-LOW ENABLE, 5.1V SWING
GND
8
R9
100k
LTC4257-1
TO
PSE
PWRGD
–48V
4 VIN
PD
LOAD
R18
10k
6
+
VOUT 5
C1
5µF
100V
SHDN
C15*
0.047µF
10V
D6
5.1V
MMBZ5231B
*C15 OPTIONAL TO FILTER PWRGD.
SEE APPLICATIONS INFORMATION
ACTIVE-HIGH ENABLE FOR RUN PIN WITH INTERNAL PULLUP
GND
TO
PSE
8
LTC4257-1
PWRGD
–48V
4 VIN
Q1
FMMT2222
R18
10k
6
+
VOUT 5
INTERNAL
PULLUP
R9
100k
C1
5µF
100V
D6
MMBD4148
C15*
0.047µF
10V
PD
LOAD
RUN
C17*
42571 F10
*C15 AND C17 OPTIONAL TO FILTER PWRGD.
SEE APPLICATIONS INFORMATION
Figure 10. Power Good Interface Examples
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Signature Disable Interface
Maintain Power Signature
To disable the 25k signature, connect the SIGDISA pin to the
GND pin. Alternately, SIGDISA can be driven high with
respect to VIN. An example of a signature disable interface
circuit is shown in Figure 9, option 2. Note that the SIGDISA
input resistance is relatively large and the threshold voltage
is fairly low. Because of high voltages present on the printed
circuit board, leakage currents from the GND pin could
inadvertently pull SIGDISA high. To insure trouble-free
operation, use high-voltage layout techniques in the vicinity
of SIGDISA. If unused, connect SIGDISA to VIN.
In an IEEE 802.3af system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically
draw at least 10mA and also have an AC impedance less
than 26.25kΩ in parallel with 0.05µF. The PD application
circuits shown in this data sheet meet the requirements
necessary to maintain power. If either the DC current is
less than 10mA or the AC impedance is above 26.25kΩ,
the PSE might disconnect power. The DC current must be
less than 5mA and the AC impedance must be above 2MΩ
to guarantee power will be removed.
Load Capacitor
The IEEE 802.3af specification requires that the PD maintain a minimum load capacitance of 5µF. It is permissible
to have a much larger load capacitor and the LTC4257-1
can charge very large load capacitors before thermal
issues become a problem. However, the load capacitor
must not be too large or the PD design may violate IEEE
802.3af requirements.
If the load capacitor is too large there can be a problem with
inadvertent power shutdown by the PSE. Consider the following scenario. If the PSE is running at – 57V (maximum
allowed) and the PD has been detected and powered up,
the load capacitor will be charged to nearly – 57V. If for
some reason the PSE voltage suddenly is reduced to – 44V
(minimum allowed), the input bridge will reverse bias and
PD power will be supplied solely by the load capacitor.
Depending on the size of the load capacitor and the DC load
of the PD, the PD will not draw any power from the PSE
for a period of time. If this period of time exceeds the IEEE
802.3af 300ms disconnect delay, the PSE may remove
power from the PD. For this reason, it is necessary to
evaluate the load capacitance and load current to ensure
that inadvertent shutdown cannot occur.
Very small output capacitors (≤10µF) will charge very
quickly in current limit. The rapidly changing voltage at
the output may reduce the current limit temporarily,
causing the capacitor to charge at a somewhat reduced
rate. Conversely, charging very large capacitors may
cause the current limit to increase slightly. In either case,
once the output voltage reaches its final value, the input
current limit will be restored to its nominal value.
Layout
The LTC4257-1 is relativity immune to layout problems.
Excessive parasitic capacitance on the RCLASS pin should
be avoided. If using the DD package, include an electrically
isolated heat sink to which the exposed pad on the bottom
of the package can be soldered. For optimum thermal
performance, make the heatsink as large as possible.
Voltages in a PD can be as large as – 57V, so high voltage
layout techniques should be employed.
The load capacitor connected between Pins 5 and 8 of the
LTC4257-1 can store significant energy when fully charged.
The design of a PD must ensure that this energy is not
inadvertently dissipated in the LTC4257-1. The polarityprotection diode(s) prevent an accidental short on the
cable from causing damage. However, if the VIN pin is
shorted to the GND pin inside the PD while the load
capacitor is charged, current will flow through the parasitic body diode of the internal MOSFET and may cause
permanent damage to the LTC4257-1.
Electro Static Discharge and Surge Suppression
The LTC4257-1 is specified to operate with an absolute
maximum voltage of – 100V and is designed to tolerate
brief overvoltage events. However, the pins that interface
to the outside world (primarily VIN and GND) can routinely
see peak voltages in excess of 10kV. To protect the
LTC4257-1, it is highly recommended that a transient
voltage suppressor be installed between the bridge and
the LTC4257-1 (D3 in Figure 2).
42571fb
17
IN
FROM
PSE
RJ45
8
7
5
4
6
3
2
1
J2
SPARE–
SPARE
+
9
10
11
RX +
RX –
14
15
16
TX –
TX +
4
T1
R2
75Ω
C3
0.01µF
200V
8
7
6
3
2
1
RXOUT –
RXOUT +
TXOUT –
TXOUT +
OUT
TO PHY
C2
1000pF
2kV
R1
75Ω
C7
0.01µF
200V
R30
75Ω
C24
0.01µF
200V
D15
B1100
D16
B1100
D14
B1100
D12
B1100
RCLASS
1%
3
GND
D13
MMSD4148
VOUT
PWRGD
LTC4257CDD-1
VIN
NC
RCLASS SIGDISA
NC
D6
SMAJ58A
C11
0.1µF
100V
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS ARE 5%
2. ALL CAPACITORS ARE 25V
3. SELECT RCLASS FOR CLASS 1-4 OPERATION. REFER
TO DATA SHEET APPLICATIONS INFORMATION SECTION
4. CONNECT TO CHASSIS GROUND
C4 TO C6: TDK C4532X5R0J107M
C2, C23: AVX 1808GC102MAT
D1, D7: MM3Z12VT1
D3: MMBD1505
D9 TO D12, D14 TO D16: DIODES INC., B1100
L1: COILCRAFT D01608C-472
T1: PULSE H2019
T2: PULSE PB2134
T3: PULSE PA0184
D17
B1100
R31
75Ω
C25
0.01µF
200V
D10
B1100
D11
B1100
+
D7
12V
R17
10k
R14
100k
C1A
10µF
100V
R13
30.1k
1%
D3A
R23
3.65k
1%
tON
D1
12V
C12
0.1µF
50V
C10
4.7µF
35V
R5
47K
VCC
UVLO
R25
62k
R26
10k
R27
62k
C13
470pF
R11
10k
GATE
C19
47pF
C20
0.47µF
Q2
MMBT3904
VC
ISENSE
Q5
MMBT3904
C21
0.1µF
C22
680pF
0603
Q4
MMBT2907ALT1
SFST RCMPC
R9
100Ω
C9
R8 100pF
47Ω
R6
47Ω
D2
BAT54
OSCAP SGND PGND
LT1737CGN
R10
62k
D4
BAS21LT1
Q1
MMBTA06
MINENAB ROCMP ENDLY
R7
33Ω
1/4W
D3B
3VOUT
FB
R24
100k
C1C
0.82µF
100V
Q9
2N7002
C1B
0.82µF
100V
L1
4.7µH
R28
10k
C17
3300pF
Q3
Si4490DY
R15
1•
0.22Ω
1/2W T3
1%
8
C16
0.1µF
50V
R16
330Ω
SEPARATING
LINE
FOR GROUND
PLANE
3
1•
4•
5
Q6
Si7892DP
R12
47Ω
D5
B0540W
VOUT–
VOUT+
C4 TO C6
100µF
6.3V
3.3V @ 3.3A
R18
100Ω
42571 TA02
4
R4
10k
C14
1µF
Q7
Q8
FMMT718 MMBT3904
D8
BAT54
C23
1000pF
2kV
4
5
C18
1nF
10
9
11
8
T2
APPLICATIO S I FOR ATIO
U U
W
U
D9
B1100
•
•
18
•
Figure 11. PD Power Interface with 3.3V, 3.3A High Efficiency Isolated Power Supply
LTC4257-1
42571fb
LTC4257-1
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
.050 BSC
.245
MIN
8
.160 ±.005
7
6
5
.053 – .069
(1.346 – 1.752)
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
3
2
NOTE:
1. DIMENSIONS IN
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
.010 – .020
× 45°
(0.254 – 0.508)
4
RECOMMENDED SOLDER PAD LAYOUT
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
SO8 0303
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
TYP
5
0.38 ± 0.10
8
0.675 ±0.05
3.5 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
3.00 ±0.10
(4 SIDES)
PACKAGE
OUTLINE
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD8) DFN 1203
0.25 ± 0.05
0.200 REF
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.75 ±0.05
0.00 – 0.05
4
0.25 ± 0.05
1
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
42571fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC4257-1
U
TYPICAL APPLICATIO
PD Power Interface with 3.3V, 3A Nonisolated Power Supply
L1
1µH
J1
1
TX + 16 T1 1
2
3
6
4
TX
TXOUT +
2
15
–
14
3
RX + 11
TXOUT –
6
RXOUT +
10
7
9
8
RX –
XFMR
RXOUT –
R11
75Ω
+
~
0.01µF
0.01µF
200V
200V 75Ω
SPARE –
+
D3
TVS
SMAJ58A
C8
0.001µF
BR1
2kV
DF01SA
~
LTC4257-1
NC
C14
0.1µF
100V
3
~
75Ω
8
C3
0.01µF
200V
SPARE +
5
7
TO
PHY
R12
75Ω
C4
0.01µF
200V
–
R13
100k
Q2
FMMT625
D4
MMBZ5235B
6.8V
RCLASS SIGDISA
NC
PWRGD
VIN
VOUT
+
BR2
DF01SA
~
GND
C1A
4.7µF
100V
C1B
2.2µF
100V
RCLASS
1%
2
D5
UPS840
–
9 10
2
T2
CTX-02-15242
RJ45
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTOR VALUES ARE 5%
2. SELECT RCLASS FOR CLASS 1-4 OPERATION.
REFER TO DATA SHEET APPLICATIONS INFORMATION SECTION
3. CONNECT TO CHASSIS GROUND
C1A: PANASONIC ECEV2AA4R7P
C1B: TDK C5750X7R2A225KT
C8: AVX 1808GC102MAT
C9, C10, C12, C13: TDK C4532X5ROJ107
L1: LQLB2518T1ROM
T1: PULSE H2019
R9
100k
R18
10k
R10
100k
RUN
Q1
2N7002
D6
1N4148
Q4
FMMT2222
R17
750Ω
RC
12k
CC1
1nF
SENSE
ITH
VIN
FB
INTVCC
FREQ
RT
80.6k
1%
R16
100Ω
•
LTC1871
GATE
+
•
•
4 11 12
C9
100µF
X5R
6.3V
C10
100µF
X5R
6.3V
+
+
VOUT+
3.3V
AT 3A
C12
100µF
X5R
6.3V
C13
100µF
X5R
6.3V
+
Q3
FDC2512
MODE/SYNC GND
R15
21k 1%
R14
12.4k
1%
C5
4.7µF
6.3V
C6
1µF 6.3V
R5
0.1Ω
1%
VOUT–
4257 TA03
RELATED PARTS
PART NUMBER
LTC1737
LTC1871
LTC3803
DESCRIPTION
High Power Isolated Flyback Controller
Wide Input Range, No RSENSE™ Current Mode Flyback,
Boost and SEPIC Controller
Current Mode Flyback DC/DC Controller in ThinSOT™
LTC4257
LTC4258
IEEE 802.3af PD Interface Controller
Quad IEEE 802.3af Power over Ethernet Controller
LTC4259A-1
Quad IEEE 802.3af Power over Ethernet Controller
LTC4267
IEEE 802.3af PD Interface Controller with
Integrated Switching Regulator
COMMENTS
Sense Output Voltage Directly from Primary-Side Winding
Adjustable Switching Frequency, Programmable Undervoltage
Lockout, Optional Burst Mode® Operation at Light Load
200kHz Constant Frequency, Adjustable Slope Compensation,
Optimized for High Input Voltage Applications
100V, 400mA Internal Switch, Programmable Classification
DC Disconnect Only, IEEE-Compliant PD Detection and Classification,
Autonomous Operation or I2C™ Control
AC or DC Disconnect, IEEE-Compliant PD Detection and
Classification, Autonomous Operation or I2C Control
Onboard 100V, 400mA Internal Switch, 16-Pin SSOP or 3mm × 5mm
DFN Packages
Burst Mode is a registered trademark of Linear Technology Corporation. No RSENSE and ThinSOT are trademarks of Linear Technology Corporation.
42571fb
20
Linear Technology Corporation
LT 1205 1K REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2003