STMICROELECTRONICS STHS4257L1

STHS4257A, STHS4257A1
STHS4257L, STHS4257L1
IEEE 802.3af PoE Powered Device (PD)
interface controller with integrated signature resistor
Features
■
IEEE 802.3af-compliant interface for Powered
Devices (PDs)
■
Integrated 100V, 450mA power MOSFET low
side switch
■
Inrush current limit
■
Normal operation current limit
■
Integrated 25kΩ signature resistor
■
Signature disable (STHS4257A1/L1)
■
Resistor-programmable classification current
(Class 0-4)
■
Power Good output, open drain
■
Undervoltage Lockout (UVLO)
■
Thermal overload protection (two-step for the
STHS4257A/L)
■
Latch (L) or auto-retry (A) after repetitive
thermal overload
■
SO8 and DFN8 (3mm x 3mm) packages
■
RoHS compliant
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Order code
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Signature
disable
STHS4257A
STHS4257A1
✔
STHS4257L
STHS4257L1
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SO8 (M)
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Applications
Industrial temperature range: –40 to +85°C
Device options
1
DFN8 3mm x 3mm (DB)
■
Table 1.
8
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Voice over IP (VoIP) phones
■
Web cameras
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WLAN access points
Internet appliances
POS terminals
RFID readers
UVLO
threshold,
rising (V)
UVLO
threshold,
falling (V)
Protection
mode
39.2
30.5
Auto
2 steps
36.0
30.5
Auto
1 step
39.2
30.5
Latch
2 steps
36.0
30.5
Latch
1 step
Thermal
overload
protection
Inrush
current limit
(mA, typ)
Normal
operation
current limit
(mA, typ)
350/188 (1)
140
375
350/188 (1)
140
375
1. Current limit is common for both modes and gets reduced only in case of thermal overload. See Table 5: Electrical parameters.
July 2007
Rev 4
1/18
www.st.com
1
Contents
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
1.2
2
1.1.1
Classification (RCLASS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.2
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.3
Power supply (GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.4
Signature disable input (SIGDISA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.5
Power Good output (PWRGD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.6
Negative power output (VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
IEEE802.3af PD power classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
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Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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Package mechanical data . . . . . . . . . . . . . . . . . . . . . . .r. . . . . . . . . . . . . 14
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Part numbering . . . . . . . . . . . . . . . . . . . . . . . .t. . . . . . . . . . . . . . . . . . . . 16
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Revision history . . . . . . . . . . . . . .b
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Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Device options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
IEEE802.3af PD power classes and corresponding RCLASS values. . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SO8 – 8-lead plastic small outline, 150mils width, mechanical data. . . . . . . . . . . . . . . . . . 14
DFN8 – 8-lead dual flat no-lead outline, package mechanical data . . . . . . . . . . . . . . . . . . 15
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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List of figures
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections (STHS4257A/L, top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections (STHS4257A1/L1, top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Application circuit overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram (STHS4257A/L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical application circuit (STHS4257A/L) with a DC/DC converter. . . . . . . . . . . . . . . . . . . 9
Block diagram (STHS4257A1/L1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical application circuit (STHS4257A1/L1) with a DC/DC converter. . . . . . . . . . . . . . . . 10
SO8 – 8-lead plastic small outline, 150mils width, mechanical drawing . . . . . . . . . . . . . . . 14
DFN8 – 8-lead dual flat no-lead outline, package mechanical drawing . . . . . . . . . . . . . . . 15
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STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
1
Summary description
Summary description
The STHS4257 is an IEEE802.3af-compliant family of interface controllers for Power over
Ethernet (PoE) Powered Device (PD) applications. The devices consist of two main
sections:
●
The IEEE802.3af interface to the PoE powered RJ-45 wall socket, and
●
the Hot Swap Controller (HSC) functions required to protect the PD during insertion,
operation, and withdrawal from the RJ-45 socket.
These devices have an integrated high voltage power MOSFET (low-side switch) with low
RON and the capability to accept transients as high as 100V. Since the pins (such as GND
and VIN) which interface to the RJ-45 socket can routinely see high peak voltages in excess
of 100V, it is strongly recommended that board designers protect the PD device with a
transient voltage suppressor, such as the SMAJ58A (available from STMicroelectronics),
connected between the GND and VIN pins (see Figure 4 on page 8).
The IEEE802.3af-compliant interface includes the basic PD detection and Classification
functions, whereas the ‘Hot Swap’ functions include other basic features, such as Inrush
Current Limiting, Undervoltage Lockout (UVLO), and Thermal Overload Protection. All of the
devices include an open drain Power Good (PWRGD) signal to indicate normal steady
operation (see Figure 1 on page 6 and Table 2 on page 6). The STHS4257 family also
incorporates a 1.5V voltage offset (two series diodes) to accommodate the input diode
bridge used to make the PD polarity insensitive.
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The STHS4257A1/L1 includes a dual level current limit circuit. This allows the
STHS4257A1/L1 to interface with legacy Power over Ethernet (LAN) systems while
maintaining compatibility with the current IEEE 802.3af specification.
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Each of the two basic part types, the STHS4257A/L and the STHS4257A1/L1, is available
either with Latched Operation (L) Mode or with Automatic Retry (A) Mode after fault
conditions. For product options overview see Table 1 on page 1.
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Summary description
Figure 1.
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Logic diagram
GND
SIGDISA(1)
PWRGD
STHS4257A/L
STHS4257A1/L1
RCLASS
VOUT
VIN
AI12214a
1. STHS4257A1 and STHS4257L1 devices only.
Table 2.
Signal names
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Pin
Symbol
Description
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STHS4257A/L STHS4257A1/L1
1, 3, 7
1, 3
NC
2
2
RCLASS
4
4
VIN
5
5
VOUT
6
6
PWRGD
Power Good Output, open drain, active-low (referenced to VIN)
—
7
SIGDISA
Signature Disable Input, internally pulled to VIN
8
8
GND
Figure 2.
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Power Output (negative rail)
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Positive Power Supply; common input/output power rail
NC
1
8
GND
RCLASS
2
7
NC
NC
3
6
PWRGD
VIN
4
5
VOUT
AI12204b
Pin connections (STHS4257A1/L1, top view)
NC
1
8
GND
RCLASS
2
7
SIGDISA
NC
3
6
PWRGD
VIN
4
5
VOUT
AI12205b
6/18
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Negative return power line to PSE
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Classification pin
Pin connections (STHS4257A/L, top view)
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Figure 3.
No Connect
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
1.1
Pin descriptions
1.1.1
Classification (RCLASS)
Summary description
This is the Classification pin. Connect a Classification resistor between this pin and VIN to
tell the PSE which power class will be connected. Leave it open for Class 0.
Note: Do not connect this pin directly to VIN. For power classes and RCLASS resistor values,
see Table 3.
1.1.2
VIN
This is negative return power line to PSE.
1.1.3
Power supply (GND)
This is the Power Input/Output, positive rail.
1.1.4
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Signature disable input (SIGDISA)
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This pin is internally pulled down to VIN to present a valid signature to PSE. Connect to VIN
if it is unused. Tie to GND to present an invalid signature.
Note: This signal is available for STHS4257A1 and STHS4257L1 only.
1.1.5
Power Good output (PWRGD)
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This pin indicates that the STHS4257x/x1 power MOSFET is fully on and works in normal
operation mode (Power Good). Open drain, low impedance means that the power is good; in
all other cases, the impedance is high (referenced to VIN).
1.1.6
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Negative power output (VOUT)
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IEEE802.3afdPD power classes
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This is the Power Output, negative rail.
1.2
Table 3.
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IEEE802.3af PD power classes and corresponding RCLASS values
Class
Usage
Max. power levels
at input of PD (W)
Nominal classification
load current (mA)
RCLASS Resistor
(Ω, 1%)
0
Default
0.44 to 12.95
<5
Open
1
Optional
0.44 to 3.84
10.5
124
2
Optional
3.84 to 6.49
18.5
68.1
3
Optional
6.49 to 12.95
28
45.3
4
Reserved
Reserved (1)
40
30.9
1. Class 4 is currently reserved and should not be used.
7/18
Summary description
Figure 4.
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Application circuit overview
RJ-45
TX
Pair
Data to Ethernet Physical Layer Device
2x DF01S
GND
100
kΩ
SMAJ58A
SIGDISA(1)
PWRGD
STHS4257A/L
STHS4257A1/L1
C1
0.1µF,
100V
Spare
Pair
RCLASS
+ C2
RX
Pair
RCLASS
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Data to Ethernet Physical Layer Device
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VOUT
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1. STHS4257A1 and STHS4257L1 devices only. To disable signature, tie this pin to GND.
2. This configuration uses either data wires or spare wires for DC power.
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100µF,
100V
VIN
Spare
Pair
To DC/DC
Converter
AI12203b
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Figure 5.
Summary description
Block diagram (STHS4257A/L)
Classification
Current Source
1
NC
+
ref
–
RCLASS
2
NC
3
25k
Signature
Resistor
EN
8
GND
7
NC
6
PWRGD
Power Good
Control
Circuits
+
ref
EN
Input
Current
Limit
Power
MOSFET
–
RS
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VIN 4
5 VOUT
AI12206c
Figure 6.
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Typical application circuit (STHS4257A/L) with a DC/DC converter
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Powered Device (PD)
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~
48V from
power sourcing
equipment (PSE)
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+
SMAJ58A
C1
Diode
Bridge 0.1µF
~
DF01S
–
GND
STHS4257A/L
RCLASS
100V
100
kΩ
VIN
5µF
(min) Switching
+ 100V
C2
PWRGD
RCLASS
Power
Supply
SHDN
RTN
VIN
VOUT
+
3V
to logic
–
AI12207a
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Summary description
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Figure 7.
Block diagram (STHS4257A1/L1)
Classification
Current Load
NC
1
–
RCLASS
8
+
ref
GND
9kΩ
EN
25k
Signature
Resistor
2
Signature Disable
7 SIGDISA
16kΩ
NC
3
6 PWRGD
Power Good
Control
Circuits
ref1(1)
+
ref2(2)
EN
VIN 4
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1. Ref.1 = ILIMIT HIGH
2. Ref. 2 = ILIMIT LOW
Figure 8.
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5 VOUT
AI12208a
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Typical application circuit (STHS4257A1/L1) with a DC/DC converter
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Power
MOSFET
–
RS
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Input
Current
Limit
48V from
power sourcing
equipment (PSE)
~
+
Powered Device (PD)
SMAJ58A
STHS4257A1/L1 100
C1
Diode
Bridge 0.1µF
~
–
DF01S
GND
RCLASS
100V
kΩ
SIGDISA
PWRGD
RCLASS
VIN
5µF
(min)
+ 100V
VOUT
C2
VIN
Switching
Power
Supply
SHDN
RTN
+
3V
to logic
–
AI12209a
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
2
Absolute maximum ratings
Absolute maximum ratings
Stressing the device above the rating listed in the Table 4: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
+0.3 to –100
V
Voltage on VOUT pin
VIN +100 to VIN –0.3
V
Voltage on the respective pins
VIN +90 to VIN –0.3
V
VRCLASS
Voltage on RCLASS pin
VIN +7 to VIN –0.3
V
IPWRGD
Power Good output current
10
IRCLASS
RCLASS pin current
100
Input/supply voltage (1)
VIN
VOUT
VSIGDISA, VPWRGD
TA
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Operating ambient temperature range
–40 to 85
TSTG
Storage temperature
–55 to 150
TSLD
Lead solder temperature for 10 seconds,
lead-free lead finish (2)
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260
mA
mA
°C
°C
°C
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1. With respect to the GND pin.
2. Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C for more than 30 seconds).
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Electrical parameters
3
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Electrical parameters
Over the full operating temperature range, unless otherwise noted. Specifications common
for both STHS4257x (=STHS4257A, STHS4257L) and STHS4257x1 (=STHS4257A1,
STHS4257L1) product families unless otherwise noted.
Table 5.
Electrical parameters
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
–57
V
–1.5
–9.5
V
–12.5
–21
V
Maximum Operating Voltage
Signature Range
Classification Range
VIN
UVLO Turn-On Voltage,
STHS4257x1
Input/supply voltage - with respect
to GND pin (1), (2), (3)
–34.8 –36.0 –37.2
V
UVLO Turn-On Voltage,
STHS4257x
–37.7 –39.2 –40.2
V
UVLO Turn-Off Voltage
–29.3 –30.5 –31.5
V
0.33
mA
Supply Current when on
VIN = –48V, pins 5, 6, 7 floating
IIN CLASS
Supply Current During
Classification
VIN = –17.5V, pins 2, 7 floating,
VOUT tied to GND (4)
ΔICLASS
Current Accuracy During
Classification
10mA < ICLASS < 40mA,
–12.5V ≤ VIN ≤ –21V (5)
Signature Resistance
–1.5V ≤ VIN ≤ –9.5V, VOUT tied to
GND, IEEE 802.3af 2-point
measurement (2), (6)
RINVALID
Invalid Signature Resistance
–1.5V ≤ VIN ≤ –9.5V, SIGDISA and
VOUT tied to GND, IEEE 802.3af
2-point measurement (2), (6), (7)
VIH
Signature Disable High Level
Input Voltage
VIL
Signature Disable Low Level
Input Voltage
IIN ON
RSIGNATURE
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With respect to VIN
Power Good Output Low Voltage
IPG = 1mA, VIN = –48V, PWRGD
referenced to VIN
VPG TH RISE (8)
Power Good Trip Point, power
good signal going inactive
VIN = –48V, voltage between VIN
and VOUT, VOUT rising
IPG LEAK
Power Good Leakage Current
VPWRGD - VIN = 57V, PWRGD
MOSFET off, VPWRGD = VGND (9)
On-Resistance
I = 350mA, VIN = –48V, measured
from VIN to VOUT
IOUT LEAK
VOUT Pin Leakage Current
VIN = 0V, power MOSFET off,
VOUT = 57V (10)
ILIMIT HIGH
Input Current Limit, High Level,
STHS4257x1
(normal operation mode)
VIN = –48V, VOUT = –43V (11), (12)
0°C ≤ TA ≤ 70°C
–40°C ≤ TA ≤ 85°C
VPG OUT
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RON
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0.25
23.25
9
3
With respect to VIN, low level
enables signature (7)
Signature Disable Input
Resistance
RINPUT
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With respect to VIN, high level
invalidates signature (7)
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0.5
0.38
mA
±3.5
%
26.00
kΩ
11.8
kΩ
57
V
0.45
V
100
2.7
kΩ
3.0
0.72
0.5
V
3.3
V
1
µA
1.0
Ω
1
µA
340
375
400
mA
330
375
400
mA
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Table 5.
Electrical parameters (continued)
Symbol
ILIMIT LOW
ILIMIT
Electrical parameters
Parameter
Input Current Limit, Low Level,
STHS4257x1
(inrush mode)
Conditions
VIN = –48V, VOUT = –43V (11), (12)
Input Current Limit, STHS4257x VIN = –48V, VOUT = –43V (14)
Min
Typ
Max
Unit
100
140
180
mA
300
350
400
mA
ILIMIT WARM
Overtemperature Input Current
Limit, STHS4257x
(14)
188
mA
TOVERTEMP
Overtemperature Trip
Temperature, STHS4257x
(14)
120
°C
TSHUTDOWN
Thermal Shutdown Trip
Temperature
(11) (13) (14)
140
°C
,
,
1. The STHS4257 family of PoE products operates with a negative supply voltage (with respect to the GND pin, unless
otherwise noted). Voltages in this data sheet are always referred to in terms of absolute magnitude, thus "maximum
negative voltage" means the most negative voltage and analogically "rising negative voltage" refers to a voltage that is
becoming more negative.
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2. The STHS4257 family of products is designed to work with two series diode drops caused by diode bridge that makes the
PD input polarity-insensitive. Parameter ranges specified in the Electrical Parameters Table are with respect to
STHS4257x/x1 pins and are designed to meet the IEEE 802.3af specifications when these diode drops are included. See
Figure 4 on page 8.
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3. The STHS4257x/x1 devices include hysteresis in the UVLO voltages to avoid any start-up oscillation. As required by IEEE
802.3af, the STHS4257 family devices will power up from a voltage source with 20Ω series resistance on the first trial.
4. The Supply Current During Classification (IIN CLASS) does not include classification current programmed at pin 2. Total
supply current in classification mode will be IIN CLASS + ICLASS (see also Note 5).
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5. ICLASS is the measured current flowing through RCLASS. ΔICLASS accuracy is with respect to the ideal current defined as
ICLASS = 1.237/RCLASS. The current accuracy specification does not include variations in RCLASS resistance. The total
classification current seen by PSE also includes the quiescent current (IIN CLASS). See Figure 4 on page 8.
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6. Signature resistance is measured via the 2-point ΔV/ΔI method as defined by IEEE 802.3af standard. The STHS4257
device family signature resistance is offset from standard 25kΩ to account for the series diode bridge resistance. With two
series diodes, the total PD resistance will be between 23.75kΩ and 26.25kΩ which meets IEEE 802.3af specifications. The
minimum probe voltages measured at the STHS4257x/x1 pins are –1.5 and –2.5V. The maximum probe voltages are –8.5
and –9.5V.
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7. To disable the 25kΩ signature, tie SIGDISA to GND (±0.1V) or hold SIGDISA high with respect to VIN. See Figure 4 on
page 8.
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8. VPG TH FALL is not used: To eliminate the current peak during the transition from inrush to normal operation mode, the
power MOSFET (between VOUT and VIN - see Figure 5 on page 9) turns fully on only after the inrush current decreases by
10% from its initial value (i.e. when the output capacitor is fully charged).
9. GND pin at the same potential as PWRGD pin to prevent ESD protection from impacting the measured results. To keep
PWRGD MOSFET off under this condition, maintain uninterrupted inrush current e.g. by applying 1V voltage between
VOUT and VIN pin. This will keep the device in inrush mode, thus preventing PWRGD from going active (on).
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10. To significantly reduce IOUT LEAK and eliminate its impact on total current during detection and classification, the resistor
divider used to provide feedback on VOUT - VIN voltage is disconnected below the UVLO threshold.
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11. The STHS4257x1 includes thermal protection. In the event of an overtemperature condition (TSHUTDOWN is reached), the
STHS4257x1 will turn off the power MOSFET until the part cools below the overtemperature limit (TOVERTEMP). The
STHS4257x1 is also protected against thermal damage from incorrect classification probing by the PSE: If the
STHS4257x1 temperature exceeds the shutdown trip point (TSHUTDOWN), the classification load current is disabled.
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12. The STHS4257x1 includes dual level input current limit. At turn-on, before output capacitor C2 is charged, the
STHS4257x1 current level is set to the low level. After the output capacitor C2 is charged, the STHS4257x1 switches to
high level current limit and remains there until the input voltage drops below the UVLO turn-off threshold.
13. The STHS4257 family devices include overtemperature protection that is intended to protect the device during momentary
overload conditions only. Continuous operation close to overtemperature limits may impair device reliability.
14. The STHS4257x includes smart thermal protection. In the event of an overtemperature condition, the STHS4257x will
reduce the input current limit by 50% to reduce the power dissipation in the package. If the part continues heating and
reaches the shutdown temperature (TSHUTDOWN), the current is reduced to zero until the part cools below the
overtemperature limit (TOVERTEMP). The STHS4257x is also protected against thermal damage from incorrect classification
probing by the PSE: If the STHS4257x temperature exceeds the shutdown trip point (TSHUTDOWN), the classification load
current is disabled.
13/18
Package mechanical data
4
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 9.
SO8 – 8-lead plastic small outline, 150mils width, mechanical drawing
h x 45˚
A2
A
C
B
ddd
e
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D
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8
E
H
1
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1. Drawing is not to scale.
Table 6.
α
A1
P
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)
mm
s
(
t
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u
d
Min
Max
Typ
Min
Max
–
1.35
1.75
–
0.053
0.069
–
0.10
0.25
–
0.004
0.010
–
0.33
0.51
–
0.013
0.020
C
–
0.19
0.25
–
0.007
0.010
D
–
4.80
5.00
–
0.189
0.197
ddd
–
–
0.10
–
–
0.004
E
–
3.80
4.00
–
0.150
0.157
e
1.27
–
–
0.050
–
–
H
–
5.80
6.20
–
0.228
0.244
h
–
0.25
0.50
–
0.010
0.020
L
–
0.40
0.90
–
0.016
0.035
α
–
0°
8°
–
0°
8°
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A1
B
N
14/18
inches
Typ
A
Ob
SO-A
SO8 – 8-lead plastic small outline, 150mils width, mechanical data
Symb
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s
L
8
8
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Package mechanical data
Figure 10. DFN8 – 8-lead dual flat no-lead outline, package mechanical drawing
A3
A1
A
A2
ddd C
Seating
Plane
C
D
e
2
3
4
E
E2
1
)
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L
8
7
6
5
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eP
Bottom View
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b
1. Drawing is not to scale.
Table 7.
DFN8 – 8-lead dual flat no-lead outline, package mechanical data
mm
Symb
Typ
Min
Max
0.80
1.00
0.035
0.031
0.039
0.02
–
0.05
0.001
0.70
–
–
0.028
A3
0.20
–
–
0.008
b
0.23
0.18
0.30
0.009
D
3.00
–
–
0.118
D2
2.38
2.23
2.48
0.094
ddd
–
–
0.08
E
3.00
–
–
0.118
E2
1.64
1.49
1.74
0.065
0.059
0.069
e
0.50
–
–
0.020
–
–
L
0.40
0.30
0.50
0.016
0.012
0.020
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A2
N
0.90
Min
inches
Typ
A1
Ob
)
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Max
A
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DFN-A
8
0.002
0.007
0.012
0.003
8
15/18
Part numbering
5
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Part numbering
Table 8.
Ordering information scheme
Example:
STHS
4257A1
M
6
F
Device type
STHS
Product options
4257A
4257A1
4257L
4257L1
)
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Package
M = SO8 (150mils width)
DB(1) = DFN8 (3mm x 3mm)
Temperature range
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6 = –40 to 85°C
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Shipping method
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F = ECOPACK Package, Tape & Reel
E = ECOPACK Package, Tube
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1. Contact local sales office for availability.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
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16/18
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
6
Revision history
Revision history
Table 9.
Document revision history
Date
Revision
Changes
12-Jul-2006
1
Initial release.
19-Dec-2006
2
Updated Features and Table 4.
24-May-2007
3
Formatting changes and updatedTable 5.
26-Jul-2007
4
Document status upgraded to full datasheet, updated cover page
and Table 8.
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17/18
STHS4257A, STHS4257A1, STHS4257L, STHS4257L1
Please Read Carefully:
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)
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)
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
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18/18