PHILIPS HEF4049BT

HEF4049B
Hex inverting buffers
Rev. 05 — 11 November 2008
Product data sheet
1. General description
The HEF4049B provides six inverting buffers with high current output capability suitable
for driving TTL or high capacitive loads. Since input voltages in excess of the buffers’
supply voltage are permitted, the buffers may also be used to convert logic levels of up to
15 V to standard TTL levels. Their guaranteed fan-out into common bipolar logic elements
is shown in Table 3.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is
also suitable for use over the industrial (−40 °C to +85 °C) temperature range.
2. Features
n
n
n
n
n
n
n
Accepts input voltages in excess of the supply voltage
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the full industrial temperature range −40 °C to +85 °C
Complies with JEDEC standard JESD 13-B
ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
3. Applications
n LOCMOS (Local Oxidation CMOS) to DTL/TTL converter
n HIGH sink current for driving two TTL loads
n HIGH-to-LOW level logic conversion
4. Ordering information
Table 1.
Ordering information
All types operate from −40 °C to +85 °C.
Type number
Package
Name
Description
Version
HEF4049BP
DIP16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
HEF4049BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
HEF4049B
NXP Semiconductors
Hex inverting buffers
5. Functional diagram
1A
2A
3A
4A
5A
6A
3
2
5
4
7
6
9
10
11
12
14
15
1Y
2Y
3Y
4Y
5Y
input
6Y
Y
A
001aai331
Fig 1.
Logic symbol
VSS
mna341
Fig 2.
Logic diagram for one gate
001aae604
Fig 3.
Input protection circuit
6. Pinning information
6.1 Pinning
HEF4049B
VDD
1
16 n.c.
1Y
2
15 6Y
1A
3
14 6A
2Y
4
13 n.c.
2A
5
12 5Y
3Y
6
11 5A
3A
7
10 4Y
VSS
8
9
4A
001aae602
Fig 4.
Pin configuration
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
VDD
1
supply voltage
1Y to 6Y
2, 4, 6, 10, 12, 15
output
HEF4049B_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 11 November 2008
2 of 11
HEF4049B
NXP Semiconductors
Hex inverting buffers
Table 2.
Pin description …continued
Symbol
Pin
Description
1A to 6A
3, 5, 7, 9, 11, 14
input
VSS
8
ground supply voltage
n.c.
13, 16
not connected
7. Functional description
Table 3.
Guaranteed fan-out
Driven element
Guaranteed fan-out
Standard TTL
2
74 LS
9
74 L
16
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
−0.5
VDD
supply voltage
VI
input voltage
II/O
input/output current
-
Tstg
storage temperature
Tamb
ambient temperature
Ptot
total power dissipation
P
power dissipation
Max
+18
−0.5
any input
Unit
V
VDD + 0.5
V
±10
mA
−65
+150
°C
−40
+85
°C
Tamb −40 °C to +85 °C
DIP16 package
[1]
-
750
mW
SO16 package
[2]
-
500
mW
-
100
mW
per output
[1]
For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2]
For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
supply voltage
3
-
15
V
VI
input voltage
Tamb
ambient temperature
in free air
0
-
VDD
V
−40
-
+85
°C
∆t/∆V
input transition rise and fall rate
VDD = 5 V
-
-
3.75
ns/V
VDD = 10 V
-
-
0.5
ns/V
VDD = 15 V
-
-
0.08
ns/V
HEF4049B_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 11 November 2008
3 of 11
HEF4049B
NXP Semiconductors
Hex inverting buffers
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
VIH
VIL
VOH
VOL
IOH
IOL
Conditions
|IO| < 1 µA
HIGH-level input voltage
|IO| < 1 µA
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
HIGH-level output current
LOW-level output current
|IO| < 1 µA
|IO| < 1 µA
Tamb = 25 °C
Tamb = 85 °C
Min
Max
Min
Max
Min
Max
Unit
5V
3.5
-
3.5
-
3.5
-
V
10 V
7.0
-
7.0
-
7.0
-
V
15 V
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
V
5V
4.95
-
4.95
-
4.95
-
V
10 V
9.95
-
9.95
-
9.95
-
V
15 V
14.95
-
14.95
-
14.95
-
V
5V
-
0.05
-
0.05
-
0.05
V
10 V
-
0.05
-
0.05
-
0.05
V
15 V
-
0.05
-
0.05
-
0.05
V
VO = 2.5 V
5V
−1.7
-
−1.4
-
−1.1
-
mA
VO = 4.6 V
5V
−0.52
-
−0.44
-
−0.36
-
mA
VO = 9.5 V
10 V
−1.3
-
−1.1
-
−0.9
-
mA
VO = 13.5 V
15 V
−3.6
-
−3.0
-
−2.4
-
mA
3.5
-
2.9
-
2.3
-
mA
VO = 0.5 V
VO = 0.4 V
10 V
12.0
-
10.0
-
8.0
-
mA
VO = 1.5 V
15 V
24.0
-
20.0
-
16.0
-
mA
15 V
-
±0.3
-
±0.3
-
±1.0
µA
II
input leakage current
VDD = 15 V
IDD
supply current
IO = 0 A
CI
Tamb = −40 °C
VDD
4.75 V
5V
-
4.0
-
4.0
-
30
µA
10 V
-
8.0
-
8.0
-
60
µA
15 V
-
16.0
-
16.0
-
120
µA
-
-
-
7.5
-
-
pF
Max
input capacitance
11. Dynamic characteristics
Table 7.
Dynamic characteristics
VSS = 0 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
tPHL
HIGH to LOW
propagation delay
nA to nY;
see Figure 5
VDD
5V
[1]
10 V
15 V
tPLH
LOW to HIGH
propagation delay
nA to nY;
see Figure 5
[1]
Extrapolation formula
Min
Typ
26 ns + (0.18 ns/pF)CL
-
35
70
ns
11 ns + (0.08 ns/pF)CL
-
15
30
ns
9 ns + (0.05 ns/pF)CL
-
12
25
ns
23 ns + (0.55 ns/pF)CL
-
50
100
ns
10 V
14 ns + (0.23 ns/pF)CL
-
25
50
ns
15 V
12 ns + (0.16 ns/pF)CL
-
20
40
ns
5V
HEF4049B_5
Product data sheet
Unit
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 11 November 2008
4 of 11
HEF4049B
NXP Semiconductors
Hex inverting buffers
Table 7.
Dynamic characteristics …continued
VSS = 0 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C; unless otherwise specified.
Symbol
tTHL
Parameter
Conditions
HIGH to LOW output
transition time
see Figure 5
LOW to HIGH output
transition time
see Figure 5
VDD
Extrapolation formula
[1]
5V
10 V
[1]
Typ
Max
Unit
3 ns + (0.35 ns/pF)CL
-
20
40
ns
3 ns + (0.14 ns/pF)CL
-
10
20
ns
2 ns + (0.09 ns/pF)CL
-
7
14
ns
10 ns + (1.00 ns/pF)CL
-
60
120
ns
10 V
9 ns + (0.42 ns/pF)CL
-
30
60
ns
15 V
6 ns + (0.28 ns/pF)CL
-
20
40
ns
15 V
tTLH
Min
[1]
5V
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol
Parameter
PD
dynamic power
dissipation
VDD
Typical formula for PD (µW)
where:
5V
PD = 2500 × fi + Σ(fo × CL) × VDD2
10 V
15 V
fi = input frequency in MHz;
PD = 11000 × fi + Σ(fo × CL) × VDD
2
fo = output frequency in MHz;
PD = 35000 × fi + Σ(fo × CL) × VDD
2
CL = output load capacitance in pF;
VDD = supply voltage in V;
Σ(CL × fo) = sum of the outputs.
12. Waveforms
tr
VI
tf
90 %
input
VM
0V
10 %
tPHL
VOH
tPLH
90 %
VM
output
10 %
VOL
tTHL
tTLH
001aai336
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5.
Table 9.
Input (nA) to output (nY) propagation delays and transition times
Measurement points
Input
Output
VM
VI
VM
VX
VY
0.5VDD
0 V to VDD
0.5VDD
0.1VDD
0.9VDD
HEF4049B_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 11 November 2008
5 of 11
HEF4049B
NXP Semiconductors
Hex inverting buffers
VDD
VI
VO
G
DUT
RT
CL
001aag182
Test data is given in Table 10.
Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 6.
Load circuitry for switching times
Table 10.
Test data
Supply voltage
5 V to 15 V
Input
Load
VI
VM
tr, tf
CL
VDD
0.5VI
≤ 20 ns
50 pF
HEF4049B_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 11 November 2008
6 of 11
HEF4049B
NXP Semiconductors
Hex inverting buffers
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
ME
seating plane
D
A2
A
A1
L
c
e
Z
w M
b1
(e 1)
b
b2
MH
9
16
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
b2
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
0.76
inches
0.17
0.02
0.13
0.068
0.051
0.021
0.015
0.049
0.033
0.014
0.009
0.77
0.73
0.26
0.24
0.1
0.3
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
ISSUE DATE
95-01-14
03-02-13
SOT38-4
Fig 7.
EUROPEAN
PROJECTION
Package outline SOT38-4 (DIP16)
HEF4049B_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 11 November 2008
7 of 11
HEF4049B
NXP Semiconductors
Hex inverting buffers
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig 8.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT109-1 (SO16)
HEF4049B_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 11 November 2008
8 of 11
HEF4049B
NXP Semiconductors
Hex inverting buffers
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
DUT
Device Under Test
DTL
Diode Transistor Logic
ESD
ElectroStatic Discharge
HBM
Human Body Model
LOCMOS
Local Oxidation CMOS
MM
Machine Model
TTL
Transistor Transistor Logic
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
HEF4049B_5
20081111
Product data sheet
-
HEF4049B_4
Modifications:
•
•
•
Maximum Tamb changed to 85 °C and Tamb = 125 °C parameter data removed throughout.
Section 1 “General description” temperature range statement modified.
Section 10 “Static characteristics” IDD, IOL, IOH, and II values updated.
HEF4049B_4
20080704
Product data sheet
-
HEF4049B_CNV_3
HEF4049B_CNV_3
19950101
Product specification
-
HEF4049B_CNV_2
HEF4049B_CNV_2
19950101
Product specification
-
-
HEF4049B_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 11 November 2008
9 of 11
HEF4049B
NXP Semiconductors
Hex inverting buffers
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
HEF4049B_5
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 05 — 11 November 2008
10 of 11
HEF4049B
NXP Semiconductors
Hex inverting buffers
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 3
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9
Legal information. . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Contact information. . . . . . . . . . . . . . . . . . . . . 10
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 11 November 2008
Document identifier: HEF4049B_5