SmartFusion2 SoC FPGA In-System
Programming Using UART Interface
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Demo Guide
May 2014
SmartFusion2 SoC FPGA In-System Programming Using UART Interface
Revision History
Date
Revision
Change
May 3, 2014
3.0
Fourth release
16 December 2013
2.0
Third release
02 December 2013
1.0
Second release
27 August 2013
0.0
First release
Confidentiality Status
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This document is a non-confidential.
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SmartFusion2 SoC FPGA In-System Programming Using UART Interface Demo Guide
Table of Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
About this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Microsemi Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
In-System Programming Using UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Requirements and Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Demo Design Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Demo Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Setting Up the Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Alternate Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Board Setup Snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Running the Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Example command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Resetting the board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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Authenticate Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Verify Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Program Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Checking if the fabric is programmed successfully . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Checking if the eNVM is programmed successfully . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Programming Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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Appendix 1: Connecting the SmartFusion2 Device to the Host PC Through the USB to UART (FTDI) Interface . 20
Appendix 2: Board Setup when Using the USB-RS232 Serial Adapter or RS232 Cable . . . . . . . . . . . . . . . . . . . 21
Appendix 3: Board setup through the USB to UART (FTDI) interface using the USB A to Mini - B Cable . . . . . . 22
Appendix 4: Jumper Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Appendix 5: Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Appendix 6: Generating .spi Programming File using Libero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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A List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-27
B Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-28
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Email . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
My Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Outside the U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision 3
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Preface
About this document
This demo is for SmartFusion®2 system-on-chip (SoC) field programmable gate array (FPGA) devices. It
provides instructions on how to use the corresponding reference design.
Intended Audience
•
FPGA designers
•
Embedded designers
•
System-level designers
References
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The following designers using the SmartFusion2 devices:
Microsemi Publications
SmartFusion2 Programming User Guide
•
SmartFusion2 System Controller User Guide
•
SmartFusion2 Microcontroller Subsystem User Guide
•
SmartFusion2 SoC FPGA Remapping eNVM, eSRAM, and DDR/SDR SDRAM Memories
Application Notes
•
Configuring Serial Terminal Emulation Programs Tutorial
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See the following web page for a complete and up-to-date listing of SmartFusion2 device documentation:
http://www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion2#documents.
Revision 3
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In-System Programming Using UART Interface
Introduction
You can use in-system programming (ISP) to reprogram for design iterations and field upgrades.
SmartFusion2 devices support ISP using the universal asynchronous receiver/transmitter (UART)
interface. This document describes how to program the following using ISP through the UART interface:
embedded Nonvolatile Memory (eNVM)
•
FPGA Fabric
•
Both the eNVM and the FPGA Fabric
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For information on different programming modes supported by SmartFusion2 SoC FPGAs, see the
SmartFusion2 Programming User Guide. For information on system controller programming services,
see the SmartFusion2 System Controller User Guide.
Requirements and Details
Table 1 • Reference Design Requirements and Details
Reference Design Requirements and Details
Hardware Requirements
Rev C or later
12 V adapter
•
FlashPro4 programmer
•
USB A to Mini-B cable
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SmartFusion2 Development Kit
•
Description
-
Host PC or Laptop
Windows 64-bit Operating System
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USB-RS232 Serial adapter or RS232 cable
Software Requirements
Libero® System-on-Chip (SoC) for viewing the design
files
•
11.3
FlashPro Programming Software v11.3
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Host PC Drivers
USB to UART drivers
Demo Design
Introduction
The demo design files are available for download from the following path in the Microsemi® website:
www.microsemi.com/soc/download/rsc/?f=sf2_isp_using_uart_interface_demo_df
The demo design files include:
•
Libero SoC software project
•
STAPL programming files
•
UART Host PC Loader application (M2S_UARTHost_Loader.exe)
•
Sample programming files
Revision 3
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In-System Programming Using UART Interface
Figure 1 shows the top-level structure of the design files. For further details, see the readme.txt file.
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Demo design files top level structure
Figure 2 describes the demo. The SmartFusion2 device application configures the MMUART_1
peripheral for serial communication and initializes the system controller to run the ISP service. The UART
Host PC Loader initiates the communication with the SmartFusion2 device through the UART interface
and sends the data bitstreams to the ARM® Cortex™-M3 processor.
The Cortex-M3 processor sends the received blocks of data to the system controller ISP service. The
system controller ISP service executes the ISP operation in the requested mode and reports the status to
the Cortex-M3 processor. See "Demo Design Description" on page 7 for information on modes of
operation.
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There are two ways to connect the Host PC to the SmartFusion2 device:
•
Using the USB-RS232 Serial adapter or the RS232 cable.
•
Using the USB to UART (FTDI) interface.
–
–
6
See "Running the Demo Design" section on page 12.
See "Appendix 1: Connecting the SmartFusion2 Device to the Host PC Through the USB to
UART (FTDI) Interface" on page 20.
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SmartFusion2 SoC FPGA In-System Programming Using UART Interface Demo Guide
Demo Design Features
The demo design performs three types of programming based on the input provided by the programming
file.
•
eNVM programming: The ISP programming service programs only eNVM. In this case, the input
programming file has only eNVM content.
•
FPGA Fabric programming: The ISP programming service programs only the FPGA Fabric. In
this case, the input programming file has only the FPGA Fabric content.
•
eNVM and FPGA Fabric programming: The ISP programming service programs both the FPGA
Fabric and eNVM. In this case, the input programming file has both the FPGA Fabric and eNVM
content.
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Demo Design Description
The ISP in SmartFusion2 devices is performed by the Cortex-M3 processor and the system controller.
The system controller manages the SmartFusion2 device programming and handles the system service
requests. The SmartFusion2 device allows the Cortex-M3 processor to directly provide a bitstream to the
system controller for programming. The Cortex-M3 processor initializes the system controller and
receives the programming bitstream from the Host PC through the UART interface. The received
bitstream is sent to the system controller to execute the ISP service in one of the following modes of
operation:
Authenticate: System controller ISP service validates the integrity of the input data bitstream and
reports the status information to the Cortex-M3 processor.
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Program: System controller ISP service programs the following depending on the input data
bitstream:
–
eNVM
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FPGA Fabric
–
Both the eNVM and the FPGA Fabric
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•
For security and reliability reasons, Microsemi recommends that the bitstream is
authenticated before the program is executed, using the Authenticate operation mode. The
SmartFusion2 device application must commit only the bitstream for programming, after
successful authentication and the integrity of the bitstream is validated.
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•
•
Verify: System controller ISP service verifies the contents of the SmartFusion2 device against the
input data bitstream and reports the status information to the Cortex-M3 processor.
The system controller ISP service utilizes the COMM_BLK interface to receive the entire programming
data bitstream as a continuous stream of bytes. Refer to the SmartFusion2 Microcontroller Subsystem
User Guide for more information on communication block (COMM_BLK).
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The Cortex-M3 processor in the SmartFusion2 device can execute an application image from embedded
SRAM (eSRAM), eNVM or DDR/SDR memories. Refer to the SmartFusion2 SoC FPGA Remapping
eNVM, eSRAM, and DDR/SDR SDRAM Memories Application Notes for more information on remapping
techniques. In this demo design, the Cortex-M3 processor executes the ISP application image from
eSRAM while the eNVM programming taking place, that is during Program operation mode. In order to
execute the application image from eSRAM, the Cortex-M3 processor copies the ISP application image
(resides in eNVM data client) to the eSRAM and remaps the eSRAM to the Cortex-M3 processor code
region. For Verify and Authenticate operation modes, the application image can be executed from either
eNVM or eSRAM since the eNVM programming is not taking place.
UART Host PC Loader
UART Host PC Loader (M2S_UARTHost_Loader.exe) is an executable program that transfers the
programming files (*.spi) from the Host PC to the SmartFusion2 Development Kit board.The
M2S_UARTHost_Loader.exe file is executed from the command prompt. It is located at:
<download_folder>\sf2_isp_using_uart_interface_demo_df\host_tool_and_samples.
The syntax is:
M2S_UARTHost_Loader.exe <*.spi> <COM Port number> <Operation Mode>
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In-System Programming Using UART Interface
Arguments:
•
*.spi programming file.
•
COM Port number.
•
Operation Mode. See Table 2.
For more information, see "Running the Demo Design" on page 12.
Table 2 shows the ISP operation modes and the values that are supplied in the command for the modes.
Table 2 • ISP Operation Modes
Value
Authenticate
0
Program
1
Verify
2
Programming Files
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Mode
Sample programming files with the file extension .spi are provided to program:
•
eNVM
•
FPGA Fabric
•
Both the eNVM and the FPGA Fabric
The folder <download_folder>\sf2_isp_using_uart_interface_demo_df\host_tool_and_samples contains
the following sample programming files.
isp_envm_only.spi: Programs only eNVM. The eNVM client has a simple message display
program.
•
isp_fabric_only.spi: Programs only the FPGA Fabric. The FPGA Fabric has a light-emitting
diode (LED) blinking logic.
•
isp_fabric_and_envm.spi: Programs both the FPGA Fabric and eNVM. The eNVM client
has a message display program and the FPGA Fabric has an LED blinking logic.
•
isp_demo.spi: This is the .spi file format version of isp_demo.stp file provided in
<download_folder>\sf2_isp_using_uart_interface_demo_df\stapl_programming_file.
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Note: For more information on generating .spi programming files, refer to the "Appendix 6: Generating
.spi Programming File using Libero" section on page 25.
ISP Execution Flow
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Figure 3 on page 9 describes the ISP flow. The UART Host PC Loader starts the communication with the
SmartFusion2 device through the UART interface. On connecting with the SmartFusion2 device, the
UART Host PC Loader sends the programming file size and the ISP operation mode to the target
SmartFusion2 device. The SmartFusion2 device initializes the system controller and starts the ISP
service in the chosen operation mode.
On receiving the data request from the SmartFusion2 device, the UART Host PC Loader starts
transferring the input source programming file in blocks of 4 Kb data with cyclic redundancy check
(CRC). The SmartFusion2 device:
•
Stores the received 4 Kb data in a temporary buffer.
•
Checks the CRC.
•
Inputs the same data to the ISP service.
•
Sends acknowledgment to the UART Host PC Loader for the 4 Kb data that was received and
requests to send the next block of 4 Kb data.
This operation repeats until the UART Host PC Loader transfers the entire file. The UART Host PC
Loader is notified with a status code when the ISP service completes the authentication or the verification
process. When the operation mode is Program, an internal device reset is generated for the new design
to take effect.
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R e vi s i o n 3
SmartFusion2 SoC FPGA In-System Programming Using UART Interface Demo Guide
Figure 3 shows the ISP execution flow.
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Revision 3
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In-System Programming Using UART Interface
Setting Up the Demo Design
1. Connect the FlashPro4 programmer to the J59 connector of the SmartFusion2 Development Kit
board.
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2. Connect the Host PC to the DB9-RS232 connector of the SmartFusion2 Development Kit board
using the USB-RS232 serial adapter cable or the RS232 cable.
When using USB-RS232 serial adapter cable, make sure that the USB-RS232 serial adapter
drivers are automatically detected. Figure 4 shows an example Device Manager window that has
the USB-to-Serial Comm Port listed under Ports (Comm & LPT). COM port number is required
to run the demo design, so make a note of it.
Figure 4 •
Device Manager window showing the USB-to-Serial Communication Port
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3. Connect the jumpers on the SmartFusion2 Development Kit board, as described in Table 3 on
page 11. For information on jumper locations, see "Appendix 4: Jumper Locations" section on
page 23.
–
10
Caution: Before making the jumper connections, switch off the power supply switch, SW7.
R e visio n 3
SmartFusion2 SoC FPGA In-System Programming Using UART Interface Demo Guide
Table 3 • SmartFusion2 Development Kit Jumper Settings
Settings
Notes
J70, J93, J94, J117, J123,
J142, J157, J160, J167,
J225, J226, J227
1-2 closed
These are the default jumper settings of the
Development Kit board. Make sure these
jumpers are set accordingly.
J2
1-3 closed
J23
2-3 closed
J188, 197
1-2 closed
•
Jumper settings when using
MMUART_1. These are not set by
default and must be set manually.
•
Leave these jumpers open if the
USB to UART (FTDI) interface is
used. See "Appendix 1: Connecting
the SmartFusion2 Device to the
Host PC Through the USB to UART
(FTDI) Interface" on page 20
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Jumper Number
4. Connect the power supply to the J18 DC jack.
Alternate Setup
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This demo can also be run using the USB to UART (FTDI) interface without using the USB-RS232 serial
adapter or the RS232 cable. See "Appendix 1: Connecting the SmartFusion2 Device to the Host PC
Through the USB to UART (FTDI) Interface" section on page 20 for information on how to connect the
Host PC to the SmartFusion2 Development Kit board for serial communication through the FTDI USB
interface using the USB A to Mini - B cable.
Board Setup Snapshot
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Snapshots of the SmartFusion2 Development Kit board with all the setup made in both types of
connections are given in the following appendices:
"Appendix 2: Board Setup when Using the USB-RS232 Serial Adapter or RS232 Cable" on
page 21
•
"Appendix 3: Board setup through the USB to UART (FTDI) interface using the USB A to Mini - B
Cable" on page 22
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In-System Programming Using UART Interface
Running the Demo Design
1. Download the demo design from:
www.microsemi.com/soc/download/rsc/?f=sf2_isp_using_uart_interface_demo_df.
2. Switch ON the SW7 power supply switch.
3. Launch the FlashPro software.
4. Click New Project.
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5. In the New Project window, type the project name.
Figure 5 •
FlashPro New Project
6. Click Browse and navigate to the location where you want to save the project.
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7. Select Single device as the Programming mode.
8. Click OK to save the project.
9. Click Configure Device.
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SmartFusion2 SoC FPGA In-System Programming Using UART Interface Demo Guide
FlashPro project configured
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Figure 6 •
rs
ed
ed
10. Click Browse and navigate to the location where the isp_demo.stp file is located and select the
file. The default location is:
<download_folder>\sf2_isp_using_uart_interface_demo_df\stapl_programming_file. The required
programming file is selected and is ready to be programmed in the device.
Revision 3
13
In-System Programming Using UART Interface
11. Click PROGRAM to start programming the device. Wait until you get a message indicating that
the program passed. ISP requires the SmartFusion2 device to be preprogrammed with the
application code to activate the ISP service. So, the SmartFusion2 device is preprogrammed with
the isp_demo.stp using FlashPro software.
LEDs 5 to 8 blinking in the board indicates that the SmartFusion2 Device fabric is
preprogrammed successfully.
pe
rs
ed
ed
–
Figure 7 •
FlashPro program passed
12. Open the Command Prompt in the Host PC.
Su
13. Navigate to the directory, where the UART Host PC Loader (M2S_UARTHost_Loader.exe) is
located. The default location is:
<download_folder>\sf2_isp_using_uart_interface_demo_df\host_tool_and_samples.
14. Execute the M2S_UARTHost_Loader.exe file and launch the UART Host PC Loader to
program the:
–
FPGA Fabric
–
eNVM
–
FPGA Fabric and eNVM
Example command
Example command for programming
isp_fabric_and_envm.spi file:
both
the
FPGA
Fabric
M2S_UARTHost_Loader.exe isp_fabric_and_envm.spi 24 1
Where, 24 is the Com port number and 1 is the Operation Mode: Program
14
R e visio n 3
and
eNVM
using
the
SmartFusion2 SoC FPGA In-System Programming Using UART Interface Demo Guide
Figure 8 shows the UART Host PC Loader example command.
UART Host PC Loader example command
Resetting the board
ed
ed
Figure 8 •
If the UART Host PC Loader is not connected to the SmartFusion2 Development Kit board, press the
switch, SW9 to reset the board.
UART Host PC Loader reset
pe
Figure 9 •
rs
Figure 9 shows an example message that instructs to reset the board.
Authenticate Operation Mode
To authenticate the data from isp_fabric_and_envm.spi, type:
M2S_UARTHost_Loader.exe isp_fabric_and_envm.spi 24 0
Su
Where, 24 is the Com port number and 0 is the Operation Mode: Authenticate.
Revision 3
15
In-System Programming Using UART Interface
Figure 10 • ISP Authentication Status
ed
ed
On completion of the ISP authentication, the command prompt displays an operation success message.
Figure 10 shows the operation success message.
Press the switch, SW9 to reset the SmartFusion2 Development Kit and try other ISP operation modes.
rs
Verify Operation Mode
To verify the device FPGA fabric and eNVM contents, type the command:
M2S_UARTHost_Loader.exe isp_demo.spi 24 2
pe
Where, 24 is the Com port number and 2 is the Operation Mode: Verify.
Su
Figure 11 shows a successful verification message.
Figure 11 • ISP Verification Status
16
R e visio n 3
SmartFusion2 SoC FPGA In-System Programming Using UART Interface Demo Guide
The verification operation demonstrated is for the isp_demo.stp file that is already running in the
SmartFusion2 device. If any other .spi file is verified while the isp_demo.stp file is still running, that
verification operation fails.
If the verification fails, the command prompt displays an error message with an error code. Figure 12
shows an example error message. For more information on error codes, see "Appendix 5: Error Codes"
on page 24.
The programming files are at:
<download_folder>\sf2_isp_using_uart_interface_demo_df\host_tool_and_samples.
All of them do not pass the verification. Only the isp_demo.spi file passes the verification operation
as it matches with the SmartFusion2 device contents (isp_demo.stp). The other programming files fail
verification.
pe
rs
ed
ed
Press SW9 to reset the SmartFusion2 Development Kit to try other ISP operation modes from CMD
prompt window.
Figure 12 • ISP verification failure error message
Program Operation Mode
the
eNVM
of
the
SmartFusion2
device
using
the
Su
To program the FPGA Fabric and
isp_fabric_and_envm.spi file, type:
M2S_UARTHost_Loader.exe isp_fabric_and_envm.spi 24 1
Where, 24 is the Com port number and 1 is the Operation Mode: Program.
Revision 3
17
In-System Programming Using UART Interface
Figure 13 • ISP Program Status
ed
ed
It takes a few minutes for the ISP service to complete and the FPGA Fabric and eNVM are programmed.
Figure 13 shows a successful ISP programming result.
Press SW9 to reset the SmartFusion2 Development Kit or Power Cycle the SmartFusion2 Development
Kit.
rs
Checking if the fabric is programmed successfully
LEDs 1 to 4 blinking in the board indicates that the fabric is programmed successfully.
Checking if the eNVM is programmed successfully
pe
To check if the eNVM is programmed successfully, start any serial terminal emulation program such as:
•
HyperTerminal
•
PuTTY
•
Tera Term
The configuration for the program is:
Baud Rate: 57600
•
8 Data bits
•
1 Stop bit
•
No Parity
•
No Flow Control
Su
•
For information on configuring the serial terminal emulation programs, see the Configuring Serial
Terminal Emulation Programs Tutorial.
18
R e visio n 3
SmartFusion2 SoC FPGA In-System Programming Using UART Interface Demo Guide
rs
ed
ed
If the eNVM is programmed successfully, the serial terminal emulation program displays an operation
success message. Figure 14 shows an operation success message for eNVM programming in the
PuTTY window.
Figure 14 • ISP Program Successful
Programming Results
pe
The result shown in Figure 14 is for the isp_fabric_and_envm.spi file. Table 4 shows the possible
results for ISP Program operation mode for sample programming files provided in folder
<download_folder>\sf2_isp_using_uart_interface_demo_df\host_tool_and_samples. Not all .spi files
listed in the table are demonstrated.
Table 4 • ISP programming results
*.spi Programming File Name
eNVM Programming Result
FPGA Fabric Programming Result
The serial terminal emulation program NA
shows successful eNVM program
message
isp_fabric_only.spi
NA
isp_fabric_and_envm.spi
The serial terminal emulation program SmartFusion2 LEDs 1 to 4 blinks
shows successful eNVM program
message
Su
isp_envm_only.spi
SmartFusion2 LEDs 1 to 4 blinks
After successful ISP Program operation, the Development Kit must be reprogrammed with the original
isp_demo.stp file to try the ISP operation modes again.
Revision 3
19
In-System Programming Using UART Interface
Appendix 1: Connecting the SmartFusion2 Device to the Host
PC Through the USB to UART (FTDI) Interface
The following procedure describes how to connect the SmartFusion2 device to the Host PC through the
USB to UART (FTDI) interface using a USB A to Mini - B Cable for serial communication:
1. Connect the host PC to the J24 connector using the USB A to Mini-B cable.
Su
pe
rs
ed
ed
2. Make sure that the USB to UART bridge drivers are automatically detected. Of the four COM
ports, select the one with Location as on USD Serial Converter D. Figure 14 shows an example
Device Manager window that has the USB Serial Port and its properties showing the port
number and location. COM port number is required to run the demo design, so make a note of it.
Figure 15 • Device Manager window showing the USB Serial Port
3. Connect the jumpers as follows:
20
–
Pin 2 of J197 to pin 3 of J129
–
Pin 2 of J188 to pin 3 of J133
–
Figure 17 on page 22 shows these pin connections.
–
See Figure 18 on page 23 for location of the jumpers. These connections are required for
connecting the MMUART_1 TXD and RXD signals to the FTDI USB to UART bridge available
in SmartFusion2 Development Kit board.
R e visio n 3
SmartFusion2 SoC FPGA In-System Programming Using UART Interface Demo Guide
Appendix 2: Board Setup when Using the USB-RS232 Serial
Adapter or RS232 Cable
3RZHUVXSSO\
VZLWFK6:
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'&-DFN
WRFRQQHFW
9DGDSWHU
)ODVK3UR
&RQQHFWRU
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86%56
VHULDODGDSWHU '%56
FRQQHFWRU
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6:WRUHVHW
/('WR/('
-XPSHUVIRU008$57B
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Figure 16 • Board setup when using the USB-RS232 Serial adapter or RS232 cable
Revision 3
21
In-System Programming Using UART Interface
Appendix 3: Board setup through the USB to UART (FTDI)
interface using the USB A to Mini - B Cable
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ed
3RZHUVXSSO\
VZLWFK6:
'&-DFN
WRFRQQHFW
9DGDSWHU
3LQRI-WR3LQRI-
3LQRI-WR3LQRI-
pe
)ODVK3UR
&RQQHFWRU
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86%0LQL%&RQQHFWRU
6:WRUHVHW
/('WR/('
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Figure 17 • Board setup when using the USB to UART (FTDI) interface using the USB A to Mini - B Cable
22
R e visio n 3
SmartFusion2 SoC FPGA In-System Programming Using UART Interface Demo Guide
J230
POE CONN
J6
J10
R26
C7
R27
R25
CONN1
C6
J11
TP10
R24
R23
R21
R22
D6
D5
R36
R56
DS11 PGOOD
R52
R35
OFF
C42
6
AT FLAG
DS10
R55
C44
SC1
U15 R104
L5
C58
SC2
T2
Q18
L10
RXN0
TXP2
TXN2
Q25
Q26
Q27
TXP1
TXN1
RXN1
RXP1
TXP3
TXN3
RXP3
RXN3
C119
C120
C121
RXP0
J171
C134
J150
J148
J149
J169
J170
R219
J156
J166
J186 J182
RXN2
RXP2
D14
J192
J191
J190
J189
TS_MDIO
TS_MDC
R244
TP25
J229
1
DDR3_1P5V
TP21 R354
R355
D18
R365 C204
R366
D20
TP20
J208
J207
U61
D17
C200 C202
DVDD12
R375
D15
R350
TP24
C198
D16
R339
R346
TP12
U59
R338
C186
R353
J220
J219
1
GND
R325
U60
R356 C189
R326
C191
2P5V_LDO
J206
J205
R312
C61
R130
U20
DS22
DS25
TXN0
GND
LED8
LED5
R372 R362
R381
R380
R383
R379
Q24
R382
R378
Q23
C68
SC3
SC4
R123
J44
C71
R131
1P0V_PHY
GND
TXP0
SERDES1
REFCLK0_N
LED7
R374 R364
LED6
R373 R363
LED4
R371 R361
LED3
R370 R360
LED2
R369 R359
LED1
R368 R358
Q22
3
1
ON
R102
R103
R100
R111
R112
R150
R151
R152
R157R153
R154
C78
C79
R158R155
J80
1
J103
J112
1
J116
1
J132
C105
R243
R242
1 R247
J185
R238
R239
R240
R241
C152
C153
R189
U37
GND
J168
U45 R220
R221
1
R278
R279
C84
R170
J147
J151
C128
C129
C130
C131
J160
RS6 1
1
R670
R230
J177
TP14
J228
Q21
D11
C32
C33
R50
R80
R113
R81
R114
DS16 P1LED3
J31
DS17 P1LED2 R82
DS18 P1LED1
DS19 P1LED0 R83 DS12 P0LED3
DS13 P0LED2
DS14 P0LED1
DS15 P0LED0
4
HPOUTCLK5
R32
R46
J67
R185
C94
C95
R178
R179
R184
R182
R183
1
789
123
A
B
C
D
E
F
G
H
J
J142
1
L13
R206
R207
R212
R217
J167
C150
C151
R276
R277
POE PWR ENB
J16
R30
J15
J13
C28
C29
C67
1
J82
U36
R662
Y2
R172
R173
C91
C92
C85
C86
C87
C88
C89
C90
R205
C146
R2 C147
66
C148
C149
R274
R275
R2
86
R282
R283
U33
1P0V_PHY
R256
J211
Q20
C74
C77
C111
1
SF2 DEV KIT
R367 R357
1
R132
R137
GND
1
J152
DDR3_VTT
R377
R385
R384
B14
1
3P3V_LDO
Q15
ON
DVP-102-000400-001 REFCLK0_P
RevC
U55
C70
T1
D19
C205
B49
Su
B11
R280
R376
C184
J224
J223
2
1
B1
R281
C164 TP22
U56
A
B
C
D
E
F
G
H
KJ
L
M
N
PLLXVDDA
U54
R311
R310
3
PLLMDDRVDDA
2
1
C203
C76 C75 C73 C72 C69 C62 C60 C59
SW8
2
R159
R160
4
R149
U23
4
J81
3
1
C159
123
789
A
B
DC
E
F
G
H
J
K
L
M
N
VPP
J233
R267
R269
R268
U51
C167
789
J227
123
789
C173
123
A
B
DC
E
F
G
H
J
K
L
M
N
J226
3
R270
R226
R229
R231
R232
R234
R235
R236
R237
C162
J225
1
1
R45
R47
R48
R49
R60
R61
1
1
C66
1
3
R146
J54
R148 LED9
RST LED
J70
2
U27
SW9
R663
JTAG SEL
RS2
J117
C100
C96
C103
C104
C98
A1
Q14
J153
R218
U42
C172
R289
R319
R320
R317
R318
J234
J215 R290
R291
C187
J217 R295 J130 R187
R332
R296
R333R334
1 R299
R302
R303
R304 TP7
R305
R306
R307
R308
R309 GND
1
L12
R213
R215
RS5
A30
C63
D10
C54
TP13
SW10
R340
C192
R341
R342
1
R335
R336
C190
R337
R351 R344
R345
C195
3
R329
C188
C183
C185
R327
C177
C178
C182
J212
R322R314
R323
C181
R321
1
C180 C176
GND
U57
J222
R343
C196
R348 R349
R352 C201
J203
1
ON
U40
C114
C197
C193C194
J216
C199
HDR-RS485
R347
R328
R331
R330
U58
1
8
J218
1
1
J128
J125
RS4
J172
K23
J175
L26
J179
H26
J184
J29
J188
H30
J195
H28
J197
G29
J200
F30
J202
K25
J210
L23
J214
N23
TP29
GND_0
R143
R671 R181
R186
R188
J126 J127
J124
RS3
3
1
C37
R74
C48
R97
GND
R166
R167
R168
Y3
R180
J123
rs
C125
Q19
R271
C155
R272 R249
R273 C142
3
C40
C43
R86
7
7
U62
PCIEXVDD
AK1
C38
C51
1
2
R99
C49R87
J33 C50R88
R89
R90
R106
R107
R108
R109
R110
R95
C52 R91
C53 R92
R93
R94
J29
J19
GND
J37
J59
U31
1
J107
J108
3
3
J139
P24
J141
N26
J144
M27
J146
L29
J155
L28
J159
K30
J162
J27
1
1
1
V2J21 M2 J20 M2J20 H2 J19G3 J196 H2J19 J2 J18 J3 J18 J2 J17 K2 J174
9 4 8 7 0 3 6 8 4
63 4 9 5 1 7 9 0
20
J221
R177
L8
PLLFDDRVDDA
R674
R673
R672
R676
pe
19
1
C175
R315
J14
J12
SW1
R53
R54
R39
SW4
U8
J26
J28
1
J38
J43
J55
1
U25
1
U30
R163
U29
1
1
J193
C160
R288
L15 C171
1 C174
R313
R316
C179
R324
L7
R175
AK30
1
Y1
3
R203
R204
D12
1
R202
R287
C143
U53
R293
R300R294
3
1
U48
C165
U52
J173
J180
C97
C101 C102
A14
P14
D7
U10
R69
R70
R73
R78
C46
J49
C80
2
1
50 MHZ
85
R2
R248
R255
C144
R264 C161
C163
J204
R190
C110
C108
R193
DS27
C112
HVDD
C117
C118
R200 R197
R199
C123
C124
J157
TP28
TP27
R261 C139
R262 R245
C154
R263
R208
R209
R210
R211
C127
U47
1
C145
R259
R260R250
J176
J198
U49
C158
C141
R251
5
R284
3
J105
J104
R176
C93
U22
C39
Q13
P3LED2
TC2 P3LED3
TC1
TC4 P3LED1
J32 P3LED0 TC3
TC6 P2LED3
P2LED2 TC5
TC7 P2LED0
R121
A1
R161 R162
TP3
C99
P1
REFCLK0_P
REFCLK0_N
SERDES0
65
R2
DB9-RS232 1
ANALOG INPUT
L14
R227
C140
R246 R254
HVDD R252 R253
R257 R258 R233
J181 C156 C157
1
TP26
VDDIO
R292
C168
R298 R297
C170 R301
1
J138
P23
J140
N25
J143
N24
J145
M26
J154
L30
J158
K29
C133 J161
K28
1
J165
C81
C82
U28
R680
R681
R678
R679
R677
R675
DS26
HVSS
U39
U38
C126
4
3
C138
C169C166 U50
J164
U46
2
J163
C137
5
R224 U44
R228
1
C136
C113
J137
D13
HVSS
R223
R225
C132
1
P1
C135
J121
5
J113
USB MICRO AB
OTG Support
1
R222
R216
1
R196
R198
1
CR4
R214
C106
R194
J94
1
U19
R28
10
U43
CR3
R195
U41
W28
R29
R24
RESET
4
3
J111
V24
J115
AA29
J119
Y30
J122
M23
J131
T27
J134
T26
J135
V23
J232
U24
20
4
C122
R201
TP5
C107
1 J93
ZL RST
GND
J30
1
1
R117
R118
R119
R122
R125
R126
R127
R129
R133
R135
R136
R138
R139
R141
R144
R145
R85
3
C115
C116
J106
1
M12
R59
TP30
GND_C
2
L11
R191
-
-
9
R76
SW6
R58
L4
R64
R66
R68
A12
TP11
J231
R51
U9
1
C109
3
12
J4
6
U34
L9
TP4
J48 J41 J39
L6
C83
R174
J120
1
V22
J110
AA28
J114
W27
J118
TP8
DS24
U26
J63
J99
J102
J101
J100
J98
J91
J88
J60
J66
R171
R147
SFP CONN
A1 R62
R65
GND
R134
10
FP4 HEADER
J79
U32
J83
J92
R165
GND
1
R664
R169 1
1
U35
U69 1
J78
J84
J89 J90
J136
DB9-CAN2
J77
J87
GND
1
R192
J42
5
1
J75
J61
J95
6
1
J69 J64
J74
REMOTE
PWR ENB
DS23
1
19 R128
GND
2
17
5
J62
J68
R156
J73
J76
1
J34
J86
J97
R164
J40
J53
J96
Q17
10
J58
J65
J85
2
9
J45
R142
J71
J109
U12
J27
C55
U17
C64
C65
J57
R140
20
J56
3
1
U21
X1
U24
19
J51
1
U18
J47
J50
2
7
20
ed
ed
R29
SW3
C35
R105
R120
J46
20 R115
1
TP2
R67
R71
R72
R75
R77
R79
R84
REFP6
ETM HEADER
RS1
J35
J72
1
R63
R44
D8
R98 U11
D9
C56
1
DS21
GND
R124
R41
C30
R42
C31
R43
J18
DB9-CAN1
R116
1
DS20
2
1
5
TP15
R101
TP19
C57
1.2V
VDD_REG
J36
J52
REFP5
C47
C45
3P3V_LDO
U16
M1
J20
3
J21
3
J22
3
J25
3
RVI HEADER
U14
U13
1
J23
Q10
J17
R38
R33
C25
C26
C34
Q12
12
J5
J7
U7
5
1
CR2
FTDI INTERFACE
R96
J24
1
6
17
C20
U4
C27
1.0V
CR1
1
7
C694
1
C21
R37
C23
C24
R14
R13
C13
C19
R31
D1
R34
3
C41
1
SW2
SW5
C1
C22
C18
U5
R57
USB MINI B
SW7
J1
HPDIFFN4 HPDIFFP4
FMC HEADER
3P3V
DS8
DS9
DS7
C10
C17
10
4
ON
TP1
R10
R9
Q11
L3
U6
1
J9
1
GND
C16
2P5V
TP18
Q8
J8
1
C14
C15
1
R40
J3
C3
C4
3P3V
R17
R18
R19
R20
C12
1P8V
6
Q7
1
C693
D3
R15
D2
D4
C682
R16
L2
TP23
OFF
FMC HEADER
L1
TP17
3
A1
A40
7
1
7
C11
C9
1
DC JACK12V/6A
12P0V
DS4
DS5
DS6
5P0V
VDD_REG
R5 2P5V
Q5
R6
Q4
U1
R12
R11 C2
U3
C8
Q6
R4 2P5V_LDO
DS3
R3 3P3V_LDO
R1 1P8V
R2 DDR3-1P5V
DS2
Q1
Q2
12V_POE
Q3
12V
R8
R7
GND
R669
K1
1
12V_PCIE
R668
5P0V
TP16
C36
C683
R660
TP9
U2
12_DCJACK
Q9
K40
1
J2
1
DS1
Appendix 4: Jumper Locations
Figure 18 • SmartFusion2 Development Kit Silkscreen Top View
Figure 18 shows the jumper locations in Development Kit board.
Notes:
•
Jumpers highlighted in red are set by default.
•
Jumpers highlighted in green must be set manually.
•
The location of the jumpers in Figure 18 are searchable.
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In-System Programming Using UART Interface
Appendix 5: Error Codes
Table 5 • Error Codes
Error Code
#define
Description
#define MSS_SYS_CHAINING_MISMATCH
Device contents mismatch
2
#define MSS_SYS_UNEXPECTED_DATA_RECEIVED
Data is not supported
3
#define MSS_SYS_INVALID_ENCRYPTION_KEY
Invalid encryption key
11
#define MSS_SYS_UNSUPPORTED_BITSTREAM_PROT_VER bitstream is not supported
12
#define MSS_SYS_VERIFY_NOT_PERMITTED_ON_BITSTR
Verification is not allowed for
input bitstream
127
#define MSS_SYS_ABORT
operation aborted
129
#define MSS_SYS_NVM_VERIFY_FAILED
eNVM verification failed
130
#define MSS_SYS_DEVICE_SECURITY_PROTECTED
Device is secured
131
#define MSS_SYS_PROGRAMMING_MODE_NOT_ENABLED
Programming mode is not
enabled.
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SmartFusion2 SoC FPGA In-System Programming Using UART Interface Demo Guide
Appendix 6: Generating .spi Programming File using Libero
1. Launch the Libero SoC software to open a Libero project for isp_fabric_and_envm.spi
programming file. The Libero design file is provided in
<download_folder>\sf2_isp_using_uart_interface_demo_df\host_tool_and_samples\fabric_and_
envm.
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2. Right-click Export Programming File under Handoff Design for Production in the Design
Flow tab, and click Configure Options from the context menu..
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Figure 19 • Configuring Export Programming File
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In-System Programming Using UART Interface
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3. On the Export Programming File Options window, select the SPI file check box.
4. Click OK.
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Figure 20 • Export Programming File Options window
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5. Double-click Export Programming File under Handoff Design for Production in the Design
Flow tab to generate the .spi file (Figure 19 on page 25). Figure 21 shows the .spi file location
in Reports tab.
Figure 21 • .SPI File Location
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A – List of Changes
The following table lists critical changes that were made in each revision of the chapter in the demo
guide.
Date
Changes
Page
Updated the document for Libero v11.3 software release (SAR 56619).
Revision 2
(December 2013)
Updated "Demo Design Description" section (SAR 53451).
Revision 1
(December 2013)
Updated the document for Libero v11.2 software release (SAR 52962).
NA
Revision 0
(July 2013)
Initial release
NA
NA
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Revision 3
(May 2014)
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B – Product Support
Microsemi SoC Products Group backs its products with various support services, including Customer
Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.
This appendix contains information about contacting Microsemi SoC Products Group and using these
support services.
Customer Service
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Contact Customer Service for non-technical product support, such as product pricing, product upgrades,
update information, order status, and authorization.
From North America, call 800.262.1060
From the rest of the world, call 650.318.4460
Fax, from anywhere in the world, 408.643.6913
Customer Technical Support Center
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Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled
engineers who can help answer your hardware, software, and design questions about Microsemi SoC
Products. The Customer Technical Support Center spends a great deal of time creating application
notes, answers to common design cycle questions, documentation of known issues, and various FAQs.
So, before you contact us, please visit our online resources. It is very likely we have already answered
your questions.
Technical Support
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Visit the Customer Support website (www.microsemi.com/soc/support/search/default.aspx) for more
information and support. Many answers available on the searchable web resource include diagrams,
illustrations, and links to other resources on the website.
Website
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You can browse a variety of technical and non-technical information on the SoC home page, at
www.microsemi.com/soc.
Contacting the Customer Technical Support Center
Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be
contacted by email or through the Microsemi SoC Products Group website.
Email
You can communicate your technical questions to our email address and receive answers back by email,
fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.
We constantly monitor the email account throughout the day. When sending your request to us, please
be sure to include your full name, company name, and your contact information for efficient processing of
your request.
The technical support email address is [email protected].
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SmartFusion2 SoC FPGA In-System Programming Using UART Interface Demo Guide
My Cases
Microsemi SoC Products Group customers may submit and track technical cases online by going to My
Cases.
Outside the U.S.
Customers needing assistance outside the US time zones can either contact technical support via email
([email protected]) or contact a local sales office. Sales office listings can be found at
www.microsemi.com/soc/company/contact/default.aspx.
ITAR Technical Support
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For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms
Regulations (ITAR), contact us via [email protected]. Alternatively, within My Cases, select
Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR
web page.
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Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
E-mail: [email protected]
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capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif. and has
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