PHILIPS ISP1362BD

ISP1362
Single-chip Universal Serial Bus On-The-Go controller
Rev. 03 — 06 January 2004
Product data
1. General description
The ISP1362 is a single-chip Universal Serial Bus (USB) On-The-Go (OTG) controller
integrated with the advanced Philips Slave Host Controller (PSHC) and the Philips
ISP1181B Device Controller (DC). The USB OTG controller is compliant with
On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0a. The host and device
controllers are compliant with Universal Serial Bus Specification Rev. 2.0, supporting
data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s).
The ISP1362 has two USB ports: port 1 and port 2. Port 1 can be hardware
configured to function as a downstream port, an upstream port or an OTG port
whereas port 2 can only be used as a downstream port. The OTG port can switch
roles from host to peripheral, or from peripheral to host. The OTG port can become a
host through the Host Negotiation Protocol (HNP) as specified in the OTG
supplement.
A USB product with OTG capability can function either as a host or as a peripheral.
For instance, with this dual-role capability, a Personal Computer (PC) peripheral such
as a printer may switch roles from a peripheral to a host for connecting to a digital
camera so that the printer can print pictures taken by the camera without using a PC.
When a USB product with OTG capability is inactive, the USB interface is turned off.
This feature has made OTG a technology well-suited for use in portable
devices—such as, Personal Digital Assistant (PDA), Digital Still Camera (DSC) and
mobile phone—in which power consumption is a concern. The ISP1362 is an OTG
controller designed to perform such functions.
2. Features
■ Complies fully with:
◆ Universal Serial Bus Specification Rev. 2.0
◆ On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0a
■ Supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
■ Adapted from Open Host Controller Interface Specification for USB Release 1.0a
■ USB OTG:
◆ Supports Host Negotiation Protocol (HNP) and Session Request Protocol
(SRP) for OTG dual-role devices
◆ Provides status and control signals for software implementation of HNP and
SRP
◆ Provides programmable timers required for HNP and SRP
◆ Supports built-in and external source of VBUS
◆ Output current of the built-in charge pump is adjustable by using an external
capacitor
ISP1362
Philips Semiconductors
Single-chip USB OTG controller
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
USB host:
◆ Supports integrated physical 4096 bytes of multiconfiguration memory
◆ Supports all four types of USB transfers: control, bulk, interrupt and
isochronous
◆ Supports multiframe buffering for isochronous transfer
◆ Supports automatic interrupt polling rate mechanism
◆ Supports paired buffering for bulk transfer
◆ Directly addressable memory architecture; memory can be updated on-the-fly
USB device:
◆ Supports high performance USB interface device with integrated Serial
Interface Engine (SIE), buffer memory and transceiver
◆ Supports fully autonomous and multiconfiguration DMA operation
◆ Supports up to 14 programmable USB endpoints with 2 fixed control IN/OUT
endpoints
◆ Supports integrated physical 2462 bytes of multiconfiguration memory
◆ Supports endpoints with double buffering to increase throughput and ease
real-time data transfer
◆ Supports controllable LazyClock (110 kHz ± 50 %) output during ‘suspend’
Supports two USB ports: port 1 and port 2
◆ Port 1 can be configured to function as a downstream port, an upstream port
or an OTG port
◆ Port 2 can be used only as a downstream port
Supports software-controlled connection to the USB bus (SoftConnect™)
Supports good USB connection indicator that blinks with traffic (GoodLink™)
Complies with USB power management requirements
Supports internal power-on and low-voltage reset circuit, with possibility of a
software reset
Supports operation over the extended USB voltage range (4.0 V to 5.5 V) with
5 V tolerant I/O pads
High-speed parallel interface to most CPUs available in the market, such as
Hitachi SH-3, Intel® StrongARM®, Philips XA, Fujitsu SPARClite®, NEC and
Toshiba MIPS, ARM7/9, Motorola DragonBall™ and PowerPC™ Reduced
Instruction Set Computer (RISC):
◆ 16-bit data bus
◆ 10 Mbyte/s data transfer rate between the microprocessor and ISP1362
Supports Programmed I/O (PIO) or Direct Memory Access (DMA)
Supports ‘suspend’ and remote wake-up
Uses 12 MHz crystal or direct clock source with on-chip Phase-Locked Loop
(PLL) for low Electro-Magnetic Interference (EMI)
Operates at +3.3 V power supply
Operating temperature range from −40 °C to +85 °C
Available in 64-pin LQFP and TFBGA packages.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
2 of 150
ISP1362
Philips Semiconductors
Single-chip USB OTG controller
3. Applications
The ISP1362 can be used to implement a dual-role USB device in any
application—USB host or USB peripheral—depending on the cable connection. If the
dual-role device is connected to a typical USB peripheral, it behaves like a typical
USB host. The dual-role device, however, can also be connected to a PC or any other
USB host and behave like a typical USB peripheral.
3.1 Host/peripheral roles
■ Mobile phone to/from:
◆ Mobile phone: exchange contact information
◆ Digital still camera: e-mail pictures or upload pictures to the web
◆ MP3 player: upload, download and broadcast music
◆ Mass storage: upload and download files
◆ Scanner: scan business cards
■ Digital still camera to/from:
◆ Digital still camera: exchange pictures
◆ Mobile phone: e-mail pictures, upload pictures to the web
◆ Printer: print pictures
◆ Mass storage: store pictures
■ Printer to/from:
◆ Digital still camera: print pictures
◆ Scanner: print scanned image
◆ Mass storage: print files stored in a device
■ MP3 player to/from:
◆ MP3 player: exchange songs
◆ Mass storage: upload and download songs
■ Oscilloscope to/from:
◆ Printer: print screen image
■ Personal digital assistant to/from:
◆ Personal digital assistant: exchange files
◆ Printer: print files
◆ Mobile phone: upload and download files
◆ MP3 player: upload and download songs
◆ Scanner: scan pictures
◆ Mass storage: upload and download files
◆ Global Positioning System (GPS): obtain directions, mapping information
◆ Digital still camera: upload pictures
◆ Oscilloscope: configure oscilloscope.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
3 of 150
ISP1362
Philips Semiconductors
Single-chip USB OTG controller
4. Abbreviations
DC — Device Controller
DMA — Direct Memory Access
DSC — Digital Still Camera
EMI — Electro-Magnetic Interference
GPS — Global Positioning System
HC — Host Controller
HCD — Host Controller Driver
HNP — Host Negotiation Protocol
OTG — On-The-Go
PDA — Personal Digital Assistant
PIO — Programmed Input/Output
PLL — Phase-Locked Loop
PSHC — Philips Slave Host Controller
SIE — Serial Interface Engine
SRP — Session Request Protocol
USB — Universal Serial Bus.
5. Ordering information
Table 1:
Ordering information
Type number
Package
Name
Description
Version
ISP1362BD
LQFP64
plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
ISP1362EE
TFBGA64
plastic thin fine-pitch ball grid array package; 64 balls; body 6 x 6 x 0.8 mm SOT543-1
ISP1362EE/01
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
4 of 150
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X1
44
32
RESET
internal
reset
POWER-ON
RESET
HC BUFFER
MEMORY
CLKOUT
43
38
ISP1362
PLL
33
H_SUSPEND/
H_WAKEUP
16
to system
clock
2, 3,
5 to 8,
10 to 13,
15 to 18,
63, 64
ADVANCED PHILIPS
SLAVE HOST
CONTROLLER
OVERCURRENT
PROTECTION
D0 to D15
Rev. 03 — 06 January 2004
RD
CS
WR
A0
A1
DACK1
DACK2
DREQ1
DREQ2
INT1
INT2
20
21
22
61
62
28
29
24
25
30
31
ON-THE-GO
CONTROLLER
BUS
INTERFACE
OTG
TRANSCEIVER
46
47
49
50
VDD_5V
H_PSW1
H_PSW2
H_OC1
H_OC2
H_DM2
H_DP2
OTG_DM1
OTG_DP1
PHILIPS DEVICE
CONTROLLER
CHARGE
PUMP
23
59
60
DC BUFFER
MEMORY
DGND
51
AGND
4, 14, 26,
40, 52, 58
VCC
34
D_SUSPEND/
D_WAKEUP
55
VBUS
GOODLINK
39
GL
45
48
ID
OTGMODE
54
CP_CAP2
53
CP_CAP1
004aaa044
ISP1362
5 of 150
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
1, 9, 19, 27,
37, 57
Fig 1. Block diagram.
USB
TRANSCEIVER
56
35
36
42
41
Single-chip USB OTG controller
TEST0
TEST1
TEST2
Philips Semiconductors
X2
6. Block diagram
9397 750 12337
Product data
12 MHz
ISP1362
Philips Semiconductors
Single-chip USB OTG controller
7. Pinning information
49 OTG_DM1
50 OTG_DP1
51 AGND
52 VCC
53 CP_CAP1
54 CP_CAP2
55 VBUS
56 VDD_5V
57 DGND
58 VCC
59 TEST1
60 TEST2
61 A0
62 A1
63 D0
64 D1
7.1 Pinning
DGND 1
48 ID
D2 2
47 H_DP2
D3 3
46 H_DM2
VCC 4
45 OTGMODE
D4 5
44 X2
D5 6
43 X1
D6 7
42 H_OC1
D7 8
41 H_OC2
ISP1362BD
DGND 9
40 VCC
D8 10
39 GL
D9 11
38 CLKOUT
RESET 32
INT2 31
INT1 30
DACK2 29
DACK1 28
VCC 26
DGND 27
DREQ2 25
33 H_SUSPEND/H_WAKEUP
DREQ1 24
D13 16
TEST0 23
34 D_SUSPEND/D_WAKEUP
WR 22
D12 15
CS 21
35 H_PSW1
RD 20
VCC 14
D15 18
36 H_PSW2
DGND 19
37 DGND
D11 13
D14 17
D10 12
004aaa050
Fig 2. Pin configuration LQFP64.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
6 of 150
ISP1362
Philips Semiconductors
Single-chip USB OTG controller
004aaa151
K
J
H
G
ISP1362EE
ISP1362EE/01
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9 10
ball A1
index area
Fig 3. Pin configuration TFBGA64.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
7 of 150
ISP1362
Philips Semiconductors
Single-chip USB OTG controller
7.2 Pin description
Table 2:
Pin description
Symbol[1]
Pin
LQFP64
Ball
TFBGA64
Type[2]
Description
DGND
1
B1
-
digital ground
D2
2
C2
I/O
bit 2 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, three-state output
D3
3
C1
I/O
bit 3 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, three-state output
VCC
4
D2
-
supply voltage (3.3 V); it is recommended to connect a decoupling
capacitor of 0.01 µF
D4
5
D1
I/O
bit 4 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, three-state output
D5
6
E2
I/O
bit 5 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, three-state output
D6
7
E1
I/O
bit 6 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, three-state output
D7
8
F2
I/O
bit 7 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, three-state output
DGND
9
F1
-
digital ground
D8
10
G2
I/O
bit 8 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, three-state output
D9
11
G1
I/O
bit 9 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, three-state output
D10
12
H2
I/O
D11
13
H1
I/O
bit 10 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
bit 11 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
8 of 150
ISP1362
Philips Semiconductors
Single-chip USB OTG controller
Table 2:
Pin description…continued
Symbol[1]
Pin
LQFP64
Ball
TFBGA64
Type[2]
Description
VCC
14
J2
-
supply voltage (3.3 V); it is recommended to connect a decoupling
capacitor of 0.01 µF
D12
15
J1
I/O
bit 12 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
D13
16
K1
I/O
bit 13 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
D14
17
K2
I/O
bit 14 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
D15
18
J3
I/O
DGND
19
K3
-
digital ground
RD
20
J4
I
read strobe input; when asserted LOW, it indicates that the HC/DC
driver is requesting a read to the buffer memory or the internal
registers of the HC/DC
CS
21
K4
I
bidirectional, push-pull input, three-state output
bit 15 of the bidirectional data bus that connects to the internal
registers and buffer memory of the ISP1362; the bus is in the
high-impedance state when it is idle
bidirectional, push-pull input, three-state output
input with hysteresis
chip select input (active LOW); enables the HC/DC driver to access
the buffer memory and registers of the HC/DC
input
WR
22
J5
I
write strobe input; when asserted LOW, it indicates that the HC/DC
driver is requesting a write to the buffer memory or the internal
registers of the HC/DC
input with hysteresis
TEST0
23
K5
I/O
for test input and output; pulled HIGH by a 100 kΩ resistor
bidirectional, push-pull input, three-state output
DREQ1
24
J6
O
DMA request output; when active, it signals the DMA controller that a
data transfer is requested by the HC; the active level (HIGH or LOW)
of the request is programmed by using the HcHardwareConfiguration
register (20H/A0H)
If the OneDMA bit of the HcHardwareConfiguration register is set to
logic 1, both the HC and DC DMA channel will be routed to DREQ1
and DACK1.
push-pull output
DREQ2
25
K6
O
DMA request output; when active, it signals the DMA controller that a
data transfer is requested by the DC; the active level (HIGH or LOW)
of the request is programmed by using the DcHardwareConfiguration
register (BAH/BBH)
push-pull output
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
9 of 150
ISP1362
Philips Semiconductors
Single-chip USB OTG controller
Table 2:
Pin description…continued
Symbol[1]
Pin
LQFP64
Ball
TFBGA64
Type[2]
Description
VCC
26
J7
-
supply voltage (3.3 V); it is recommended to connect a decoupling
capacitor of 0.01 µF
DGND
27
K7
-
digital ground
DACK1
28
J8
I
DMA acknowledge input; indicates that a request for DMA transfer
from the HC has been granted by the DMA controller; the active level
(HIGH or LOW) of the acknowledge signal is programmed by using the
HcHardwareConfiguration register (20H/A0H); when not in use, this
pin must be connected to VCC through a 10 kΩ resistor
input with hysteresis
DACK2
29
K8
I
INT1
30
J9
O
DMA acknowledge input; indicates that a request for DMA transfer
from the DC has been granted by the DMA controller; the active level
(HIGH or LOW) of the acknowledge signal is programmed by using the
DcHardwareConfiguration register (BAH/BBH); when not in use, this
pin must be connected to VCC through a 10 kΩ resistor
input with hysteresis
interrupt request from the HC; provides a mechanism for the HC to
interrupt the microprocessor; see HcHardwareConfiguration register
(20H/A0H) Section 15.4.1 for details
If the OneINT bit of the HcHardwareConfiguration register is set to
logic 1, both the HC and DC interrupt request will be routed to INT1.
push-pull output
INT2
31
K9
O
interrupt request from the DC; provides a mechanism for the DC to
interrupt the microprocessor; see DcHardwareConfiguration register
(BAH/BBH) Section 16.1.4 for details
push-pull output
RESET
32
K10
I
reset input
input with hysteresis and internal pull-up resistor
H_SUSPEND/
H_WAKEUP
33
J10
I/O
I/O pin (open-drain); goes HIGH when the HC is in the ‘suspend’
mode; a LOW pulse must be applied to this pin to wake up the HC;
connect a 100 kΩ resistor to VCC
bidirectional, push-pull input, three-state open-drain output
D_SUSPEND/
D_WAKEUP
34
H9
I/O
I/O pin (open-drain); goes HIGH when the DC is in the ‘suspend’
mode; a LOW pulse must be applied to this pin to wake up the DC;
connect a 100 kΩ resistor to VCC
bidirectional, push-pull input, three-state open-drain output
H_PSW1
35
H10
O
connects to the external PMOS switch; required when the external
charge pump or external VBUS is used for providing VBUS to the
downstream port
LOW — switches ON the PMOS providing VBUS to the downstream
port
HIGH — switches OFF the PMOS
when not in use, leave this pin open
open-drain output
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
10 of 150
ISP1362
Philips Semiconductors
Single-chip USB OTG controller
Table 2:
Pin description…continued
Symbol[1]
H_PSW2
Pin
LQFP64
36
Ball
TFBGA64
G9
Type[2]
Description
O
connects to the external PMOS switch
LOW — switches ON the PMOS providing VBUS to the downstream
port
HIGH — switches OFF the PMOS
when not in use, leave this pin open
open-drain output
DGND
37
G10
-
digital ground
CLKOUT
38
F9
O
programmable clock output; the default clock frequency is 12 MHz and
can be varied from 3 MHz to 48 MHz
push-pull output
GL
39
F10
O
GoodLink LED indicator output; the LED is OFF by default, blinks ON
upon USB traffic
VCC
40
E9
-
supply voltage (3.3 V); it is recommended to connect a decoupling
capacitor of 0.01 µF
H_OC2
41
E10
I
overcurrent sense input for downstream port 2; both the digital and
analog overcurrent inputs can be used for port 2, depending on the
hardware mode register setting; when not in use, it is recommended to
connect this pin to the VDD_5V pin
H_OC1
42
D9
I
overcurrent sensing input for downstream port 1; both the digital and
analog overcurrent inputs can be used for port 1, depending on the
hardware mode register setting; when not in use, it is recommended to
connect this pin to the VDD_5V pin
X1
43
D10
AI
crystal input; connected directly to a 12 MHz crystal; when this pin is
connected to an external clock oscillator, leave pin X2 open
X2
44
C9
AO
crystal output; connected directly to a 12 MHz crystal; when pin X1 is
connected to an external clock oscillator, leave this pin open
OTGMODE
45
C10
I
to select whether port 1 is operating in the OTG or non-OTG mode;
see Table 8
H_DM2
46
B9
AI/O
downstream D− signal; host only, port 2; when not in use, leave this
pin open and set bit ConnectPullDown_DS2 of the
HcHardwareConfiguration register
H_DP2
47
B10
AI/O
downstream D+ signal; host only, port 2; when not in use, leave this
pin open and set bit ConnectPullDown_DS2 of the
HcHardwareConfiguration register
ID
48
A10
I
input pin for sensing OTG ID; the status of this input pin is reflected in
the OTGStatus register (bit 0); see Table 8
open-drain output; 4 mA
input with hysteresis
input with hysteresis
OTG_DM1
49
A9
AI/O
D− signal of the OTG port, the downstream host port 1 or the
upstream device port; when not in use, leave this pin open and set
bit ConnectPullDown_DS1 of the HcHardwareConfiguration register[3]
OTG_DP1
50
B8
AI/O
D+ signal of the OTG port, the downstream host port 1 or the
upstream device port; when not in use, leave this pin open and set
bit ConnectPullDown_DS1 of the HcHardwareConfiguration register[3]
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
11 of 150
ISP1362
Philips Semiconductors
Single-chip USB OTG controller
Table 2:
Pin description…continued
Symbol[1]
Pin
LQFP64
Ball
TFBGA64
Type[2]
Description
AGND
51
A8
-
analog ground; used for OTG ATX
VCC
52
B7
-
supply voltage (3.3 V); it is recommended to connect a decoupling
capacitor of 0.01 µF
CP_CAP1
53
A7
AI/O
charge pump capacitor pin 1; low ESR; see Section 11.6
CP_CAP2
54
B6
AI/O
charge pump capacitor pin 2; low ESR; see Section 11.6
VBUS
55
A6
I/O
analog input and output
OTG mode — built-in charge pump output or VBUS voltage
comparators input; connect to pin VBUS of the OTG connector
DC mode — input as VBUS sensing; connect to pin VBUS of the
upstream connector
HC mode — not used; leave open
VDD_5V
56
B5
I
supply reference voltage (5 V); to be used together with built-in
overcurrent circuit; when built-in overcurrent circuit is not in use, this
pin can be tied to VCC; it is recommended to connect a decoupling
capacitor of 0.01 µF
DGND
57
A5
-
digital ground
VCC
58
B4
-
supply voltage (3.3 V); it is recommended to connect a decoupling
capacitor of 0.01 µF
TEST1
59
A4
I/O
for test input and output, pulled to GND by a 10 kΩ resistor
bidirectional, push-pull input, three-state output
TEST2
60
B3
I/O
for test input and output, pulled to GND by a 10 kΩ resistor
bidirectional, push-pull input, three-state output
A0
61
A3
I
A1
62
B2
I
command or data phase
input
LOW — PIO bus of the HC is selected
HIGH — PIO bus of the DC is selected
input
D0
63
A2
I/O
bit 0 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, three-state output
D1
64
A1
I/O
bit 1 of the bidirectional data bus that connects to the internal registers
and buffer memory of the ISP1362; the bus is in the high-impedance
state when it is idle
bidirectional, push-pull input, three-state output
[1]
[2]
[3]
Symbol names with an overscore (for example, NAME) represent active LOW signals.
All I/O pads are 5 V tolerant.
In the OTG mode, this pin is pulled down by an internal resistor.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 12337
Product data
Rev. 03 — 06 January 2004
12 of 150
ISP1362
Philips Semiconductors
Single-chip USB OTG controller
8. Functional description
8.1 On-The-Go (OTG) controller
The OTG Controller provides all the control, monitoring and switching functions
required in OTG operations.
8.2 Advanced Philips Slave Host Controller (PSHC)
The advanced Philips Slave HC is designed for highly optimized USB host
functionality. Many advanced features are integrated to fully utilize the USB
bandwidth. A number of tasks are performed at the hardware level. This reduces the
requirement on the microprocessor and thus speeds up the system.
8.3 Philips Device Controller (DC)
The Philips DC is a high performance USB device with up to 14 programmable
endpoints. These endpoints can be configured as double-buffered endpoints to
further enhance the throughput.
8.4 Phase-Locked Loop (PLL) clock multiplier
A 12 MHz-to-48 MHz clock multiplier PLL is integrated on-chip. This allows the use of
a low-cost 12 MHz crystal that also minimizes Electro-Magnetic Interference (EMI)
because of low frequency. No external components are required for the operation of
PLL.
8.5 USB and OTG transceivers
The integrated transceivers (for typical downstream port) directly interface to the USB
connectors (type A) and cables through some termination resistors. The transceiver
is compliant with Universal Serial Bus Specification Rev 2.0.
8.6 Overcurrent protection
The ISP1362 has a built-in overcurrent protection circuitry. This feature monitors the
current drawn on the downstream VBUS and switches off VBUS when the current
exceeds the current threshold. The built-in overcurrent protection feature can be used
when the port acts as a host port.
8.7 Bus interface
The bus interface connects the microprocessor to the USB host and the USB device
allowing fast and easy access to both.
8.8 DC and HC buffer memory
4096 bytes (host) and 2462 bytes (device) of built-in memory provide sufficient space
for the buffering of USB traffic. Memory in the HC is addressable by using the fast and
versatile direct addressing method.
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8.9 GoodLink
Indication of a good USB connection is provided through the GoodLink technology
(open-drain, maximum current: 4 mA). During enumeration, LED indicators blink ON
momentarily corresponding to the enumeration traffic of the ISP1362 ports. The LED
also blinks ON whenever there is valid traffic to the USB ports. In the ‘suspend’ mode,
the LED is OFF.
This feature of GoodLink provides a user-friendly indication on the status of the USB
traffic between the host and the hub, as well as the connected devices. It is a useful
diagnostics tool to isolate faulty equipment and helps to reduce field support and
hotline costs.
8.10 Charge pump
The charge pump generates a 5 V supply from 3.3 V to drive VBUS when the ISP1362
is an A-device in the OTG mode. For details, see Section 11.6.
9. Host and device bus interface
The interface between the external microprocessor and the ISP1362 Host Controller
(HC) and Device Controller (DC) is separately handled by the individual bus interface
circuitry. The host or device automux selects the path for the host access or the
device access. This selection is determined by the A1 address line. For any access
to HC or DC registers, the command phase and the data phase are needed, which is
determined by the A0 address line.
All the functionality of the ISP1362 can be accessed using a group of registers and
two buffer memory areas (one for the HC and the other the DC). Registers can be
accessed using the Programmed I/O (PIO) mode. The buffer memory can be
accessed using both the PIO and direct memory access (DMA) modes.
When CS is LOW (active), the address pin A1 has priority over DREQ and DACK.
Therefore, as long as the CS pin is held LOW, the ISP1362 bus interface does not
respond to any DACK signals. When CS is HIGH (inactive), the bus interface will
respond to DREQn and DACKn. The address pin A1 will be ignored when CS is
inactive.
An active DACKn signal when the DREQn is inactive will be ignored. If DREQ1,
DACK1, DREQ2 and DACK2 are active, the bus interface will be switched off to avoid
potential data corruption.
Table 3 provides the bus access priority for the ISP1362.
Table 3:
Bus access priority table for the ISP1362
Priority CS
A1
DACK1
DACK2
DREQ1 DREQ2 HC and DC active
1
L
L
X
X
X
X
HC
2
L
H
X
X
X
X
DC
3
H
X
L
X
H
L
HC[1]
4
H
X
X
L
L
H
DC[1]
5
H
X
X
X
H
H
no driving
[1]
Only for enabling of the bus and disabling of the bus. Depends only on the DACK signal.
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9.1 Memory organization
The buffer memory in the HC uses a multiconfigurable direct addressing architecture.
The 4096 bytes HC buffer memory is shared by the ISTL0, ISTL1, INTL and ATL
buffers. ISTL0 and ISTL1 are used for isochronous traffic (double buffer), INTL is
used for interrupt traffic, and ATL is used for control and bulk traffic.
The allocation of the buffer memory follows the sequence ISTL0, ISTL1, INTL, ATL
and unused memory. For example, consider that the buffer sizes of the ISTL, INTL
and ATL buffers are 1024 bytes, 1024 bytes and 1024 bytes, respectively. Then,
ISTL0 will start from memory location 0, ISTL1 will start from memory location 1024
(size of ISTL0), INTL will start from memory location 2048 (size of ISTL0 + size of
ISTL1) and ATL will start from memory location 3072 (size of ISTL0 + size of
ISTL1 + size of INTL).
The HCD has the responsibility to ensure that the sum of the four memory buffers
does not exceed the total memory size. If this condition is violated, it will lead to data
corruption. The buffer size must be a multiple of two bytes (one word).
The buffer memory of the DC follows a similar architecture. Details on the DC
memory area allocation can be found in Section 13.3. Note that the DC buffer
memory does not support the direct addressing mode.
9.1.1
Memory organization for the HC
The HC in the ISP1362 has a total of 4096 bytes of buffer memory. This buffer area is
divided into four parts (see Table 4 and Figure 4):
Table 4:
Buffer memory areas and their applications
Buffer memory area
Application
ISTL0 and ISTL1
isochronous transfer (double buffering)
INTL
interrupt transfer
ATL
control and bulk transfer
The ISTL0 and ISTL1 buffers must have the same size. Memory is allocated by
the HC according to the value set by the HCD in HcISTLBufferSize,
HcINTLBufferSize and HcATLBufferSize. All buffer sizes must be multiples of two
bytes (one word).
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0x0000
ISTL0 area (512 bytes)
0x03FF
0x0400
ISTL1 area (512 bytes)
0x07FF
0x0800
INTL area (512 bytes)
0x09FF
0x0A00
ATL area (1536 bytes)
0x0FFF
004aaa053
Fig 4. Recommended values of the ISP1362 buffer memory allocation.
The INTL and ATL buffers use ‘blocked memory management’ scheme to enhance
the status and control capability of each and every individual PTD structure. The INTL
and ATL buffers are further divided into blocks of equal sizes depending on the value
written to the HcATLBlkSize register (ATL) and the HcINTLBlkSize register (INTL).
The ISP1362 HC supports up to 32 blocks in the ATL and INTL buffers. Each of these
blocks can be used for one complete Philips Transfer Descriptor (PTD) data.
Note that the block size does not include the 8-byte PTD header and is strictly the
size of the payload. Both the ATL and INTL block sizes must be a multiple of DWord
(4 bytes).
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Starting address of the
ATL or INTL buffer area
8 bytes PTD header
64 bytes PTD header
Payload area
Block of 72 bytes
(64 + 8,
where 64 is the block size defined)
8 bytes PTD header
64 bytes PTD header
Payload area
72 bytes
8 bytes PTD header
64 bytes PTD header
Payload area
72 bytes
004aaa055
Fig 5. A sample snapshot of the ATL or INTL memory management scheme.
Figure 5 provides a snapshot of a sample ATL or INTL buffer area of 256 bytes with a
block size of 64 bytes. The HCD may put a PTD with payload size of up to 64 bytes
but not more. Depending on the ATL or INTL buffer size, up to 32 ATL blocks and
32 INTL blocks can be allocated. Note that a portion of the ATL or INTL buffer
remains unused. This is allowed but can be avoided by choosing the appropriate ATL
or INTL buffer size and block size.
The ISTL0 or ISTL1 buffer memory (for isochronous transfer) uses a different
memory management scheme (see Figure 6). There is no fixed block size for the
ISTL buffer memory. While the PTD header remains 8 bytes for all PTDs, the PTD
payload can be of any size. The PTD payload, however, is padded to the next DWord
boundary when the HC calculates the location of the next PTD header. The
ISP1362 HC checks the payload size from the ‘Total size’ field of the PTD itself and
calculates the location of the next PTD header based on this information.
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Starting address of ISTL0 or ISTL1
PTD header (Total size = 64)
72 bytes (64 + 8)
PTD payload (64 bytes)
PTD header (Total size = 160)
168 bytes (160 + 8)
PTD payload (160 bytes)
PTD header (Total size = 32)
PTD payload (32 bytes)
40 bytes (32 + 8)
004aaa054
‘Total size’ is a 10-bit field in the PTD.
Fig 6. A sample snapshot of the ISTL memory management scheme.
9.1.2
Memory organization for the DC
The ISP1362 DC has a total of 2462 bytes of built-in buffer memory. This buffer
memory is multiconfigurable to support the requirements of different applications. The
DC buffer memory is divided into 16 areas to be used by control OUT, control IN and
14 programmable endpoints.
Figure 7 provides a snapshot of the DC buffer memory.
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Control OUT (64 bytes)
Control IN (64 bytes)
Endpoint 1 (128 bytes)
Endpoint 2 (128 bytes)
Endpoint 3 (512 bytes)
Endpoint 4 (64 bytes)
Endpoint 5 (64 bytes)
Endpoint 6 (96 bytes)
Endpoint 7 (96 bytes)
004aaa057
Fig 7. DC buffer memory organization.
The buffer memory is configured by the DcEndpointConfiguration registers (ECRs).
Although the control endpoint has a fixed configuration, all 16 endpoints (control OUT,
control IN and 14 programmable endpoints) must be configured before the DC
internally allocates the buffer. The 14 programmable endpoints could be programmed
into sizes ranging from 16 bytes to 1023 bytes, single or double buffering.
The DC buffer memory for each endpoint can be accessed through the
DcReadEndpointBuffer and DcWriteEndpointBuffer registers.
9.2 PIO access mode
The ISP1362 provides the PIO mode for external microprocessors to access its
internal control registers and buffer memory. It occupies only four I/O ports or four
memory locations of a microprocessor. An external microprocessor can read or write
to the internal control registers and buffer memory of the ISP1362 through the PIO
operating mode. Figure 8 shows the PIO interface between a microprocessor and the
ISP1362.
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µP bus interface
D [15:0]
D [15:0]
MICROPROCESSOR
RD
RD
WR
WR
CS
CS
A2
A1
A1
A0
IRQ1
INT1
IRQ2
INT2
ISP1362
004aaa042
Fig 8. PIO interface between a microprocessor and the ISP1362.
9.3 DMA mode
The ISP1362 also provides the DMA mode for external microprocessors to access
the internal buffer memory of the ISP1362. The DMA operation enables data to be
transferred between the system memory of a microprocessor and the internal buffer
memory of the ISP1362.
Remark: The DMA operation must be controlled by the DMA controller of the external
microprocessor system (master). Figure 9 shows the DMA interface between a
microprocessor system and the ISP1362.
The ISP1362 provides two DMA channels. The DMA channel 1 (controlled by the
DREQ1 and DACK1 signals) is for the DMA transfer between the system memory of
a microprocessor and the internal buffer memory of the ISP1362 HC. The DMA
channel 2 (controlled by the DREQ2 and DACK2 signals) is for the DMA transfer
between the system memory of a microprocessor and the internal buffer memory of
the ISP1362 DC. The ISP1362 provides an internal End-Of-Transfer (EOT) signal to
terminate the DMA transfer.
µP bus interface
D [15:0]
MICROPROCESSOR
D [15:0]
RD
RD
WR
WR
DACK1
DACK1
DREQ1
DREQ1
DACK2
DACK2
DREQ2
DREQ2
ISP1362
004aaa043
Fig 9. DMA interface between a microprocessor and the ISP1362.
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9.4 PIO access to internal control registers
Table 5 shows the I/O port addressing in the ISP1362. The complete I/O port address
decoding should combine with the chip select signal (CS) and the address lines (A1
and A0). The direction of access of I/O ports, however, is controlled by the RD and
WR signals
When RD is LOW, the microprocessor reads data from the data port of the ISP1362
(see Figure 10). When WR is LOW, the microprocessor writes command to the
command port or writes data to the data port (see Figure 11).
Table 5:
I/O port addressing
CS
A1
A0
Access
Data bus width
Description
L
L
L
R/W
16 bits
HC data port
L
L
H
W
16 bits
HC command port
L
H
L
R/W
16 bits
DC data port
L
H
H
W
16 bits
DC command port
The register structure in the ISP1362 is a command-data register pair structure. A
complete register access needs a command phase followed by a data phase. The
command (also named as the index of a register) is used to inform the ISP1362 about
the register that will be accessed at the data phase.
On the 16-bit data bus of a microprocessor, a command occupies the lower byte and
the upper byte is filled with zeros (see Figure 12).
For 32-bit registers, the access cycle is shown in Figure 13. It consists of a command
phase followed by two data phases.
BUS INTERFACE
0
Host bus interface
µP bus interface
Device bus interface
1
A1
004aaa122
When A1 = L, microprocessor accesses the HC.
When A1 = H, microprocessor accesses the DC.
Fig 10. Microprocessor access to the HC or the DC.
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CMD/DATA
SWITCH
Host or Device
bus interface
1
command port
data port
Commands
0
A0
Command register
..
.
Control registers
004aaa160
When A0 = L, microprocessor accesses the data port.
When A0 = H, microprocessor accesses the command port.
Fig 11. Access to internal control registers.
Read 16-bit
Write16-bit
A0/A1
A0/A1
CS
CS
RD
WR
D[15:0]
D[15:0]
004aaa045
Fig 12. PIO register access.
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Reading from a 16/32-bit register
32-bit access
16-bit access
A0/A1
CS
RD
WR
D[15:0]
Command phase
Data phase
Second data phase
for 32-bit register
Writing to a 16/32-bit register
32-bit access
16-bit access
A0/A1
CS
RD
WR
D[15:0]
Command phase
Data phase
Second data phase
for 32-bit register
004aaa046
Fig 13. PIO access for a 16 or 32-bit register.
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The following is a sample code for PIO access to internal control registers:
unsigned long read_reg32(unsigned char reg_no)
{
unsigned int result_l,result_h;
unsigned long result;
outport(hc_com, reg_no); // Command phase
result_l=inport(hc_data); // Data phase
result_h=inport(hc_data); // Data phase
result = result_h;
result = result<<16;
result = result+result_l;
return(result);
}
void write_reg32(unsigned char reg_no, unsigned long data2write)
{
unsigned int low_word;
unsigned int hi_word;
low_word=data2write&0x0000FFFF;
hi_word=(data2write&0xFFFF0000)>>16;
outport(hc_com,reg_no|0x80); // Command phase
outport(hc_data,low_word); // Data phase
outport(hc_data,hi_word); // Data phase
}
unsigned int read_reg16(unsigned char reg_no)
{
unsigned int result;
outport(hc_com, reg_no); // Command phase
result=inport(hc_data); // Data phase
return(result);
}
void write_reg16(unsigned char reg_no, unsigned int data2write)
{
outport(hc_com,reg_no|0x80); // Command phase
outport(hc_data,data2write); // Data phase
}
9.5 PIO access to the buffer memory
The buffer memory in the ISP1362 can be addressed using either the direct
addressing method or the indirect addressing method.
9.5.1
PIO access to the buffer memory by using direct addressing
This method uses the HcDirectAddressLength register to specify two parameters
required to randomly access the ISP1362 buffer memory (total of 4096 bytes). These
two parameters are:
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Starting address — Location to start writing or reading
Data length — Number of bytes to write or read.
The following is a sample code for setting the HcDirectAddressLength register:
void Set_DirAddrLen(unsigned int data_length,unsigned int addr)
{
unsigned long RegData = 0;
RegData =(long)(addr&0x7FFF);
RegData|=(((long)data_length)<<16);
write_reg32(HcDirAddrLen,RegData);
}
After the proper value is written to the HcDirectAddressLength register, data is
accessible from the HcDirectAddressData register (called as HcDirAddr_Port in the
following sample code). A sample code for writing word_size bytes of data from
*w_ptr to the memory locations of the ISP1362 buffer starting from the address
start_addr is as follows:
void direct_write(unsigned int *w_ptr,unsigned int
start_addr,unsigned int word_size)
{
unsigned int cnt=0;
Set_DirAddrLen(word_size*2,start_addr);
outport(hc_com,HcDirAddr_Port|0x80); // hc_com is system address of
// HC command port
do
{
outport(hc_data,*(w_ptr+cnt)); // hc_data is system address of
// HC data port
cnt++;
}
while(cnt<word_size);
}
Direct addressing allows fast and random access to any location within the ISP1362
memory. Your program, however, needs the address location of each buffer area to
access them.
9.5.2
PIO access to the buffer memory by using indirect addressing
Indirect addressing is the addressing method that is compatible with the Philips
ISP1161 addressing mode. This method uses a unique data port for each buffer
memory area (ATL, INTL, ISTL0 and ISTL1). These four data areas share the
HcTransferCounter register that is used to indicate the number of bytes to be
transferred.
A sample code for writing an array at *a_ptr into the ATL memory area with word_size
as the word size is given as follows:
void write_atl(unsigned int *a_ptr, unsigned int word_size)
{
int cnt;
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write_reg16(HcTransferCnt,word_size*2);
outport(hc_com,HcATL_Port|0x80); // hc_com is system address of HC
// command port
cnt=0;
do
{
outport(hc_data,*(a_ptr+cnt));
// hc_data is system address of HC
// data port
cnt++;
}
while(cnt<(word_size));
Remark: The HcTransferCounter register counts the number of bytes even though
the transfer is in number of words. Therefore, the transfer counter should be set to
word_size × 2. Incorrect setting of the HcTransferCounter register may cause the
ISP1362 to go into an indeterminate state.
The buffer memory access using indirect addressing always starts from the location 0
of each buffer area. Only the front portion of the memory (example: first 64 bytes of a
1024 bytes buffer) can be accessed. Therefore, to access a portion of the memory
that does not start from memory location 0, all memory locations before that location
must be accessed in a sequential order. The method is similar to the sequential file
access method.
9.6 Setting up a DMA transfer
The ISP1362 uses two DMA channels to individually serve the HC and the DC. The
DMA transfer allows the system CPU to work on other tasks while the DMA controller
transfers data to or from the ISP1362. The DMA slave controller, in the ISP1362, is
compatible with the 8327 type DMA controller.
The DMA transfer can be used with the direct addressing mode or the indirect
addressing mode. The registers used in these two modes are shown in Table 6.
Table 6:
Addressing mode[1]
HcDMAConfiguration bit[3:1]
Total bytes to transfer
Direct addressing
1XXB
HcDirectAddressLength
Indirect addressing
0XXB
HcTransferCounter
[1]
9.6.1
Registers used in addressing modes
In the direct addressing mode, HcTransferCounter must be set to 0001H.
Configuring registers for a DMA transfer
To set up a DMA transfer, the following HC registers must be configured depending
on the type of transfer required:
• HcHardwareConfiguration
– DREQ1 output polarity (bit 5)
– DACK1 input polarity (bit 6)
– DACK mode (bit 8).
• HcµPInterruptEnable
– If you want an interrupt to be generated after the DMA transfer is complete, set
EOTInterruptEnable (bit 3).
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• HcµPInterrupt
– Before initiating the DMA transfer, clear AllEOTInterrupt (bit 3). This bit is set
when the DMA transfer is complete.
• HcTransferCounter
– If DMACounterEnable of the HcDMAConfiguration register is set (that is, the
DMA counter is enabled), HcTransferCounter must be set to the number of
bytes to be transferred.
• HcDMAConfiguration
– Read or write DMA (bit 0)
– Targeted buffer: ISTL0, ISTL1, ATL and INTL (bits 1 to 3)
– DMA enable or disable (bit 4)
– Burst length (bits 5 to 6)
– DMA counter enable (bit 7).
Remark: Configure the HcDMAConfiguration register only after you have configured
all the other registers. The ISP1362 will assert DREQ1 once the DMA enable bit in
this register is set.
9.6.2
Combining the two DMA channels
The ISP1362 allows systems with limited DMA channels to use a single DMA channel
(DMA1) for both the HC and the DC. This option can be enabled by writing logic 1 to
the OneDMA bit of the HcHardwareConfiguration register. If this option is enabled,
the polarity of the DC DMA and the HC DMA must be set to DACK active LOW and
DREQ active HIGH.
9.7 Interrupts
Various events in the HC, the DC and the OTG controller can be programmed to
generate a hardware interrupt. By default, the interrupt generated by the HC and the
OTG controller is routed out at the INT1 pin and the interrupt generated by the DC is
routed out at the INT2 pin.
9.7.1
Interrupt in the HC and the OTG controller
There are two levels of interrupts represented by level 1 and level 2 (see Figure 14).
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OtgInterruptEnable register
OTG_TMR_IE
B_SE0_SRP_IE
A_SRP_DET_IE
OTG_RESUME_IE
OTG_SUSPND_IE
RMT_CONN_IE
B_SESS_VLD_IE
OR
A_SESS_VLD_IE
B_SESS_END_IE
A_VBUS_VLD_IE
ID_REG_IE
OtgInterrupt register
OTG_TMR_TIMEOUT
B_SE0_SRP
level 2
(OTG group)
A_SRP_DET
OTG_RESUME
OTG_SUSPND
RMT_CONN_C
B_SESS_VLD_C
A_SESS_VLD_C
B_SESS_END_C
ATL_IRQ_InterruptEnable
ClkReady
OPRInterruptEnable
HCSuspendedEnable
EOT_InterruptEnable
ISTL_1_InterruptEnable
SOFInterruptEnable
FNO
ISTL_0_InterruptEnable
ATL_IRQ
OTG_IRQ
ClkReady
INTL_IRQ
OPR_Reg
HcSuspended
ISTL_1_INT
MIE
RHSC
AIIEOTInterrupt
SOF_INT
HcInterruptEnable register
ISTL_0_INT
ID_REG_C
OTG_IRQ_InterruptEnable
HcµPInterruptEnable register
INTL_IRQ_InterruptEnable
HcµPInterrupt register
A_VBUS_VLD_C
UE
RD
OR
SF
SO
level 2
(OPR group)
HcInterruptStatus register
RHSC
FNO
UE
OR
level 1
RD
SF
SO
HcHardwareConfiguration register
INT1
LATCH
LE
InterruptPinEnable
From INT2
004aaa395
OneINT
HcHardwareConfiguration
register
Fig 14. HC and OTG interrupt logic.
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The interrupt level 2 (OPR group) contains six possible interrupt events (recorded in
the HcInterruptStatus register). When any of these events occurs, the corresponding
bit would be set to logic 1, and if the corresponding bit in the HcInterruptEnable
register is also logic 1, the 6-input OR gate would output logic 1. This output is
combined with the value of MIE (bit 31 of HcInterruptEnable) using the AND
operation and logic 1 output at this AND gate will cause the OPR bit in the
HcµPInterrupt register to be set to logic 1.
The interrupt level 2 (OTG group) contains 11 possible interrupt events (recorded in
the OtgInterrupt register). When any of these events occurs, the corresponding bit
would be set to logic 1, and if the corresponding bit in the OtgInterruptEnable register
is also logic 1, the 11-input OR gate would output logic 1 and cause the OTG_IRQ bit
in the HcµPInterrupt register to be set to logic 1.
The level 1 interrupts contains 10 possible interrupt events. The HcµPInterrupt and
HcµPInterruptEnable registers work in the same way as the HcInterruptStatus and
HcInterruptEnable registers. The output from the 10-input OR gate is connected to a
latch, which is controlled by InterruptPinEnable (the bit 0 of HcHardwareConfiguration
register).
When the software wishes to temporarily disable the interrupt output of the
ISP1362 HC and OTGC, follow this procedure:
1. Set the InterruptPinEnable bit in HcHardwareConfiguration register to logic 1.
2. Clear all bits in the HcµPInterrupt register.
3. Set the InterruptPinEnable bit to logic 0.
To re-enable the interrupt generation, set the InterruptPinEnable bit to logic 1.
Remark: The InterruptPinEnable bit in the HcHardwareConfiguration register
controls the latch of the interrupt output. When this bit is set to logic 0, the interrupt
output will remain unchanged, regardless of any operation on the interrupt control
registers.
If INT1 is asserted, and the HCD wishes to temporarily mask off the INT signal
without clearing the HcµPInterrupt register, follow this procedure:
1. Make sure that the InterruptPinEnable bit is set to logic 1.
2. Clear all bits in the HcµPInterruptEnable register.
3. Set the InterruptPinEnable bit to logic 0.
To re-enable the interrupt generation:
1. Set all bits in the HcµPInterruptEnable register according to the HCD
requirements.
2. Set the InterruptPinEnable bit to logic 1.
9.7.2
Interrupt in the DC
The registers that control the interrupt generation in the ISP1362 DC are:
• DcMode (bit 3)
• DcHardwareConfiguration (bits 0 and 1)
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• DcInterruptEnable
• DcInterrupt.
The DcMode register (bit 3) is the overall DC interrupt enable.
DcHardwareConfiguration determines the following features:
• Level-triggered or edge-triggered (bit 1)
• Output polarity (bit 0).
For details on the interrupt logic in the DC, refer to the Interrupt Control application
note.
9.7.3
Combining INT1 and INT2
In some embedded systems, interrupt inputs to the CPU are a very scarce resource.
The system designer might want to use just one interrupt line to serve the HC, the DC
and the OTG controller. In such a case, make sure the OneINT feature is activated.
When OneINT (bit 9 of the HcHardwareConfiguration register) is set to logic 1, both
the INT1 (HC or OTG controller) interrupt and the INT2 (DC) interrupt are routed to
pin INT1, thereby reducing hardware resource requirements.
Remark: Both the host controller (or OTG controller) and the device controller
interrupts must be set to the same polarity (active HIGH or active LOW) and the same
trigger type (edge or level). Failure to conform to this will lead to unpredictable
behavior of the ISP1362.
9.7.4
Behavior difference between level-triggered and edge-triggered interrupts
In many microprocessor systems, the operating system disables an interrupt when it
is in an Interrupt Service Routine (ISR). If there is an interrupt event during this
period, it will lead to:
Level-triggered interrupt: When the ISP1362 interrupt asserts, the operating
system takes no action because it disables the interrupt when it is in the ISR. The
interrupt line of the ISP1362 remains asserted. When the operating system exits the
ISR and re-enables the interrupt processing, it sees the asserted interrupt line and
immediately enters the ISR.
Edge-triggered interrupt: When the ISP1362 outputs a pulse, the operating system
takes no action because it disables the interrupt when it is in the ISR. The interrupt
line of the ISP1362 goes back to the inactive state. When the operating system exits
the ISR and re-enables the interrupt processing, it sees no pending interrupt. As a
result, the interrupt is missed.
If the system needs to know whether an interrupt (approximately 160 ns pulse width)
occurs during this period, it may read the HcµPInterrupt register (see Table 68).
10. Power-on reset (POR)
When VCC is directly connected to the RESET pin, the internal POR pulse width
(tPORP) will be typically 800 ns. The pulse is started when VCC rises above Vtrip
(2.03 V).
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To give a better view of the functionality, Figure 15 shows a possible curve of VCC with
dips at t2–t3 and t4–t5. If the dip at t4–t5 is too short (that is, < 11 µs), the internal
POR pulse will not react and will remain LOW. The internal POR starts with a HIGH at
t0. At t1, the detector will see the passing of the trip level and a delay element will add
another tPORP before it drops to LOW.
The internal POR pulse will be generated whenever VCC drops below Vtrip for more
than 11 µs.
V CC
V trip
t0
t1
t
t2
t4
t3
t
PORP
t5
PORP (1)
PORP
004aaa482
(1) PORP = power-on reset pulse.
Fig 15. Internal power-on reset timing.
The RESET pin can be either connected to VCC (using the internal POR circuit) or
externally controlled (by the micro, ASIC, and so on). Figure 16 shows the availability
of the clock with respect to the external reset pulse.
RESET
EXTERNAL CLOCK
004aaa484
A
Stable external clock is available at A.
Fig 16. Clock with respect to the external power-on reset.
11. On-The-Go (OTG) controller
11.1 Introduction
OTG is a supplement to the Hi-Speed USB (USB 2.0) specification that augments
existing USB peripherals by adding to these peripherals limited host capability to
support other targeted USB peripherals. It is primarily targeted at portable devices
because it addresses concerns related to such devices, such as a small connector
and low power. Non-portable devices (even standard hosts), nevertheless, can also
benefit from OTG features.
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The ISP1362 OTG controller is designed to perform all the tasks specified in the OTG
supplement. It supports Host Negotiation Protocol (HNP) and Session Request
Protocol (SRP) for dual-role devices. The ISP1362 uses software implementation of
HNP and SRP for maximum flexibility. A set of OTG registers provides the control and
status monitoring capabilities to support software HNP or SRP.
Besides the normal USB transceiver, timers and analog components required by
OTG are also integrated on-chip. The analog components include:
•
•
•
•
Built-in 3.3 V-to-5 V charge pump
Voltage comparators
Pull-up or pull-down resistors on data lines
Charge or discharge resistors for VBUS.
11.2 Dual-role device
When port 1 of the ISP1362 is configured in the OTG mode, it can be used as an
OTG dual-role device. A dual-role device is a USB device that can function either as a
host or as a peripheral. As a host, the ISP1362 can support all four types of transfers
(control, bulk, isochronous and interrupt) at full-speed or low-speed. As a peripheral,
the ISP1362 can support two control endpoints and up to 14 configurable endpoints,
which can be programmed to any of the four transfer types.
The default role of the ISP1362 is controlled by the ID pin, which in turn is controlled
by the type of plug connected to the mini-AB receptacle. If ID = LOW (mini-A plug
connected), it becomes an A-device, which is a host by default. If ID = HIGH (mini-B
plug connected), it becomes a B-device, which is a peripheral by default.
Both the A-device and the B-device work on a session base. A session is defined as
the period of time in which devices exchange data. A session starts when VBUS is
driven and ends when VBUS is turned off. Both the A-device and the B-device may
start a session. During a session, the role of the host can be transferred back and
forth between the A-device and the B-device any number of times by using HNP.
If the A-device wants to start a session, it turns on VBUS by enabling the charge pump.
The B-device detects that VBUS has risen above the B_SESS_VLD level and
assumes the role of a peripheral asserting its pull-up resistor on the DP line. The
A-device detects the remote pull-up resistor and assumes the role of a host. Then,
the A-device can communicate with the B-device as long as it wishes. When the
A-device finishes communicating with the B-device, the A-device turns-off VBUS and
both the devices finally go into the idle state. See Figure 18 and Figure 19.
If the B-device wants to start a session, it must initiate SRP by ‘data line pulsing’ and
‘VBUS pulsing’. When the A-device detects any of these SRP events, it turns on its
VBUS (note that only the A-device is allowed to drive VBUS). The B-device assumes
the role of a peripheral, and the A-device assumes the role of a host. The A-device
detects that the B-device can support HNP by getting the OTG descriptor from the
B-device. The A-device will then enable the HNP hand-off by using SetFeature
(b_hnp_enable) and then go into the ‘suspend’ state. The B-device signals claiming
the host role by deasserting its pull-up resistor. The A-device acknowledges by going
into the peripheral state. The B-device then assumes the role of a host and
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communicates with the A-device as long as it wishes. When the B-device finishes
communicating with the A-device, both the devices finally go into the idle state. See
Figure 18 and Figure 19.
11.3 Session Request Protocol (SRP)
As a dual-role device, the ISP1362 can initiate and respond to SRP. The B-device
initiates SRP by data line pulsing followed by VBUS pulsing. The A-device can detect
either data line pulsing or VBUS pulsing.
11.3.1
B-device initiating SRP
The ISP1362 can initiate SRP by performing the following steps:
1. Detect initial conditions [read ID_REG, B_SESS_END and SE0_2MS (bits 0,
2 and 9) of the OtgStatus register].
2. Start data line pulsing [set LOC_CONN (bit 4) of OtgControl register to logic 1].
3. Wait for 5 ms to 10 ms.
4. Stop data line pulsing [set LOC_CONN (bit 4) of OtgControl register to logic 0].
5. Start VBUS pulsing [set CHRG_VBUS (bit 1) of the OtgControl register to logic 1].
6. Wait for 10 ms to 20 ms.
7. Stop VBUS pulsing [set CHRG_VBUS (bit 1) of the OtgControl register to logic 0].
8. Discharge VBUS for about 30 ms [by using DISCHRG_VBUS (bit 2) of the
OtgControl register], optional.
The B-device must complete both data line pulsing and VBUS pulsing within 100 ms.
11.3.2
A-device responding to SRP
The A-device must be able to respond to one of the two SRP events: data line pulsing
or VBUS pulsing. The ISP1362 allows you to choose which SRP to support and has a
mechanism to disable or enable the SRP detection. This is useful for some
applications under certain cases. For example, if the A-device battery is low, it may
not want to turn on its VBUS by detecting SRP. In this case, it may choose to disable
the SRP detection function.
When the data line SRP detection is used, the ISP1362 can detect either the
DP pulsing or the DM pulsing. This means a peripheral-only device can initiate data
line pulsing SRP through DP (full-speed) or DM (low-speed). A dual-role device will
always initiate data line pulsing SRP through DP because it is a full-speed device.
• Steps to enable the SRP detection by VBUS pulsing:
– Set A_SEL_SRP (bit 9) of the OtgControl register to logic 0.
– Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 1.
• Steps to enable the SRP detection by data line pulsing:
– Set A_SEL_SRP (bit 9) of the OtgControl register to logic 1.
– Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 1.
• Steps to disable the SRP detection:
– Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 0.
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11.4 Host Negotiation Protocol (HNP)
HNP is used to transfer control of the host role between the default host (A-device)
and the default peripheral (B-device) during a session. When the A-device is ready to
give up its role as a host, it will condition the B-device by SetFeature (b_hnp_enable)
and will go into ‘suspend’. If the B-device wants to use the bus at that time, it signals
a ‘disconnect’ to the A-device. Then, the A-device will take the role of a peripheral
and the B-device will take the role of a host.
11.4.1
Sequence of HNP events
The sequence of events for HNP as observed on the USB bus is illustrated in
Figure 17.
A-device
1
6
8
3
B-device
2
5
4
7
DP Composite
004aaa079
Legend
DP driven
Pull-up dominates
Pull-down dominates
Normal bus activity
Fig 17. HNP sequence of events.
As can be seen in Figure 17:
1. The A-device completes using the bus and stops all bus activity (that is,
suspends the bus).
2. The B-device detects that the bus is idle for more than 5 ms and begins HNP by
turning off the pull-up on DP. This allows the bus to discharge to the SE0 state.
3. The A-device detects SE0 on the bus and recognizes this as a request from the
B-device to become a host. The A-device responds by turning on its DP pull-up
within 3 ms of first detecting SE0 on the bus.
4. After waiting for 30 µs to ensure that the DP line is not HIGH because of the
residual effect of the B-device pull-up, the B-device notices that the DP line is
HIGH and the DM line is LOW (that is, J state). This indicates that the A-device
has recognized the HNP request from the B-device. At this point, the B-device
becomes a host and asserts bus reset to start using the bus. The B-device must
assert the bus reset (that is, SE0) within 1 ms of the time that the A-device turns
on its pull-up.
5. When the B-device completes using the bus, it stops all bus activity. Optionally,
the B-device may turn on its DP pull-up at this time.
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6. The A-device detects lack of bus activity for more than 3 ms and turns off its
DP pull-up. Alternatively, if the A-device has no further need to communicate with
the B-device, the A-device may turn off VBUS and end the session.
7. The B-device turns on its pull-up.
8. After waiting 30 µs to ensure that the DP line is not HIGH because of the residual
effect of the A-device pull-up, the A-device notices that the DP-line is HIGH (and
the DM line is LOW) indicating that the B-device is signaling a connect and is
ready to respond as a peripheral. At this point, the A-device becomes a host and
asserts the bus reset to start using the bus.
11.4.2
OTG state diagrams
Figure 18 and Figure 19 show the state diagrams for the dual-role A-device and the
dual-role B-device, respectively. For a detailed explanation, refer to On-The-Go
Supplement to the USB 2.0 Specification Rev. 1.0a.
The OTG state machine is implemented with software. The inputs to the state
machine come from four sources: hardware signals from the USB bus, software
signals from the application program, internal variables with the state machines and
timers:
• Hardware inputs: Include id, a_vbus_vld, a_sess_vld, b_sess_vld, b_sess_end,
a_conn, b_conn, a_bus_suspend, b_bus_suspend, a_bus_resume,
b_bus_resume, a_srp_det and b_se0_srp. All these inputs can be derived from
the OtgInterrupt and OtgStatus registers.
• Software inputs: Include a_bus_req, a_bus_drop and b_bus_req.
• Internal variables: Include a_set_b_hnp_en, b_hnp_enable and b_srp_done.
• Timers: The HNP state machine uses four timers: a_wait_vrise_tmr,
a_wait_bcon_tmr, a_aidl_bdis_tmr and b_ase0_brst, tmr. All timers are started on
entry to and reset on exit from their associated states. The ISP1362 provides a
programmable timer that can be used as any of these four timers.
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b_idle
drv_vbus/
chrg_vbus/
loc_conn/
loc_sof/
START
a_idle
drv_vbus/
chrg_vbus/
loc_conn/
loc_sof/
id | a_bus_req |
(a_sess_vld/ &
b_conn/)
id
a_bus_drop/ &
(a_bus_req |
a_srp_det)
id | a_bus_drop |
a_wait_bcon_tmout
a_wait_vfall
drv_vbus/
loc_conn/
loc_sof/
id | a_bus_drop
id | a_bus_drop
a_wait_vrise
drv_vbus
loc_conn/
loc_sof/
b_bus_suspend
id | a_bus_drop |
a_vbus_vld |
a_wait_vrise_tmout
a_vbus_err
drv_vbus/
loc_conn/
loc_sof/
a_vbus_vld/
a_vbus_vld/
a_peripheral
drv_vbus
loc_conn
loc_sof/
a_vbus_vld/
a_vbus_vld/
a_wait_bcon
drv_vbus
loc_conn/
loc_sof/
b_conn/ &
a_set_b_hnp_en/
id |
a_bus_drop |
a_aidl_bdis_tmout
b_conn/ &
a_set_b_hnp_en
id |
b_conn/ |
a_bus_drop
b_conn
a_bus_req |
b_bus_resume
a_suspend
drv_vbus
loc_conn/
loc_sof/
a_host
drv_vbus
loc_conn/
loc_sof
a_bus_req/ |
a_suspend_req
004aaa077
Fig 18. Dual-role A-device state diagram.
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a_idle
drv_vbus/
chrg_vbus/
loc_conn/
loc_sof/
START
b_idle
drv_vbus/
chrg_vbus/
loc_conn/
loc_sof/
id/ |
b_sess_vld/
b_bus_req &
b_sess_end &
b_se0_srp
id/ |
b_srp_done
id/ |
b_sess_vld/
b_host
chrg_vbus/
loc_conn/
loc_sof
id/
b_srp_init
pulse loc_conn
pulse chrg_vbus
loc_sof/
id/ |
b_sess_vld/
b_sess_vld
b_bus_req/ |
a_conn/
a_conn
a_bus_resume |
b_ase0_brst_tmout
b_wait_acon
chrg_vbus/
loc_conn/
loc_sof/
b_peripheral
chrg_vbus/
loc_conn
loc_sof/
b_bus_req &
b_hnp_en &
a_bus_suspend
004aaa078
Fig 19. Dual-role B-device state diagram.
11.4.3
HNP implementation and OTG state machine
The OTG state machine is the software behind all the OTG functionality. It is
implemented in the microprocessor system that is connected to the ISP1362. The
ISP1362 provides all input status, the output control and timers to fully support the
state machine transitions in Figure 18 and Figure 19.
These registers include:
• OtgControl register: provides control to VBUS driving, charging or discharging, data
line pull-up or pull-down, SRP detection, and so on
• OtgStatus register: provides status detection on VBUS and data lines including ID,
VBUS session valid, session end, overcurrent, bus status
• OtgInterrupt register: provides interrupts for status change in OtgStatus register
bits and the OtgTimer time-out event
• OtgInterruptEnable register: provides interrupt mask for OtgInterrupt register bits
• OtgTimer register: provides 0.01 ms base programmable timer for use in the OTG
state machine.
The OTG interrupt is generated on the INT1 pin. It is shared with the HC interrupt. To
enable the OTG interrupt, perform these steps:
1. Set the polarity and the level-triggering or edge-triggering mode of the
HcHardwareConfiguration register (bits 1 and 2, default is level-triggered, active
LOW).
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2. Set the corresponding bits of the OtgInterruptEnable register (bits 0 to 8, or some
of them).
3. Set bit OTG_IRQ_InterruptEnable of the HcµPInterruptEnable register (bit 9).
4. Set bit InterruptPinEnable of the HcHardwareConfiguration register (bit 0).
When an interrupt is generated on INT1, perform these steps in the interrupt service
routine to get the related OTG status:
1. Read the HcµPInterrupt register. If OTG_IRQ (bit 9) is set, then step 2.
2. Read the OtgInterrupt register. If any of the bits 0 to 4 are set, then step 3.
3. Read the OtgStatus register.
The OTG state machine routines are called when any of the inputs is changed. These
inputs come from either OTG registers (hardware) or application program (software).
The outputs of the state machine include control signals to the OTG register (for
hardware) and states or error codes (for software). For more information, refer to the
Philips document ISP136x Embedded Programming Guide.
11.5 Power saving in the idle state and during wake-up
The ISP1362 can be put in the power saving mode if the OTG device is not in a
session. This significantly reduces the power consumption. In this mode, both the DC
and the HC are suspended. The PLL and the oscillator are stopped, and the charge
pump is in the suspend state.
As an OTG device, however, the ISP1362 is required to respond to the SRP event. To
support this, a LazyClock is kept running when the chip is in the power saving mode.
An SRP event will wake up the chip (that is, enable the PLL and the oscillator).
Besides this, an ID change or B_SESS_VLD detection can also wake up the chip.
These wake-up events can be enabled or disabled by programming the related bits of
the OtgInterruptEnable register before putting the chip in the power saving mode. If
the bit is set, then the corresponding event (status change) will wake up the ISP1362.
If the bit is cleared, then the corresponding event will not wake up the ISP1362.
You can also wake up the ISP1362 from the power saving mode by using software.
This is accomplished by accessing any of ISP1362 registers. Accessing a register will
assert CS of the ISP1362, and therefore, set it awake.
11.6 Current capacity of the OTG charge pump
The ISP1362 uses a built-in charge pump to generate a 5 V VBUS supply from a
3.3 V ± 0.3 V voltage source. The only external component required is a capacitor.
The value of this capacitor depends on the amount of current drive required. Table 7
provides two recommended capacitor values and the corresponding current drive.
Table 7:
Recommended capacitor values
Capacitance
VCC
Current
27 nF
3.0 V to 3.6 V
8 mA
82 nF
3.0 V to 3.3 V
14 mA
3.3 V to 3.6 V
20 mA
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The connection of the external capacitor (Cext) is given in the partial schematics in
Figure 20.
Remark: If the internal charge pump is not used, Cext is not required.
VBUS
OTG VBUS
0.1 µF
4.7 µF
ISP1362
CP_CAP2
Cext
CP_CAP1
004aaa154
Fig 20. External capacitors connection.
12. USB Host Controller (HC)
12.1 USB states of the HC
The USB HC in the ISP1362 has four USB states: USBOperational, USBReset,
USBSuspend and USBResume. These states define the responsibilities of the HC
related to the USB signaling and bus states. These signals are visible to the HC
Driver (HCD), the software driver of the HC, by using the control registers of the
ISP1362 USB HC.
USBOperational
USBReset write
USBOperational write
USBReset write
USBOperational write
USBResume
USBReset
USBSuspend write
hardware or software
reset
USBResume write
or
remote wake-up
USBReset write
MGT947
USBSuspend
Fig 21. USB HC states of the ISP1362.
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The USB states are reflected in the HostControllerFunctionalState (HCFS) field of the
HcControl register. The HCD is allowed to perform only the USB state transitions
shown in Figure 21.
12.2 USB traffic generation
USB traffic can be generated only when the ISP1362 USB HC is under the
USBOperational state. Therefore, the HCD must set the ISP1362 USB HC into the
USBOperational state. This is done by setting the HCFS field of the HcControl
register before generating USB traffic.
A brief flow of USB traffic generation is described as follows:
1. Reset the ISP1362 by using the RESET pin or the software reset.
2. Set the physical size of the ATL, interrupt, ISTL0 and ISTL1 buffers.
3. Write the 32-bit hexadecimal value 0x800000FD to the HcInterruptEnable
register. This will enable all the interrupt events in the register to trigger the
hardware interrupt (see Section 15.1.5).
4. Write the 16-bit hexadecimal value 0x002D to the HcHardwareConfiguration
register. This will set up the HC to level triggered and active HIGH interrupt
setting (see Section 15.4.1).
5. Write 0x05000B02 to HcRhDescriptorA and 0x00000000 to HcRhDescriptorB.
6. Write the 16-bit hexadecimal value 0x0680 to the HcControl register to set the
ISP1362 into the Operation mode (see Section 15.1.2).
7. Read the HcRhPortStatus[1] and HcRhPortStatus[2] registers. These registers
contain the 32-bit hexadecimal value 0x00010100 (see Section 15.3.4).
8. Connect a full-speed device to one of the downstream ports or use a 1.5 kΩ
resistor to pull up the DP line (to emulate a full-speed device).
9. Read the HcRhPortStatus[1] and HcRhPortStatus[2] registers. The hexadecimal
value of one of the registers must change to 0x00010101 indicating that a device
connection has been detected.
10. Write the 32-bit hexadecimal value 0x00000102 into either HcRhPortStatus[1] or
HcRhPortStatus[2] depending on the port that is being used.
11. Read the HcRhPortStatus[1] and HcRhPortStatus[2] registers. Depending on
which port the USB device is connected to, one of the registers should contain
the hexadecimal value 0x00010103.
SOF packets should be visible on DP and DM now.
The HcFmNumber register contains the current frame number, which is updated
every milliseconds.
Remark: The generation of SOF is completely performed by the ISP1362 hardware.
In this state of operation, if a PTD is written to the buffer memory, it would be
processed and sent.
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12.3 USB ports
The ISP1362 has two USB ports: port 1 and port 2. Port 1 can be configured as a
downstream port (host), an upstream port (device) or a dual-role port (OTG). Port 2 is
a fixed downstream port.
The function of port 1 depends on two input pins of the ISP1362, namely ID and
OTGMODE.
Table 8:
Port 1 function
OTGMODE
ID
Function of port 1
L
X
OTG
H
L
host
H
H
peripheral
In the OTG mode, port 2 operates as an internal host. It is not advisable to expose
the host port 2 to external devices because it will not respond to the SRP and HNP
protocols. Besides, the current capability of VBUS may be different from the OTG
port’s. The USB compliance checklist states that one and only one USB mini-AB
receptacle is allowed on an OTG device.
12.4 Philips Transfer Descriptor (PTD)
The PTD provides a communication channel between the HCD and the ISP1362
USB HC. A PTD consists of a PTD header and a payload data. The size of the PTD
header is 8 bytes, and it contains information required for data transfer, such as data
packet size, transfer status and transfer token types. Payload data to be transferred
within a particular frame must have a PTD as the header (see Figure 22).
The ISP1362 has three types of PTDs: control and bulk transfer (aperiodic transfer)
PTD, interrupt transfer PTD and isochronous (ISO) transfer PTD.
In the control and bulk transfer PTD and the interrupt transfer PTD, the buffer area is
separated into equal sized blocks that are determined by HcATLBlockSize and
HcINTLBlockSize. For example, if the block size is defined as 32 bytes, the first PTD
structure in the memory buffer will have an offset of 0 bytes and the second PTD
structure will have an offset of 40 bytes [sum of the block size (32 bytes) and the PTD
header size (8 bytes)]. Because of the fixed block size of the ISP1362 HC, however,
even a PTD with 4 bytes of payload will occupy all the 40 bytes in a block.
In the isochronous PTD, the HC uses a more flexible method to calculate the PTD
offset because each PTD can have a different payload size. The actual amount of
space for the payload, however, must be a multiple of DWord. Therefore, a 10-byte
payload must have a reserved data size of 12 bytes. Take for example there are four
PTDs in the ISTL0 buffer area with payload sizes of 200 bytes, 10 bytes, 1023 bytes
and 30 bytes. Then, the offset of each of these PTDs will be as follows:
PTD1 (200 bytes) — offset = 0
PTD2 (10 bytes) — offset = (200 + 8) = 208
PTD3 (1023 bytes) — offset = (200 + 8) + (12 + 8) = 228
PTD4 (30 bytes) — offset = (200 + 8) + (12 + 8) + (1024 + 8) = 1260.
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PTD data stored in the HC buffer memory will not be processed unless the respective
control bits (ATL_Active, INTL_Active, ISTL0_BufferFull or ISTL1_BufferFull) in
HcBufferStatus are set.
PTD data in the ATL or interrupt buffer memory can be disabled by setting the
respective skip bit in HcATLSkipMap and HcINTLSkipMap. To skip a particular PTD in
the ATL or interrupt buffer, the HCD may set the corresponding bit of the SkipMap
register. For example, setting the HcATLSkipMap register to 0x0011 will cause
the HC to skip the first and the fifth PTDs in the ATL buffer memory.
Certain fields in the PTD header are used by the HC to inform the HCD about the
status of the transfer. These fields are indicated by the ‘Status Update by HC’ column.
These fields are updated after every transaction to reflect the current status of the
PTD.
buffer memory
top
PTD header
PTD data #1
payload data
PTD header
PTD data #2
payload data
PTD header
PTD data #N
payload data
bottom
004aaa121
Fig 22. PTD data stored in the buffer memory.
Table 9:
Generic PTD structure: bit allocation
Bit
7
6
5
4
Byte 0
2
1
0
ActualBytes[7:0]
Byte 1
CompletionCode[3:0]
Byte 2
Active
Toggle
ActualBytes[9:8]
Speed
MaxPktSize[9:8]
MaxPktSize[7:0]
Byte 3
EndpointNumber[3:0]
Byte 4
B3[3]
TotalBytes[7:0]
Byte 5
B5[7]
Byte 6
reserved
B5[6]
Byte 7
[1]
3
reserved
DirToken[1:0]
TotalBytes[9:8]
FunctionAddress[6:0]
B7[7:0]
All reserved bits should be set to logic 0.
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Table 10:
Bit
ATL
Interrupt
ISTL (ISO)
B3[3]
reserved
reserved
Last
B5[6]
Ping-Pong
reserved
reserved
B5[7]
Paired
reserved
reserved
B7[7:0]
reserved
PollingRate[7:5];
StartingFrame[4:0]
StartingFrame
[1]
Table 11:
Special fields for ATL, interrupt and ISO[1]
All reserved bits should be set to logic 0.
Generic PTD structure: bit description
Name
Status update
by HC
Description
ActualBytes[9:0]
Yes
This field contains the number of bytes that were transferred for this PTD.
CompletionCode[3:0]
Yes
0000
NoError
General Transfer Descriptor (TD) or
isochronous data packet processing
completed with no detected errors.
0001
CRC
The last data packet from the endpoint
contained a Cyclic Redundancy Check
(CRC) error.
0010
BitStuffing
The last data packet from the endpoint
contained a bit stuffing violation.
0011
DataToggleMismatch
The last packet from the endpoint had data
toggle Packet ID (PID) that did not match the
expected value.
0100
Stall
TD was moved to the Done queue because
the endpoint returned a STALL PID.
0101
DeviceNot
Responding
The device did not respond to the token (IN)
or did not provide a handshake (OUT).
0110
PIDCheckFailure
The check bits on PID from the endpoint
failed on data PID (IN) or handshake (OUT).
0111
UnexpectedPID
The received PID was not valid when
encountered, or the PID value is not defined.
1000
DataOverrun
The amount of data returned by the endpoint
exceeded either the size of the maximum
data packet allowed from the endpoint (found
in the MaximumPacketSize field of ED) or the
remaining buffer size.
1001
DataUnderrun
The endpoint returned is less than
MaximumPacketSize and that amount was
not sufficient to fill the specified buffer.
1010
-
reserved
1011
-
reserved
1100
BufferOverrun
During an IN, the HC received data from the
endpoint faster than it could be written to the
system memory.
1101
BufferUnderrun
During an OUT, the HC could not retrieve
data from the system memory fast enough to
keep up with the USB data rate.
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Table 11:
Generic PTD structure: bit description…continued
Name
Status update
by HC
Description
Active
Yes
Set to logic 1 by firmware to enable the execution of transactions by the HC.
When the transaction associated with this descriptor is completed, the HC
sets this bit to logic 0 indicating that a transaction for this element should not
be executed when it is next encountered in the schedule.
Toggle
Yes
This bit is used to generate or compare the data PID value (DATA0 or DATA1)
for IN and OUT transactions. It is updated after each successful transmission
or reception of a data packet.
MaxPktSize[9:0]
No
This indicates the maximum number of bytes that can be sent to or received
from the endpoint in a single data packet.
EndpointNumber[3:0]
No
This is the USB address of the endpoint within the function.
B3[3] Last (PTD)
No
This indicates that it is the last PTD of a list. Logic 1 means that this PTD is
the last PTD. The last PTD is used only for ISO. This bit is not used in interrupt
and ATL transfers. The last PTD is indicated by the HcINTLLastPTD and
HcATLLastPTD registers.
Speed (low)
No
This bit indicates the speed of the endpoint.
0 — full-speed
1 — low-speed
TotalBytes[9:0]
No
This specifies the total number of bytes to be transferred with this data
structure. This can be greater than MaximumPacketSize.
B5[6] Ping-Pong
No
0 — This is the ping buffer of the paired buffer. Paired must be logic 1.
1 — This is the pong buffer of the paired buffer. Paired must be logic 1.
B5[7] Paired
No
If this bit is set to logic 1, two PTDs of the same endpoint and address can be
made active at the same time. This bit is used with the Ping-Pong bit. The first
paired PTD always starts with Ping = 0. The pong PTD payload can be sent
out only if the ping PTD payload is sent out. You can also monitor
RAM_BUFFER _STATUS to see which PTD is currently active on the USB
line.
DirToken[1:0]
No
00 — set-up
01 — OUT
10 — IN
11 — reserved
FunctionAddress[6:0]
No
This field contains the USB address of the function containing the endpoint
that this PTD refers to.
B7[7:5] PollingRate
B7[4:0] StartingFrame
(interrupt only)
No
These two fields together select a start frame number (5 bits) and polls the
interrupt device at a rate specified by PollingRate (3 bits); see Section 12.6.
B7[7:0] StartingFrame
(ISO only)
No
The HC compares this byte with the current frame number (can be accessed
from the HcFrameNumber register). The PTD will be processed and sent out
only if the starting frame number equals to the current frame number.
12.5 Features of the control and bulk transfer (aperiodic transfer)
• A Paired PTD is a special feature that provides high performance single endpoint
bulk transfer and handles set-up enumeration sequence within 1 ms. A paired PTD
consists of two PTDs serving the same endpoint of a device that are set active and
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placed in the ATL RAM at the same time. A paired PTD is designed specially for
high performance of a single endpoint. They are identified by hardware by using
the ‘Paired’ bit in the PTD.
• Possible to send up to a maximum of 18 USB bulk packets in 1 ms frame
(1.152 Mbyte/s) by using the paired PTD feature.
• Provides the status of every transfer endpoints (PTD) by monitoring the
HcATLDoneMap of the ISP1362. This register provides information on which PTD
transfers are complete.
• Sets the IRQ after the user-specified number of transfers is done.
• Skips any PTD that is wasting bandwidth by using HcATLSkipMap.
12.5.1
Sending a USB device request (Get Descriptor)
This section provides an example on how a USB transfer descriptor ‘Get Descriptor’
(commonly used in device enumeration) is used to illustrate the ISP1362 PTD
application. To perform this example, make sure the ISP1362 is in the Operational
state, and then connect a USB device (for example, a USB mouse) to a port.
Remark: For details on the USB device request, refer to Chapter 9 of Universal Serial
Bus Specification Rev. 2.0.
Step 1: Set the HcATLBlockSize, HcATLSkip and HcATLLast registers to 0x0008,
0xFFFE and 0x0001, respectively.
Step 2: A PTD is then constructed based on the information given in the following
sample code. This sample code places information into the correct bit location within
the 8 bytes of the PTD structure.
ActualBytes (10 bits) = 0x00
CompletionCode (4 bits) = 0x0F
Active (1 bit) = 1
Toggle (1 bit) = 0
MaxPacketSize (10 bits) = 8
EndpointNumber (4 bits) = 0
Speed (1 bit) = 0 (full-speed; use 1 for low-speed)
DirToken (2 bits) = 0 (setup token)
TotalBytes (10 bits) = 8
CompletedPTD
0xF800, 0x0008, 0x0008, 0x0000
Step 3: This array is then appended with an 8-byte payload that specifies the type of
request the HC wants to send. For example, for Get Descriptor, the payload is
0x0680, 0x0100, 0x0000, 0x0012.
Step 4: The 16 bytes of data is now a complete PTD with an accompanying payload.
This array is then copied into the ATL buffer area. Table 12 shows the ATL buffer area.
Table 12:
ATL buffer area
Offset
0
1
2
3
4
5
6
7
Data
0xF800
0x0008
0x0008
0x0000
0x0680
0x0100
0x0000
0x0012
Step 5: After copying data into the ATL buffer, the HC must be notified that the ATL
buffer is now full and ready to be processed. The ATL_Active bit of the
HcBufferStatus register must be set to logic 1 to inform the HC that the data in the
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ATL buffer is now ready for processing. Once the ATL_Active bit of the HcBufferStatus
register is set, the USB packet is sent out. The active bit in the PTD is cleared once
the PTD is sent. Depending on the outcome of the USB transfer, the 4-bit completion
code is updated.
12.6 Features of the interrupt transfer
• An interrupt transaction is sent out periodically, according to the ‘interrupt polling
rate’ as defined in the PTD.
• An interrupt transaction causes an interrupt to the CPU only if the transaction is
ACKed or has error conditions, such as STALL or no respond. An ACK condition
occurs if data is received on the IN token or data is sent out on the OUT token.
• An interrupt is activated only once every ms as long as there is ACK for different
interrupt transactions in the interrupt transfer buffer.
• Each interrupt transfer (PTD) placed in the INTL buffer can automatically hold or
send data for more than 1 ms. This can be done using the parameters in the PTD.
Table 13:
Interrupt polling
N bits [7:5]
StartingFrame N[4:0]
Interrupt polling interval (2N) in ms
0
Frame 0 to 31
1
1
Frame 0 to 31
2
2
Frame 0 to 31
4
3
Frame 0 to 31
8
4
Frame 0 to 31
16
5
Frame 0 to 31
32
6
Frame 0 to 31
64
7
Frame 0 to 31
128
12.7 Features of the isochronous (ISO) transfer
• Supports multi-buffering by using the ISTL0 or ISTL1 toggling mechanism.
• The CPU can decide (in ms) how fast it can serve the ISP1362. This gives the
CPU the flexibility to decide how much time it takes to read and fill in the ISO data.
• The ISTL buffer can be updated on-the-fly by using the direct addressing memory
architecture.
12.8 Overcurrent protection circuit
The ISP1362 has a built-in overcurrent protection circuitry. You can enable or disable
this feature by setting or resetting AnalogOCEnable (bit 10) of the
HcHardwareConfiguration register. If this feature is disabled, it is assumed that there
is an external overcurrent protection circuitry.
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12.8.1
Using internal OC detection circuit
An application using the internal OC detection circuit and internal 15 kΩ pull-down
resistors is shown in Figure 23, where DMn denotes either OTG_DM1 or H_DM2,
while DPn denotes either OTG_DP1 or H_DP2. In this example, the HC Driver must
set both AnalogOCEnable and ConnectPullDown_DS1 (bit 10 and bit 12 of the
HcHardwareConfiguration register, respectively) to logic 1.
When H_OCn detects an overcurrent status on a downstream port, H_PSWn will
output HIGH to turn off the +5 V power supply to the downstream port VBUS. When
there is no such detection, H_PSWn will output LOW to turn on the +5 V power
supply to the downstream port VBUS.
In general applications, you can use a P-channel MOSFET as the power switch for
VBUS. Connect the +5 V power supply to the drain pole of the P-channel MOSFET,
VBUS to the source pole, and H_PSWn to the gate pole. This voltage drop (∆V) across
the drain and source poles can be called the overcurrent trip voltage. For the internal
overcurrent detection circuit, a voltage comparator has been designed-in, with a
nominal voltage threshold of 75 mV. Therefore, when the overcurrent trip voltage (∆V)
exceeds the voltage threshold, H_PSWn will output a HIGH level to turn off the
P-channel MOSFET. If the P-channel MOSFET has RDSon of 150 mΩ, the overcurrent
threshold will be 500 mA. The selection of a P-channel MOSFET with a different
RDSon will result in a different overcurrent threshold.
VDD_5V
PSU_5V
drain
P_channel
MOSFET
FB2
C41(1)
VBUS
DM
DP
GND
chassis
chassis
1
DGND
gate
C18
0.1 µF
R31
10 kΩ
H_PSWn
source
H_OCn
C17
0.1 µF
DGND
2
3
4
5
6
004aaa148
DGND
(1) 100 µF for the host port or 4.7 µF for the OTG port.
Fig 23. Using internal OC detection circuit.
12.8.2
Using external OC detection circuit
When VCC (pin 56) is connected to the +3.3 V power supply instead of the +5 V
power supply, the internal OC detection circuit cannot be used. An external
OC detection circuit must be used instead. Nevertheless, regardless of VCC
connection, an external OC detection circuit can be used from time to time. To use an
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external OC detection circuit, set AnalogOCEnable, bit 10 of register
HcHardwareConfiguration, to logic 0. By default after reset this bit is set to logic 0.
Therefore, the HC Driver does not need to clear this bit.
Figure 24 shows how to use an external OC detection circuit.
PSU_5V
OC DETECTION
VIN
OC
H_OCn
VOUT
EN
H_PSWn
FB2
C41(1)
VBUS
DM
DP
GND
chassis
chassis
1
DGND
C17
0.1 µF
DGND
2
3
4
5
6
004aaa149
DGND
(1) 100 µF for the host port or 4.7 µF for the OTG port.
Fig 24. Using external OC detection circuit.
12.8.3
OC detection circuit using internal charge pump in the OTG mode
When port 1 is operating in the OTG mode, you may choose to use the internal
charge pump to provide 5 V VBUS, or supply VBUS from an external source. In this
mode, the overcurrent condition is detected by a drop in VBUS that will be sensed by
the built-in comparator. The overcurrent condition causes a change in the
A_VBUS_VLD bit of the OtgStatus register. The software has to clear the
DRV_VBUS bit in the OtgControl register when it detects the A_VBUS_VLD bit
turning to logic 0.
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H_OCn
FB2
C41(1)
VBUS
DM
DP
GND
chassis
chassis
1
DGND
VBUS
C17
0.1 µF
DGND
2
3
4
n.c.
5
H_PSWn
6
004aaa150
DGND
(1) 100 µF for the host port or 4.7 µF for the OTG port.
Fig 25. Using internal charge pump.
12.8.4
OC detection circuit using external 5 V power source in the OTG mode
In the OTG mode using external 5 V power source for VBUS, the circuit and the
operation are the same as that for the non-OTG mode (see Section 12.8.1 and
Section 12.8.2).
12.9 ISP1362 HC Power Management
In the ISP1362, the HC and the DC are suspended and waken up individually. The
H_SUSPEND/H_WAKEUP and D_SUSPEND/D_WAKEUP pins must be pulled-up
by a large resistor (100 kΩ). In the suspend state, these pins are HIGH. To wake up
the HC, these pins must be pulled LOW.
The ISP1362 can be partially suspended (only the HC or only the DC). In the partially
suspended state, clock circuit and PLL continue to work. To save power, both the HC
and the DC must be set to the suspend mode.
The HC can be suspended by writing 0x06C0 to the HcControl register.
The HC can be set awake by one of the following ways:
• LOW pulse on the H_SUSPEND/H_WAKEUP pin, minimum length of pulse is
25 ns.
• LOW pulse on the chip select (CS) pin, minimum length of pulse is 25 ns.
• Resume signal by USB devices connected to the downstream port.
On waking up from the suspend state, the clock to the HC will sustain for 5 ms. Within
this 5 ms, the HC Driver must set the HC to the operational mode by writing 0x0680
to the HcControl register. If the HcControl register remains in the suspend state
(0x06C0) after waking up the HC, the HC will return to the suspend state after 5 ms.
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13. USB Device Controller (DC)
The design of the DC in the ISP1362 is compatible with the Philips ISP1181B USB
full-speed interface device IC. The functionality of the DC in the ISP1362 is similar to
the ISP1181B in the 16-bit bus mode. In addition, the command and register sets are
also the same.
In general, the DC in the ISP1362 provides 16 endpoints for the USB device
implementation. Each endpoint can be allocated RAM space in the on-chip ping pong
buffer RAM.
Remark: The ping pong buffer RAM for the DC is independent of the buffer RAM for
the Host Controller (HC). When the buffer RAM is full, the DC transfers the data in the
buffer RAM to the USB bus. When the buffer RAM is empty, an interrupt is generated
to notify the microprocessor to feed in data. The transfer of data between a
microprocessor and the DC can be done in either the Programmed I/O (PIO) mode or
in the direct memory access (DMA) mode.
13.1 DC data transfer operation
The following sessions explains how the DC in the ISP1362 handles an IN data
transfer and an OUT data transfer. An IN data transfer means transfer from the
ISP1362 to an external USB host (through the upstream port), and an OUT transfer
means transfer from an external USB host to the ISP1362. In the device mode, the
ISP1362 acts as a USB device.
13.1.1
IN data transfer
• The arrival of the IN token is detected by the Serial Interface Engine (SIE) by
decoding the Packet IDentifier (PID).
• The SIE also checks the device number and the endpoint number to verify whether
they are okay.
• If the endpoint is enabled, the SIE checks the contents of the DcEndpointStatus
register (ESR). If the endpoint is full, the contents of the buffer memory are sent
during the data phase else an NAK handshake is sent.
• After the data phase, the SIE expects a handshake (ACK) from the host (except for
ISO endpoints).
• On receiving the handshake (ACK), the SIE updates the contents of the
DcEndpointStatus and DcInterrupt registers, which in turn generates an interrupt
to the microprocessor. For ISO endpoints, the DcInterrupt register is updated as
soon as data is sent because there is no handshake phase.
• On receiving an interrupt, the microprocessor reads the DcInterrupt register. It will
know which endpoint has generated the interrupt and reads the contents of the
corresponding ESR. If the buffer is empty, it fills up the buffer so that data can be
sent by the SIE at the next IN token phase.
13.1.2
OUT data transfer
• The arrival of the OUT token is detected by the SIE by decoding the PID.
• The SIE checks the device and endpoint numbers to verify whether they are okay.
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• If the endpoint is enabled, the SIE checks the contents of the ESR. If the endpoint
is empty, the data from USB is stored in the buffer memory during the data phase
else a NAK handshake is sent.
• After the data phase, the SIE sends a handshake (ACK) to the host (except for ISO
endpoints).
• The SIE updates the contents of the DcEndpointStatus register and the
DcInterrupt register, which in turn generates an interrupt to the microprocessor.
For ISO endpoints, the DcInterrupt register is updated as soon as data is received
because there is no handshake phase.
• On receiving an interrupt, the microprocessor reads the DcInterrupt register. It will
know which endpoint has generated the interrupt and reads the content of the
corresponding ESR. If the buffer is full, it empties the buffer so that data can be
received by the SIE at the next OUT token phase.
13.2 Device DMA transfer
13.2.1
DMA for IN endpoint (internal DC to the external USB host)
When the internal DMA handler is enabled and at least one buffer (ping or pong) is
free, the DREQ2 line is asserted. The external DMA controller then starts negotiating
for control of the bus. As soon as it has access, it asserts the DACK2 line and starts
writing data. The burst length is programmable. When the number of bytes equal to
the burst length has been written, the DREQ2 line is deasserted. As a result, the
DMA controller deasserts the DACK2 line and releases the bus. At that moment, the
whole cycle restarts for the next burst.
When the buffer is full, the DREQ2 line is deasserted and the buffer is validated
(which means that it is sent to the host at the next IN token). When the DMA transfer
is terminated, the buffer is also validated (even if it is not full). A DMA transfer is
terminated when any of the following conditions are met:
• The DMA count is complete
• DMAEN = 0.
Remark: If the OneDMA bit in the HcHardwareConfiguration register is set to logic 1,
the DC DMA controller handshake signals DREQ2 and DACK2 are routed to DREQ1
and DACK1.
13.2.2
DMA for OUT endpoint (external USB host to internal DC)
When the internal DMA handler is enabled and at least one buffer is full, the DREQ2
line is asserted. The external DMA controller then starts negotiating for control of the
bus, and as soon as it has access, it asserts the DACK2 line and starts reading data.
The burst length is programmable. When the number of bytes equal to the burst
length has been read, the DREQ2 line is deasserted. As a result, the DMA controller
deasserts the DACK2 line and releases the bus. At that moment, the whole cycle
restarts for the next burst. When all the data is read, the DREQ2 line is deasserted
and the buffer is cleared (this means that it can be overwritten when a new packet
arrives). A DMA transfer is terminated when any of the following conditions are met:
• The DMA count is complete
• DMAEN = 0.
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Remark: If the OneDMA bit in the HcHardwareConfiguration register is set to logic 1,
the DC DMA controller handshake signals DREQ2 and DACK2 are routed to DREQ1
and DACK1.
When the DMA transfer is terminated, the buffer is also cleared (even if data is not
completely read) and the DMA handler is automatically disabled. For the next DMA
transfer, the DMA controller as well as the DMA handler must be re-enabled.
13.3 Endpoint description
13.3.1
Endpoints with programmable buffer memory size
Each USB device is logically composed of several independent endpoints. An
endpoint acts as a terminus of a communication flow between the USB host and the
USB device. At design time, each endpoint is assigned a unique number (endpoint
identifier, see Table 14). The combination of the device address (given by the host
during enumeration), the endpoint number, and the transfer direction allows each
endpoint to be uniquely referenced.
The DC has 16 endpoints: endpoint 0 (control IN and OUT) and 14 configurable
endpoints, which can be individually defined as interrupt, bulk or isochronous—IN or
OUT. Each enabled endpoint has an associated buffer memory, which can be
accessed either by using the programmed I/O interface mode or by using the DMA
mode.
13.3.2
Endpoint access
Table 14 lists the endpoint access modes and programmability. All endpoints support
I/O mode access. Endpoints 1 to 14 also support the DMA mode access. DC buffer
memory DMA access is selected and enabled using bits EPIDX[3:0] and DMAEN of
the DcDMAConfiguration register. A detailed description of the DC DMA operation is
given in Section 13.4.
Table 14:
Endpoint access and programmability
Endpoint
identifier
Buffer memory size
(bytes)[1]
Double
buffering
PIO mode
access
DMA mode
access
Endpoint type
0
64 (fixed)
no
yes
no
control OUT[2][3]
0
64 (fixed)
no
yes
no
control IN[2][3]
1 to 14
programmable
supported
supported
supported
programmable
[1]
[2]
[3]
The total amount of the buffer memory storage allocated to enabled endpoints must not exceed 2462 bytes.
IN: input for the USB host (DC transmits); OUT: output from the USB host (DC receives).
The data flow direction is determined by the EPDIR bit of the DcEndpointConfiguration register.
13.3.3
Endpoint buffer memory size
The size of the buffer memory determines the maximum packet size that the
hardware can support for a given endpoint. Only enabled endpoints are allocated
space in the shared buffer memory storage, disabled endpoints have zero bytes.
Table 15 lists the programmable buffer memory sizes.
The following bits of the DcEndpointConfiguration register (ECR) affect the buffer
memory allocation:
• Endpoint enable bit (FIFOEN)
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• Size bits of an enabled endpoint (FFOSZ[3:0])
• Isochronous bit of an enabled endpoint (FFOISO).
Remark: A register change that affects the allocation of the shared buffer memory
storage among endpoints must not be made while valid data is present in any buffer
memory of the enabled endpoints. Such changes renders all buffer memory contents
undefined.
Table 15:
Programmable buffer memory size
FFOSZ[3:0]
Non-isochronous
Isochronous
0000
8 bytes
16 bytes
0001
16 bytes
32 bytes
0010
32 bytes
48 bytes
0011
64 bytes
64 bytes
0100
reserved
96 bytes
0101
reserved
128 bytes
0110
reserved
160 bytes
0111
reserved
192 bytes
1000
reserved
256 bytes
1001
reserved
320 bytes
1010
reserved
384 bytes
1011
reserved
512 bytes
1100
reserved
640 bytes
1101
reserved
768 bytes
1110
reserved
896 bytes
1111
reserved
1023 bytes
Each programmable buffer memory can be independently configured by using its
ECR, but the total physical size of all enabled endpoints (IN plus OUT) must not
exceed 2462 bytes.
Table 16 shows an example of a configuration fitting in the maximum available space
of 2462 bytes. The total number of logical bytes in the example is 1311. The physical
storage capacity used for double buffering is managed by the device hardware and is
transparent to the user.
Table 16:
Memory configuration example
Physical size
(bytes)
Logical size
(bytes)
Endpoint description
64
64
control IN (64-byte fixed)
64
64
control OUT (64-byte fixed)
2046
1023
double-buffered 1023-byte isochronous endpoint
16
16
16-byte interrupt OUT
16
16
16-byte interrupt IN
128
64
double-buffered 64-byte bulk OUT
128
64
double-buffered 64-byte bulk IN
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13.3.4
Endpoint initialization
In response to the standard USB request Set Interface, the firmware must program all
the 16 ECRs of the DC in sequence (see Table 14), whether endpoints are enabled
or not. The hardware then automatically allocates buffer memory storage space.
If all endpoints have been successfully configured, the firmware must return an empty
packet to the control IN endpoint to acknowledge success to the host. If there are
errors in the endpoint configuration, the firmware must stall the control IN endpoint.
When reset by hardware or by the USB bus occurs, the DC disables all endpoints and
clears all ECRs, except the control endpoint which is fixed and always enabled.
An endpoint initialization can be done at any time. It is, however, valid only after
enumeration.
13.3.5
Endpoint I/O mode access
When an endpoint event occurs (a packet is transmitted or received), the associated
endpoint interrupt bits (EPn) of the DcInterrupt register (IR) are set by the SIE. The
firmware then responds to the interrupt and selects the endpoint for processing.
The endpoint interrupt bit is cleared by reading the DcEndpointStatus register (ESR).
The ESR also contains information on the status of the endpoint buffer.
For an OUT (= receive) endpoint, the packet length and packet data can be read from
the DC by using the Read Buffer command. When the whole packet has been read,
the firmware sends a Clear Buffer command to enable the reception of new packets.
For an IN (= transmit) endpoint, the packet length and data to be sent can be written
to the DC by using the Write Buffer command. When the whole packet has been
written to the buffer, the firmware sends a Validate Buffer command to enable data
transmission to the host.
13.3.6
Special actions on control endpoints
Control endpoints require special firmware actions. The arrival of a Set-up packet
flushes the IN buffer and disables the Validate Buffer and Clear Buffer commands for
the control IN and OUT endpoints. The microprocessor needs to re-enable these
commands by sending an Acknowledge Set-up command to both the control
endpoints.
This ensures that the last Set-up packet stays in the buffer and that no packets can be
sent back to the host until the microprocessor has explicitly acknowledged that it has
received the Set-up packet.
13.4 DC direct memory access (DMA) transfer
DMA is a method to transfer data from one location to another in a computer system,
without intervention of the CPU. Many different implementations of DMA exist.
The DC supports the 8237 compatible mode.
8237 compatible mode: based on the DMA subsystem of the IBM personal
computers (PC, AT and all its successors and clones); this architecture uses the
Intel 8237 DMA controller and has separate address spaces for memory and I/O.
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The following features are supported:
•
•
•
•
13.4.1
Single-cycle or burst transfers (up to 16 bytes per cycle)
Programmable transfer direction (read or write)
Multiple End-Of-Transfer (EOT) sources: internal conditions, short or empty packet
Programmable signal levels on pins DREQ2 and DACK2.
Selecting an endpoint for the DMA transfer
The target endpoint for DMA access is selected using bits EPDIX[3:0] of the
DcDMAConfiguration register, as shown in Table 17. The transfer direction (read or
write) is automatically set by the EPDIR bit in the associated ECR, to match the
selected endpoint type (OUT endpoint: read; IN endpoint: write).
Asserting input DACK2 automatically selects the endpoint specified in the
DcDMAConfiguration register, regardless of the current endpoint used for the
I/O mode access.
Table 17:
13.4.2
Endpoint selection for DMA transfer
Endpoint
identifier
EPIDX[3:0]
1
Transfer direction
EPDIR = 0
EPDIR = 1
0010
OUT: read
IN: write
2
0011
OUT: read
IN: write
3
0100
OUT: read
IN: write
4
0101
OUT: read
IN: write
5
0110
OUT: read
IN: write
6
0111
OUT: read
IN: write
7
1000
OUT: read
IN: write
8
1001
OUT: read
IN: write
9
1010
OUT: read
IN: write
10
1011
OUT: read
IN: write
11
1100
OUT: read
IN: write
12
1101
OUT: read
IN: write
13
1110
OUT: read
IN: write
14
1111
OUT: read
IN: write
8237 compatible mode
The 8237 compatible DMA mode is selected by clearing the DAKOLY bit of the
DcHardwareConfiguration register (see Table 114). The pin functions for this mode
are shown in Table 18.
Table 18:
8237 compatible mode: pin functions
Symbol
Description
I/O
Function
DREQ2
DMA request of DC
O
DC requests a DMA transfer
DACK2
DMA acknowledge of DC
I
DMA controller confirms the transfer
EOT
end of transfer
I
DMA controller terminates the transfer
RD
read strobe
I
instructs the DC to put data on the bus
WR
write strobe
I
instructs the DC to get data from the bus
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The DMA subsystem of an IBM-compatible PC is based on the Intel 8237 DMA
controller. It operates as a ‘fly-by’ DMA controller. Data is not stored in the DMA
controller, but it is transferred between an I/O port and a memory address. A typical
example of the DC in 8237 compatible DMA mode is given in Figure 26.
The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and
DACK (DMA Acknowledge). General control signals are HRQ (Hold Request) and
HLDA (Hold Acknowledge). The bus operation is controlled by MEMR (Memory
Read), MEMW (Memory Write), IOR (I/O read) and IOW (I/O write).
D0 to D15
RAM
MEMR
MEMW
DMA
CONTROLLER
8237
ISP1362
CPU
DREQ2
DREQ
HRQ
HRQ
DACK2
DACK
HLDA
HLDA
RD
IOR
WR
IOW
004aaa047
Fig 26. DC in 8327 compatible DMA mode.
The following example shows the steps that occur in a typical DMA transfer:
1. The DC receives a data packet in one of its endpoint buffer memory. The packet
must be transferred to memory address 1234H.
2. The DC asserts the DREQ2 signal requesting the 8237 for a DMA transfer.
3. The 8237 asks the CPU to release the bus by asserting the HRQ signal.
4. After completing the current instruction cycle, the CPU places the bus control
signals (MEMR, MEMW, IOR and IOW) and the address lines in three-state and
asserts HLDA to inform the 8237 that it has control of the bus.
5. The 8237 now sets its address lines to 1234H and activates the MEMW and IOR
control signals.
6. The 8237 asserts DACK to inform the DC that it will start a DMA transfer.
7. The DC now places the word to be transferred on the data bus lines because its
RD signal was asserted by the 8237.
8. The 8237 waits one DMA clock period and then deasserts MEMW and IOR. This
latches and stores the word at the desired memory location. It also informs
the DC that the data on the bus lines has been transferred.
9. The DC deasserts the DREQ2 signal to indicate to the 8237 that DMA is no
longer needed. In the Single cycle mode, this is done after each byte or word; in
the Burst mode, following the last transferred byte or word of the DMA cycle.
10. The 8237 deasserts the DACK output indicating that the DC must stop placing
data on the bus.
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11. The 8237 places the bus control signals (MEMR, MEMW, IOR and IOW) and the
address lines in three-state and deasserts the HRQ signal, informing the CPU
that it has released the bus.
12. The CPU acknowledges control of the bus by deasserting HLDA. After activating
the bus control lines (MEMR, MEMW, IOR and IOW) and the address lines, the
CPU resumes the execution of instructions.
For a typical bulk transfer, the preceding process is repeated 32 times, once for each
word. After each word, the DcAddress register in the DMA controller is incremented
by two and the byte counter is decremented by two. When using the 16-bit DMA, the
number of transfers is 32 and address incrementing and byte counter decrementing
is done by two for each word.
13.4.3
End-Of-Transfer conditions
Bulk endpoints: A DMA transfer to or from a bulk endpoint can be terminated by any
of the following conditions (bit names refer to the DcDMAConfiguration register, see
Table 118 and Table 119):
• The DMA transfer completes as programmed in the DcDMACounter register
(CNTREN = 1)
• A short packet is received on an enabled OUT endpoint (SHORTP = 1)
• DMA operation is disabled by clearing the DMAEN bit.
DcDMACounter register — An EOT from the DcDMACounter register is enabled by
setting bit CNTREN of the DcDMAConfiguration register. The DC has a 16-bit
DcDMACounter register, which specifies the number of bytes to be transferred. When
DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value from
the DcDMACounter register. When the internal counter completes the transfer as
programmed in the DMA counter, an EOT condition is generated and the DMA
operation stops.
Short packet — Normally, the transfer byte count must be set using a control
endpoint before any DMA transfer takes place. When a short packet has been
enabled as EOT indicator (SHORTP = 1), the transfer size is determined by the
presence of a short packet in the data. This mechanism permits the use of a fully
autonomous data transfer protocol.
When reading from an OUT endpoint, reception of a short packet at an OUT token
will stop the DMA operation after transferring the data bytes of this packet.
Table 19:
Summary of EOT conditions for a bulk endpoint
EOT condition
OUT endpoint
IN endpoint
DcDMACounter register
transfer completes as
programmed in the
DcDMACounter register
transfer completes as
programmed in the
DcDMACounter register
Short packet
short packet is received and
transferred
counter reaches zero in
the middle of the buffer
DMAEN bit of the
DcDMAConfiguration register
DMAEN = 0[1]
DMAEN = 0[1]
[1]
The DMA transfer stops. No interrupt, however, is generated.
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Isochronous endpoints: A DMA transfer to or from an isochronous endpoint can be
terminated by any of the following conditions (bit names refer to the
DcDMAConfiguration register, see Table 118 and Table 119):
• The DMA transfer completes as programmed in the DcDMACounter register
(CNTREN = 1)
• An End-Of-Packet (EOP) signal is detected
• DMA operation is disabled by clearing bit DMAEN.
Table 20:
Recommended EOT usage for isochronous endpoints
EOT condition
OUT endpoint
IN endpoint
DcDMACounter register zero
do not use
preferred
13.5 ISP1362 DC suspend and resume
13.5.1
Suspend conditions
The DC in the ISP1362 detects a USB suspend condition in either of the following
cases:
• Constant idle state is present on the USB bus for 3 ms.
• VBUS is lost.
Bus-powered devices that are suspended must not consume more than 500 µA of
current. This is achieved by shutting down the power to system components or
supplying them with a reduced voltage.
The steps leading the DC to the suspend state are as follows:
1. In the event of no SOF for 3 ms, the DC in the ISP1362 sets bit SUSPND of the
DcInterrupt register. This will generate an interrupt if bit IESUSP of the
DcInterruptEnable register is set.
2. When the firmware detects a suspend condition (through the IESUSP), it must
prepare all system components for the suspend state:
a. All the signals connected to the DC in the ISP1362 must enter appropriate
states to meet the power consumption requirements of the suspend state.
b. All the input pins of the DC in the ISP1362 must have a CMOS logic 0 or
logic 1 level.
3. In the interrupt service routine, the firmware must check the current status of the
USB bus. When bit BUSTATUS of the DcInterrupt register is logic 0, the USB bus
has left the suspend mode and the process must be aborted. Otherwise, the next
step can be executed.
4. To meet the suspend current requirements for a bus-powered device, the internal
clocks must be switched off by clearing bit CLKRUN of the
DcHardwareConfiguration register.
5. When the firmware has set and cleared the GOSUSP bit of the DcMode register,
the DC in the ISP1362 enters the suspend state. It sets the
D_SUSPEND/D_WAKEUP pin to HIGH and switches off the internal clocks after
2 ms.
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The DC in the ISP1362 will remain in the suspend state for at least 5 ms, before
responding to external wake-up events, such as global resume, bus traffic, CS active
or LOW pulse on the D_SUSPEND/D_WAKEUP pin.
Figure 27 shows a typical timing diagram for the DC suspend and resume operations.
A
D
> 5 ms
10 ms
idle state
K-state
USB BUS
> 3 ms
INT2
suspend
interrupt
resume
interrupt
B
GOSUSP (bit)
0.5 ms to
3.5 ms
D_SUSPEND/D_WAKEUP
1.8 ms to
2.2 ms
004aaa483
C
CS
Fig 27. Suspend and resume timing.
In Figure 27:
A — indicates the point at which the USB bus goes to the idle state.
B — after detecting the suspend interrupt, set and clear the GOSUSP bit in the Mode
register.
C — indicates resume condition, which can be a resume signal from the host, a LOW
pulse on the D_SUSPEND/D_WAKEUP pin, or a LOW pulse on the CS pin.
D — indicates remote wake-up. The ISP1362 will drive a K-state on the USB bus for
10 ms after the D_SUSPEND/D_WAKEUP pin goes LOW or the CS pin goes LOW.
13.5.2
Resume conditions
Wake-up from the suspend state is initiated either by the USB host or by the
application:
• USB host: drives a K-state on the USB bus (global resume)
• Application: remote wake-up using a LOW pulse on pin D_SUSPEND/D_WAKEUP
or a LOW pulse on pin CS (if enabled using bit WKUPCS of the
DcHardwareConfiguration register).
The steps of a wake-up sequence are as follows:
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1. The internal oscillator and the PLL multiplier are re-enabled. When stabilized, the
clock signals are routed to all internal circuits of the DC in the ISP1362.
2. The D_SUSPEND/D_WAKEUP pin goes LOW, and the RESUME bit of the
DcInterrupt register is set. This will generate an interrupt if bit IERESUME of the
DcInterruptEnable register is set.
3. 5 ms after starting the wake-up sequence, the DC in the ISP1362 resumes its
normal functionality (this could be set to 100 µs by setting pin TEST0 to HIGH).
4. In case of a remote wake-up, the DC in the ISP1362 drives a K-state on the USB
bus for 10 ms.
5. The application restores itself and other system components to normal operating
mode.
6. After wake-up, the internal registers of the DC in the ISP1362 are read and
write-protected to prevent corruption by inadvertent writing during power-up of
external components. The firmware must send an Unlock Device command to
the DC in the ISP1362 to restore its full functionality.
14. OTG registers
Table 21:
OTG Control registers summary
Command (Hex)
Register
Width
References
Functionality
OTG Operation registers
Read
Write
62
E2
OtgControl
16
Section 14.1 on page 60
67
N/A
OtgStatus
16
Section 14.2 on page 62
68
E8
OtgInterrupt
16
Section 14.3 on page 63
69
E9
OtgInterruptEnable
16
Section 14.4 on page 66
6A
EA
OtgTimer
32
Section 14.5 on page 67
6C
EC
OtgAltTimer
32
Section 14.6 on page 68
14.1 OtgControl register (R/W: 62H/E2H)
Code (Hex): 62 — read
Code (Hex): E2 — write
Table 22:
OtgControl register: bit allocation
Bit
15
14
Symbol
13
12
reserved
11
10
9
8
OTG_SE0_
EN
A_SRP_
DET_EN
A_SEL_
SRP
SEL_HC_
DC
Reset
-
-
-
-
0
0
0
1
Access
-
-
-
-
R/W
R/W
R/W
R/W
Bit
Symbol
Reset
Access
7
6
5
4
3
2
1
0
LOC_
PULLDN_
DM
LOC_
PULLDN_
DP
A_RDIS_
LCON_EN
LOC_
CONN
SEL_CP_
EXT
DISCHRG_
VBUS
CHRG_
VBUS
DRV_
VBUS
1
1
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Table 23:
Bit
OtgControl register: bit description
Symbol
Description
15 to 12 11
reserved
OTG_SE0_ This bit is used by the HC to send SE0 on remote connect.
EN
0 — No SE0 sent on remote connect detection
1 — SE0 (bus reset) sent on remote connect detection
Remark: This bit is normally set when the B-device goes into the
b_wait_acon state (recommended sequence:
LOC_CONN = 0 -> DELAY -> 50 µs -> OTG_SE0_EN = 1 ->
SEL_HC_DC = 0) and is cleared when it comes out of the
b_wait_acon state.
10
A_SRP_
DET_EN
This bit is for the A-device only. If set, the A_SRP_DET bit in the
OtgInterrupt register will be set on detecting an SRP event.
0 — disable
1 — enable
9
A_SEL_
SRP
This bit is for the A-device to select a method for detecting the SRP
event (VBUS pulsing or data line pulsing).
0 — A-device responds to VBUS pulsing
1 — A-device responds to data line pulsing
8
SEL_HC_
DC
This bit is used to select either the DC or the HC that interfaces with
the transceiver.
0 — HC SIE is connected to the OTG transceiver
1 — DC SIE is connected to the OTG transceiver
7
LOC_
PULLDN_
DM
0 — disconnects the on-chip pull-down resistor on DM of the OTG
port
6
LOC_
PULLDN_
DP
0 — disconnects the on-chip pull-down resistor on DP of the OTG
port
5
A_RDIS_
LCON_EN
This bit is for the A-device only. If set, the chip will automatically
enable its pull-up resistor on DP upon detecting a remote disconnect
event. If cleared, the DP pull-up is controlled by the LOC_CONN bit.
1 — connects the on-chip pull-down resistor on DM of the OTG port
1 — connects the on-chip pull-down resistor on DP of the OTG port
0 — disable
1 — enable
Remark: This bit is normally set when the A-device goes into the
a_suspend state and is cleared when it comes out of the a_suspend
state. The LOC_CONN bit must be set before clearing this bit.
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Table 23:
OtgControl register: bit description…continued
Bit
Symbol
Description
4
LOC_
CONN
0 — disconnect the on-chip pull-up resistor on DP of the OTG port
SEL_CP_
EXT
This bit is for the A-device only. This bit is used to choose the power
source to drive VBUS.
3
1 — connect the on-chip pull-up resistor on DP of the OTG port
0 — use on-chip charge pump to drive VBUS
1 — use external power source (+5 V) to drive VBUS
Remark: When using the external power source, the H_PSW1 pin
serves as the power switch that is controlled by the DRV_VBUS bit of
this register.
2
DISCHRG_ This bit is for the B-device only. If set, it will enable a pull-down
VBUS
resistor on VBUS, which will help to speed up discharging of VBUS
below session end threshold voltage.
0 — disable
1 — enable
1
This bit is for the B-device only. If set, it will charge VBUS through a
resistor.
CHRG_
VBUS
0 — disable charging VBUS of the OTG port
1 — enable charging VBUS of the OTG port
0
DRV_VBUS This bit is used to enable the on-chip charge pump or external power
source to drive VBUS. For the B-device, it shall not enable this bit at
any time.
0 — disable driving VBUS of the OTG port
1 — enable driving VBUS of the OTG port
14.2 OtgStatus register (R: 67H)
Code (Hex): 67 — read only
Table 24:
OtgStatus register: bit allocation
Bit
15
14
13
12
11
10
Reset
-
-
-
-
-
-
Access
-
-
-
-
-
Bit
7
6
5
4
RMT_
CONN
Symbol
9
8
SE0_2MS
reserved
0
-
-
R
-
3
2
1
0
B_SESS_
VLD
A_SESS_
VLD
B_SESS_
END
A_VBUS_
VLD
ID_REG
reserved
Symbol
reserved
Reset
-
-
0
0
0
1
0
1
Access
-
-
R
R
R
R
R
R
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Single-chip USB OTG controller
Table 25:
OtgStatus register: bit description
Bit
Symbol
Description
15 to 10
-
reserved
9
SE0_2MS
0 — bus is in SE0 for less than 2 ms
1 — bus is in SE0 for more than 2 ms
8 to 6
-
reserved
5
RMT_
CONN
0 — remote pull-up resistor disconnected
1 — remote pull-up resistor connected
Remark: When the local pull-up resistor on the DP-line is
disabled, a 50 µs delay is applied before RMT_CONN detection
is enabled.
4
B_SESS_VLD
For the B-device (ID_REG = 1), this bit is a B-device session
valid indicator (B_SESS_VLD).
0 — VBUS is lower than VB_SESS_VLD
1 — VBUS is higher than VB_SESS_VLD
3
A_SESS_VLD
For the A-device (ID_REG = 0), this bit is an A-device session
valid indicator (A_SESS_VLD).
0 — VBUS is lower than VA_SESS_VLD
1 — VBUS is higher than VA_SESS_VLD
2
B_SESS_END For the B-device (ID_REG = 1), this bit is a B-device session
end indicator (B_SESS_END).
0 — VBUS is higher than VB_SESS_END
1 — VBUS is lower than VB_SESS_END
1
A_VBUS_VLD
For the A-device (ID_REG = 0), this bit is an A-device VBUS
valid indicator (A_VBUS_VLD).
0 — VBUS is lower than VA_VBUS_VLD
1 — VBUS is higher than VA_VBUS_VLD
0
ID_REG
This bit reflects the logic level of the ID pin.
0 — ID pin is LOW (mini-A plug is inserted in the device’s
mini-AB receptacle)
1 — ID pin is HIGH (no plug or mini-B plug is inserted in the
device’s mini-AB receptacle)
14.3 OtgInterrupt register (R/W: 68H/E8H)
Code (Hex): 68 — read
Code (Hex): E8 — write
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Table 26:
OtgInterrupt register: bit allocation
Bit
15
14
13
Symbol
12
11
reserved
10
9
8
OTG_TMR
_TIMEOUT
B_SE0_
SRP
A_SRP_
DET
Reset
-
-
-
-
-
0
0
0
Access
-
-
-
-
-
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
OTG_
RESUME
OTG_
SUSPND
RMT_
CONN_C
B_SESS_
VLD_C
A_SESS_
VLD_C
B_SESS_
END_C
A_VBUS_
VLD_C
ID_REG_C
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Symbol
Reset
Access
Table 27:
OtgInterrupt register: bit description
Bit
Symbol
Description
15 to 11
-
reserved
10
OTG_TMR_ This bit is set whenever the OTG timer attains time-out. Writing
TIMEOUT
logic 1 clears this bit. Writing logic 0 has no effect.
0 — no event
1 — OTG Timer time-out
9
B_SE0_
SRP
This bit is set whenever the device detects more than 2 ms of SE0.
Writing logic 1 clears this bit. Writing logic 0 has no effect.
0 — no event
1 — bus has been in SE0 for more than 2 ms
8
A_SRP_
DET
This bit is used to detect the session request event (SRP) from the
remote device. The SRP event can be either VBUS pulsing or data
line pulsing. Bit 9 (A_SEL_SRP) of the OtgControl register
determines which SRP is selected. Writing logic 1 clears this bit.
Writing logic 0 has no effect.
0 — no event
1 — SRP is detected
7
OTG_
RESUME
This bit is used to detect a J to K state change when the device is
in the ‘suspend’ state. Writing logic 1 clears this bit. Writing logic 0
has no effect.
0 — no event
1 — a resume signal (J → K) is detected when the bus is in the
‘suspend’ state
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Table 27:
OtgInterrupt register: bit description…continued
Bit
Symbol
Description
6
OTG_
SUSPND
This bit is set whenever the OTG port goes into the suspend state
(bus idle for > 3 ms). Write logic 1 to clear this bit. Writing logic 0
has no effect.
0 — no event
1 — suspend (bus idle for > 3 ms)
5
RMT_
CONN_C
This bit is set whenever the RMT_CONN bit of the OtgStatus
register changes. Write logic 1 to clear this bit. Writing logic 0 has
no effect.
0 — no event
1 — RMT_CONN bit has changed
4
B_SESS_
VLD_C
This bit is set whenever the B_SESS_VLD bit of the OtgStatus
register changes. Write logic 1 to clear this bit. Writing logic 0 has
no effect.
0 — no event
1 — bit B_SESS_VLD has changed
3
A_SESS_
VLD_C
This bit is set whenever the A_SESS_VLD bit of the OtgStatus
register changes. Write logic 1 to clear this bit. Writing logic 0 has
no effect.
0 — no event
1 — bit A_SESS_VLD has changed
2
B_SESS_
END_C
This bit is set whenever the B_SESS_END bit of the OtgStatus
register changes. Write logic 1 to clear this bit. Writing logic 0 has
no effect.
0 — no event
1 — bit B_SESS_END has changed
1
A_VBUS_
VLD_C
This bit is set whenever the A_VBUS_VLD bit of the OtgStatus
register changes. Write logic 1 to clear this bit. Writing logic 0 has
no effect.
0 — no event
1 — bit A_VBUS_VLD has changed
0
ID_REG_C
This bit is set whenever the ID_REG bit of the OtgStatus register
changes. This is an indication that the mini-A plug is inserted or
removed (that is, the ID pin is shorted to ground or pulled HIGH).
Write logic 1 to clear this bit. Writing logic 0 has no effect.
0 — no event
1 — ID_REG bit has changed
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14.4 OtgInterruptEnable register (R/W: 69H/E9H)
Code (Hex): 69 — read
Code (Hex): E9 — write
Table 28:
OtgInterruptEnable register: bit allocation
Bit
15
14
Symbol
13
12
11
reserved
10
9
8
OTG_
TMR_IE
B_SE0_
SRP_IE
A_SRP_
DET_IE
Reset
-
-
-
-
-
0
0
0
Access
-
-
-
-
-
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
OTG_
RESUME_
IE
OTG_
SUSPND_
IE
RMT_
CONN_IE
B_SESS_
VLD_IE
A_SESS_
VLD_IE
B_SESS_
END_IE
A_VBUS_
VLD_IE
ID_REG_
IE
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Symbol
Reset
Access
Table 29:
OtgInterruptEnable register: bit description
Bit
Symbol
Description
15 to 11
-
reserved
10
OTG_
TMR_IE
Logic 1 enables interrupt when the OTG timer attains time-out.
9
B_SE0_
SRP_IE
Logic 1 enables interrupt upon detection of the B_SE0_SRP status
change.
8
A_SRP_
DET_IE
Logic 1 enables interrupt upon detection of the SRP event.
7
OTG_
RESUME_
IE
Logic 1 enables interrupt upon detection of bus resume (J to K
only) event.
6
OTG_
SUSPND_
IE
Logic 1 enables interrupt upon detection of the bus ‘suspend’
status change.
5
RMT_
CONN_IE
Logic 1 enables interrupt upon detection of the RMT_CONN status
change.
4
B_SESS_
VLD_IE
Logic 1 enables interrupt upon detection of B_SESS_VLD status
change.
3
A_SESS_
VLD_IE
Logic 1 enables interrupt upon detection of A_SESS_VLD status
change.
2
B_SESS_
END_IE
Logic 1 enables interrupt upon detection of B_SESS_END status
change.
1
A_VBUS_
VLD_IE
Logic 1 enables interrupt upon detection of A_VBUS_VLD status
change.
0
ID_REG_IE Logic 1 enables interrupt upon detection of the ID_REG status
change.
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14.5 OtgTimer register (R/W: 6AH/EAH)
Code (Hex): 6A — read
Code (Hex): EA — write
Table 30:
OtgTimer register: bit allocation
Bit
Symbol
Reset
Access
Bit
31
30
29
START_
TMR
Access
Bit
Access
Bit
Access
25
24
-
-
-
-
-
-
-
R/W
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TMR_INIT_VALUE[23:16]
TMR_INIT_VALUE[15:8]
Symbol
Reset
26
0
Symbol
Reset
27
reserved
Symbol
Reset
28
TMR_INIT_VALUE[7:0]
Table 31:
OtgTimer register: bit description
Bit
Symbol
Description
31
START_
TMR
This is the start or stop bit of the OTG timer. Writing logic 1 will
cause the OTG timer to load TMR_INIT_VALUE into the counter
and start to count. Writing logic 0 will stop the timer. This bit is
automatically cleared when the OTG timer is timed out.
0 — stop the timer
1 — start the timer
30 to 24
-
reserved
23 to 0
TMR_INIT_ These bits define the initial value used by the OTG timer. The timer
VALUE
interval is 0.01 ms. Maximum timer allowed is 167.772 s.
[23:0]
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14.6 OtgAltTimer register (R/W: 6CH/ECH)
Code (Hex): 6C — read
Code (Hex): EC — write
Table 32:
OtgAltTimer register: bit allocation
Bit
Symbol
Reset
31
30
29
28
START_
TMR
27
26
25
24
reserved
0
-
-
-
-
-
-
-
R/W
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit
15
14
13
12
11
10
9
8
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Access
Bit
Symbol
CURRENT_TIME[23:16]
Symbol
CURRENT_TIME[15:8]
Symbol
CURRENT_TIME[7:0]
Table 33:
OtgAltTimer register: bit description
Bit
Symbol
Description
31
START_
TMR
This is the start or stop bit of the OTG timer 2. Writing logic 1 will
cause the OTG timer 2 to start counting from 0. When the counter
reaches FFFFFFH, this bit is auto-cleared (the counter is stopped).
Writing logic 0 will stop the counting.
If any bit of the OTGInterrupt register is set and the corresponding
bit of the OtgInterruptEnable register is also set, this bit will be
auto-cleared and the current value of the counter will be written to
the CURRENT_TIME field.
0 — stop the timer
1 — start the timer
30 to 24
-
23 to 0
CURRENT_ When read, these bits give the current value of the timer. The
TIME
actual time is CURRENT_TIME × 0.01 ms.
reserved
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15. HC registers
The HC contains a set of on-chip control registers. These registers can be read or
written by the HC Driver (HCD). The Control and Status register set, the Frame
Counter register set and the Root Hub register set are grouped under the category of
HC operational registers (32 bits). These operational registers are made compatible
to Open Host Controller Interface (OpenHCI) operational registers. This enables the
OpenHCI HCD to be ported easily to the ISP1362.
Reserved bits may be defined in future releases of this specification. To ensure
interoperability, the HCD that does not use a reserved field must not assume that the
reserved field contains logic 0. Furthermore, the HCD must always preserve the
values of the reserved field. When a R/W register is modified, the HCD must first read
the register, modify the desired bits and then write the register with the reserved bits
still containing the read value. Alternatively, the HCD can maintain an in-memory
copy of previously written values that can be modified and then written to the
HC register. When there is a write to set or clear the register, bits written to reserved
fields must be logic 0.
As shown in Table 34, the offset locations (the commands for reading registers) of
these operational registers (32-bit registers) are similar to those defined in the OHCI
specification. The addresses, however, are equal to offset divided by 4.
Table 34:
HC Control registers summary
Command (Hex)
Register
Width
Reference
Functionality
HC Control and Status
registers
Read
Write
00
N/A
HcRevision
32
Section 15.1.1 on page 71
01
81
HcControl
32
Section 15.1.2 on page 71
02
82
HcCommandStatus
32
Section 15.1.3 on page 73
03
83
HcInterruptStatus
32
Section 15.1.4 on page 74
04
84
HcInterruptEnable
32
Section 15.1.5 on page 75
05
85
HcInterruptDisable
32
Section 15.1.6 on page 76
0D
8D
HcFmInterval
32
Section 15.2.1 on page 78
0E
8E
HcFmRemaining
32
Section 15.2.2 on page 79
0F
8F
HcFmNumber
32
Section 15.2.3 on page 80
11
91
HcLSThreshold
32
Section 15.2.4 on page 81
12
92
HcRhDescriptorA
32
Section 15.3.1 on page 82
13
93
HcRhDescriptorB
32
Section 15.3.2 on page 84
14
94
HcRhStatus
32
Section 15.3.3 on page 85
15
95
HcRhPortStatus[1]
32
Section 15.3.4 on page 87
16
96
HcRhPortStatus[2]
32
Section 15.3.4 on page 87
20
A0
HcHardwareConfiguration
16
Section 15.4.1 on page 92
21
A1
HcDMAConfiguration
16
Section 15.4.2 on page 94
22
A2
HcTransferCounter
16
Section 15.4.3 on page 95
24
A4
HcµPInterrupt
16
Section 15.4.4 on page 95
25
A5
HcµPInterruptEnable
16
Section 15.4.5 on page 97
HC Root Hub registers
HC DMA and Interrupt
Control registers
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Table 34:
HC Control registers summary…continued
Command (Hex)
Register
Width
Reference
Functionality
N/A
HcChipID
16
Section 15.5.1 on page 98
A8
HcScratch
16
Section 15.5.2 on page 98
HC Miscellaneous
registers
Read
Write
27
28
N/A
A9
HcSoftwareReset
16
Section 15.5.3 on page 99
2C
AC
HcBufferStatus
16
Section 15.6.1 on page 99
32
B2
HcDirectAddressLength
32
HC Buffer RAM
Section 15.6.2 on page 100 Control registers
45
C5
HcDirectAddressData
16
Section 15.6.3 on page 101
30
B0
HcISTLBufferSize
16
Section 15.7.1 on page 101 ISO Transfer registers
40
C0
HcISTL0BufferPort
16
Section 15.7.2 on page 101
42
C2
HcISTL1BufferPort
16
Section 15.7.3 on page 102
47
C7
HcISTLToggleRate
16
Section 15.7.4 on page 102
33
B3
HcINTLBufferSize
16
43
C3
HcINTLBufferPort
16
Section 15.8.1 on page 103 Interrupt Transfer
Section 15.8.2 on page 103 registers
53
D3
HcINTLBlkSize
16
Section 15.8.3 on page 104
17
N/A
HcINTLPTDDoneMap
32
Section 15.8.4 on page 104
18
98
HcINTLPTDSkipMap
32
Section 15.8.5 on page 105
19
99
HcINTLLastPTD
32
Section 15.8.6 on page 105
1A
N/A
HcINTLCurrentActivePTD
16
Section 15.8.7 on page 105
34
B4
HcATLBufferSize
16
44
C4
HcATLBufferPort
16
Section 15.9.1 on page 106 Aperiodic Transfer
Section 15.9.2 on page 106 registers
54
D4
HcATLBlkSize
16
Section 15.9.3 on page 107
1B
N/A
HcATLPTDDoneMap
32
Section 15.9.4 on page 107
1C
9C
HcATLPTDSkipMap
32
Section 15.9.5 on page 108
1D
9D
HcATLLastPTD
32
Section 15.9.6 on page 108
1E
N/A
HcATLCurrentActivePTD
16
Section 15.9.7 on page 108
51
D1
HcATLPTDDoneThresholdCount
16
Section 15.9.8 on page 109
52
D2
HcATLPTDDoneThresholdTimeOut 16
Section 15.9.9 on page 109
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15.1 HC control and status registers
15.1.1
HcRevision register (R: 00H)
The bit allocation of the HcRevision register is given in Table 35.
Code (Hex): 00 — read only
Table 35:
HcRevision register: bit allocation
Bit
31
30
29
28
Symbol
27
26
25
24
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
Bit
Symbol
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
Bit
Symbol
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
Symbol
REV[7:0]
Reset
0
0
0
1
0
0
0
1
Access
R
R
R
R
R
R
R
R
Table 36:
15.1.2
HcRevision register: bit description
Bit
Symbol
Description
31 to 8
−
Reserved
7 to 0
REV[7:0]
Revision: This read-only field contains the Binary-Coded Decimal
(BCD) representation of the version of the HCI specification that is
implemented by this HC. For example, a value of 11H corresponds
to version 1.1. All HC implementations that are compliant with this
specification need to have a value of 11H.
HcControl register (R/W: 01H/81H)
The HcControl register defines the operating modes for the HC. The RWE bit is
modified only by the HCD. Table 37 shows the bit allocation of the register.
Code (Hex): 01 — read
Code (Hex): 81 — write
Table 37:
HcControl register: bit allocation
Bit
31
30
29
28
27
26
25
24
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
Symbol
reserved
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Bit
23
22
21
20
19
18
17
16
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
Reset
-
-
RWE
RWC
reserved
-
-
-
0
0
-
Access
-
-
-
-
-
R/W
R/W
-
Bit
7
6
5
4
3
2
1
0
0
0
-
-
-
-
-
-
R/W
R/W
-
-
-
-
-
-
Symbol
Bit
reserved
Symbol
reserved
Symbol
Reset
Access
HCFS[1:0]
reserved
Table 38:
HcControl register: bit description
Bit
Symbol
Description
31 to 11
-
reserved
10
RWE
RemoteWakeupEnable: This bit is used by the HCD to enable or
disable the remote wake-up feature on detecting upstream resume
signaling. When this bit and the ResumeDetected (RD) bit in
HcInterruptStatus are set, a remote wake-up is signaled to the host
system. Setting this bit has no impact on the generation of
hardware interrupt.
9
RWC
RemoteWakeupConnected: This bit indicates whether the HC
supports remote wake-up signaling. If remote wake-up is
supported and used by the system, it is the responsibility of the
system firmware to set this bit during POST. The HC clears the bit
upon a hardware reset but does not alter it upon a software reset.
Remote wake-up signaling of the host system is host–bus-specific
and is not described in this specification.
8
-
reserved
7 to 6
HCFS[1:0]
HostControllerFunctionalState for USB
00 — USBReset
01 — USBResume
10 — USBOperational
11 — USBSuspend
A transition to USBOperational from another state causes
start-of-frame (SOF) generation to begin 1 ms later. The HCD may
determine whether the HC has begun sending SOFs by reading
the StartofFrame (SF) field of HcInterruptStatus.
This field may be changed by the HC only when it is in the
USBSuspend state. The HC may move from the USBSuspend
state to the USBResume state after detecting the resume signaling
from a downstream port.
The HC enters USBReset after a software reset and a hardware
reset. The latter also resets the Root Hub and asserts subsequent
reset signaling to downstream ports.
5 to 0
-
reserved
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15.1.3
HcCommandStatus register (R/W: 02H/82H)
The HcCommandStatus register is a 4-byte register, and the bit allocation is given in
Table 39. This register is used by the HC to receive commands issued by the HCD,
and it also reflects the current status of the HC. To the HCD, it appears to be a ‘write
to set’ register. The HC must ensure that bits written as logic 1 become set in the
register while bits written as logic 0 remain unchanged in the register. The HCD may
issue multiple distinct commands to the HC without concern for corrupting previously
issued commands. The HCD has normal read access to all bits.
The SchedulingOverrunCount (SOC) field indicates the number of frames with which
the HC has detected the scheduling overrun error. This occurs when the Periodic list
does not complete before the End-of-Frame (EOF). When a scheduling overrun error
is detected, the HC increments the counter and sets the SchedulingOverrun (SO)
field of the HcInterruptStatus register.
Code (Hex): 02 — read
Code (Hex): 82 — write
Table 39:
HcCommandStatus register: bit allocation
Bit
31
30
29
28
Symbol
Reset
Access
Bit
Access
Bit
-
-
-
25
24
-
-
-
-
-
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
reserved
-
-
-
SOC[1:0]
-
-
-
0
0
-
-
-
-
-
-
R
R
15
14
13
12
11
10
9
8
-
-
-
-
Symbol
Reset
26
reserved
Symbol
Reset
27
reserved
-
-
-
-
Access
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
HCR
Reset
-
-
-
-
-
-
-
0
Access
-
-
-
-
-
-
-
R/W
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Table 40:
15.1.4
HcCommandStatus register: bit description
Bit
Symbol
Description
31 to 18
-
reserved
17 to 16
SOC[1:0]
SchedulingOverrunCount: This field is incremented on each
scheduling overrun error. It is initialized to 00B and wraps around
at 11B. It needs to be incremented when a scheduling overrun is
detected even if SchedulingOverrun in HcInterruptStatus has
already been set. This is used by the HCD to monitor any
persistent scheduling problems.
15 to 1
-
reserved
0
HCR
HostControllerReset: This bit is set by the HCD to initiate a
software reset of the HC. Regardless of the functional state of
the HC, it moves to the USBSuspend state in which most of the
operational registers are reset except those stated otherwise. This
bit is cleared by the HC on completing the reset operation. The
reset operation must be completed within 10 ms. This bit, when
set, should not cause a reset to the Root Hub and no subsequent
reset signaling should be asserted to its downstream ports.
HcInterruptStatus register (R/W: 03H/83H)
This register (bit allocation: Table 41) provides the status of the events that cause
hardware interrupts. When an event occurs, the HC sets the corresponding bit in this
register. When a bit is set, a hardware interrupt is generated if the interrupt is enabled
in the HcInterruptEnable register (see Section 15.1.5) and the MasterInterruptEnable
(MIE) bit is set. The HCD may clear specific bits in this register by writing logic 1 to
the bit positions to be cleared. The HC, however, does not clear the bit. The HCD may
not set any of these bits.
Code (Hex): 03 — read
Code (Hex): 83 — write
Table 41:
HcInteruptStatus register: bit allocation
Bit
31
30
29
28
Symbol
27
26
25
24
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
Bit
Symbol
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
Bit
Symbol
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
reserved
RHSC
FNO
UE
RD
SF
reserved
SO
Symbol
Reset
-
0
0
0
0
0
-
0
Access
-
R/W
R/W
R/W
R/W
R/W
-
R/W
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Table 42:
15.1.5
HcInterruptStatus register: bit description
Bit
Symbol
Description
31 to 7
-
reserved
6
RHSC
RootHubStatusChange: This bit is set when the content of
HcRhStatus or the content of any of
HcRhPortStatus[NumberofDownstreamPort] has changed.
5
FNO
FrameNumberOverflow: This bit is set when the MSB of
HcFmNumber (bit 15) changes from logic 0 to 1 or from logic 1
to 0.
4
UE
UnrecoverableError: This bit is set when the HC detects a
system error not related to the USB. The HC should not proceed
with any processing nor signaling before the system error has
been corrected. The HCD clears this bit after the HC has been
reset.
Philips Host Controller Interface (PHCI): Always set to logic 0.
3
RD
ResumeDetected: This bit is set when the HC detects that a
device on the USB is asserting resume signaling. It is the transition
from no resume signaling to resume signaling causing this bit to be
set. This bit is not set when the HCD sets the USBResume state.
2
SF
StartOfFrame: At the start of each frame, this bit is set by the HC
and an SOF is generated.
1
-
reserved
0
SO
SchedulingOverrun: This bit is set when the USB schedules for
current frame overruns. A scheduling overrun also causes the
SchedulingOverrunCount (SOC) of HcCommandStatus to be
incremented.
HcInterruptEnable register (R/W: 04H/84H)
Each enable bit in the HcInterruptEnable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used
to control which events generate a hardware interrupt. When the following three
conditions occur:
• A bit is set in the HcInterruptStatus register
• The corresponding bit in the HcInterruptEnable register is set
• The MasterInterruptEnable (MIE) bit is set.
Then, a hardware interrupt is requested on the host bus.
Writing logic 1 to a bit in the HcInterruptEnable register sets the corresponding bit,
whereas writing logic 0 to a bit in this register leaves the corresponding bit
unchanged. On a read, the current value of this register is returned. Table 43 contains
the bit allocation of the register.
Code (Hex): 04 — read
Code (Hex): 84 — write
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Table 43:
HcInterruptEnable register: bit allocation
Bit
Symbol
Reset
Access
Bit
31
30
29
28
27
MIE
26
25
24
reserved
0
-
-
-
-
-
-
-
R/W
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
Bit
Symbol
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
reserved
RHSC
FNO
UE
RD
SF
reserved
SO
Symbol
Reset
-
0
0
0
0
0
-
0
Access
-
R/W
R/W
R/W
R/W
R/W
-
R/W
Table 44:
HcInterruptEnable register: bit description
Bit
Symbol
Description
31
MIE
MasterInterruptEnable by the HCD: Logic 0 is ignored by the HC.
Logic 1 enables interrupt generation by events specified in other
bits of this register.
30 to 7
-
reserved
6
RHSC
0 — ignore
1 — enable interrupt generation because of Root Hub Status
Change
5
FNO
0 — ignore
1 — enable interrupt generation because of Frame Number
Overflow
4
UE
3
RD
0 — ignore
1 — enable interrupt generation because of Unrecoverable Error
0 — ignore
1 — enable interrupt generation because of Resume Detect
2
SF
0 — ignore
1 — enable interrupt generation because of Start of Frame
1
-
reserved
0
SO
0 — ignore
1 — enable interrupt generation because of Scheduling Overrun
15.1.6
HcInterruptDisable register (R/W: 05H/85H)
Each disable bit in the HcInterruptDisable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is
coupled with the HcInterruptEnable register. Thus, writing logic 1 to a bit in this
register clears the corresponding bit in the HcInterruptEnable register, whereas
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writing logic 0 to a bit in this register leaves the corresponding bit in the
HcInterruptEnable register unchanged. On a read, the current value of the
HcInterruptEnable register is returned. Table 45 provides the bit allocation of the
HcInterruptDisable register.
Code (Hex): 05 — read
Code (Hex): 85 — write
Table 45:
HcInterruptDisable register: bit allocation
Bit
30
29
28
26
25
24
0
-
-
-
-
-
-
-
R/W
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
Access
Bit
31
MIE
reserved
Symbol
Bit
reserved
Symbol
Symbol
27
reserved
reserved
RHSC
FNO
UE
RD
SF
reserved
SO
Reset
-
0
0
0
0
0
-
0
Access
-
R/W
R/W
R/W
R/W
R/W
-
R/W
Table 46:
HcInterruptDisable register: bit description
Bit
Symbol
Description
31
MIE
Logic 0 is ignored by the HC. Logic 1 disables interrupt generation
because of events specified in other bits of this register. This field
is set after a hardware or software reset.
30 to 7
-
reserved
6
RHSC
0 — ignore
1 — disable interrupt generation because of Root Hub Status
Change
5
FNO
0 — ignore
1 — disable interrupt generation because of Frame Number
Overflow
4
UE
0 — ignore
1 — disable interrupt generation because of Unrecoverable Error
3
RD
0 — ignore
1 — disable interrupt generation because of Resume Detect
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Single-chip USB OTG controller
Table 46:
HcInterruptDisable register: bit description…continued
Bit
Symbol
Description
2
SF
0 — ignore
1 — disable interrupt generation because of Start of Frame
1
-
reserved
0
SO
0 — ignore
1 — disable interrupt generation because of Scheduling Overrun
15.2 HC Frame Counter registers
15.2.1
HcFmInterval register (R/W: 0DH/8DH)
The HcFmInterval register (bit allocation: Table 47) contains a 14-bit value that
indicates the bit time interval in a frame between two consecutive SOFs. In addition, it
contains a 15-bit value indicating the full-speed maximum packet size that the HC
may transmit or receive without causing a scheduling overrun. The HCD may carry
out minor adjustments on FrameInterval by writing a new value over the present one
at each SOF. This provides the programmability necessary for the HC to synchronize
with an external clocking resource and to adjust any unknown local clock offset.
Code (Hex): 0D — read
Code (Hex): 8D — write
Table 47:
HcFmInterval register: bit allocation
Bit
31
Symbol
FIT
Reset
Access
Bit
30
29
28
Access
Bit
25
24
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
17
16
FSMPS[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
Symbol
Reset
26
FSMPS[14:8]
Symbol
Reset
27
reserved
-
FI[13:8]
-
1
0
1
1
1
0
Access
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
Access
FI[7:0]
1
1
0
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Table 48:
15.2.2
HcFmInterval register: bit description
Bit
Symbol
Description
31
FIT
FrameIntervalToggle: The HCD toggles this bit whenever it loads
a new value to FrameInterval.
30 to 16
FSMPS
[14:0]
FSLargestDataPacket: Specifies a value that is loaded into the
Largest Data Packet Counter at the beginning of each frame. The
counter value represents the largest amount of data in bits that can
be sent or received by the HC in a single transaction at any given
time without causing a scheduling overrun. The field value is
calculated by the HCD.
15 to 14
-
reserved
13 to 0
FI[13:0]
FrameInterval: Specifies the interval between two consecutive
SOFs in bit times. The nominal value is set to 11999. The HCD
must store the current value of this field before resetting the HC.
Setting the HostControllerReset (HCR) field of the
HcCommandStatus register causes the HC to reset this field to its
nominal value. The HCD may choose to restore the stored value
upon completing the Reset sequence.
HcFmRemaining register (R/W: 0EH/8EH)
The HcFmRemaining register is a 14-bit down counter showing the bit time remaining
in the current frame. The bit allocation is given in Table 49.
Code (Hex): 0E — read
Code (Hex): 8E — write
Table 49:
HcFmRemaining register: bit allocation
Bit
Symbol
Reset
Access
Bit
31
30
29
28
FRT
Access
Bit
0
25
24
-
-
-
-
-
-
-
R/W
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
reserved
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
Symbol
Reset
26
reserved
Symbol
Reset
27
reserved
-
FR[13:8]
-
0
0
0
0
0
0
Access
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
Access
FR[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Single-chip USB OTG controller
Table 50:
15.2.3
HcFmRemaining register: bit description
Bit
Symbol
Description
31
FRT
FrameRemainingToggle: This bit is loaded from the
FrameIntervalToggle (FIT) field of HcFmInterval whenever
FrameRemaining (FR) reaches 0. This bit is used by the HCD for
synchronization between FrameInterval (FI) and FrameRemaining
(FR).
30 to 14
-
reserved
13 to 0
FR[13:0]
FrameRemaining: This counter is decremented at each bit time.
When it reaches zero, it is reset by loading the FrameInterval (FI)
value specified in HcFmInterval at the next bit time boundary.
When entering the USBOperational state, the HC reloads it with
the content of the FrameInterval (FI) part of the HcFmInterval
register and uses the updated value from the next SOF.
HcFmNumber register (R/W: 0FH/8FH)
The HcFmNumber register is a 16-bit counter, and the bit allocation is given in
Table 51. It provides a timing reference for events happening in the HC and the HCD.
The HCD may use the 16-bit value specified in this register and generate a 32-bit
frame number without requiring frequent access to the register.
Code (Hex): 0F — read
Code (Hex): 8F — write
Table 51:
HCFmNumber register: bit allocation
Bit
31
30
29
28
Symbol
Reset
Access
Bit
Access
Bit
26
25
24
-
-
-
-
reserved
-
-
-
-
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
Symbol
Reset
27
reserved
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
Symbol
FN[15:8]
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit
7
6
5
4
3
2
1
0
Symbol
FN[7:0]
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
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Table 52:
15.2.4
HcFmNumber register: bit description
Bit
Symbol
Description
31 to 16
−
reserved
15 to 0
FN[15:0]
FrameNumber: This is incremented when HcFmRemaining is
reloaded. It needs to be rolled over to 0H after FFFFH. When the
USBOperational state is entered, this is incremented automatically.
The content needs to be written to HCCA after the HC has
incremented the FrameNumber (FN) at each frame boundary and
sent an SOF. However, the content needs to be written before
the HC reads the first Endpoint Descriptor (ED) in that frame. After
writing to HCCA, the HC needs to set the StartofFrame (SF) in
HcInterruptStatus.
HcLSThreshold register (R/W: 11H/91H)
The HcLSThreshold register contains an 11-bit value used by the HC to determine
whether to commit to the transfer of a maximum of 8-byte LS packet before the EOF.
Neither the HC nor the HCD is allowed to change this value. Table 53 shows the bit
allocation of the register.
Code (Hex): 11 — read
Code (Hex): 91 — write
Table 53:
HcLSThreshold register: bit allocation
Bit
31
30
29
28
Symbol
27
26
25
24
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
Bit
Symbol
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
Bit
Symbol
reserved
LST[10:8]
Reset
-
-
-
-
-
1
1
0
Access
-
-
-
-
-
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
Access
LST[7:0]
0
0
1
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 54:
HcLSThreshold register: bit description
Bit
Symbol
Description
31 to 11
−
reserved
10 to 0
LST[10:0]
LSThreshold: Contains a value that is compared to the
FrameRemaining (FR) field before a low-speed transaction is
initiated. The transaction is started only if FrameRemaining
(FR) ≥ this field. The value is calculated by the HCD, which
considers transmission and set-up overhead.
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15.3 HC Root Hub registers
All registers included in this partition are dedicated to the USB Root Hub, which is an
integral part of the HC although it is a functionally a separate entity. The HCD
emulates USB Driver (USBD) accesses to the Root Hub by using a register interface.
The HCD maintains many USB-defined hub features that are not required to be
supported in hardware. For example, the Hub’s device, Configuration, Interface and
Endpoint Descriptors are maintained only in the HCD, as well as some static fields of
the Class Descriptor. The HCD also maintains and decodes the address of the Root
Hub device and other trivial operations that are better suited to software than to
hardware.
Root Hub registers are developed to maintain the similarity of bit organization and
operation to typical hubs found in the system.
Four registers are defined as follows:
•
•
•
•
HcRhDescriptorA
HcRhDescriptorB
HcRhStatus
HcRhPortStatus[1:NDP].
Each register is read and written as a DWord. These registers are only written during
initialization to correspond with the system implementation. The HcRhDescriptorA
and HcRhDescriptorB registers should be implemented such that they are writeable,
regardless of the USB states of the HC. HcRhStatus and HcRhPortStatus must be
writeable during the USBOperational state.
15.3.1
HcRhDescriptorA register (R/W: 12H/92H)
The HcRhDescriptorA register is the first register of two describing the characteristics
of the Root Hub. The bit allocation is given in Table 55.
Code (Hex): 12 — read
Code (Hex): 92 — write
Table 55:
HcRhDescriptorA register: bit description
Bit
31
30
29
28
26
25
24
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
17
16
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
Symbol
Reset
Access
Bit
POTPGT[7:0]
Symbol
Bit
27
reserved
Symbol
NOCP
OCPM
DT
NPS
PSM
Reset
-
reserved
-
-
0
1
0
0
1
Access
-
-
-
R/W
R/W
R
R/W
R/W
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Bit
7
6
5
4
3
2
1
Reset
-
-
-
-
-
-
1
0
Access
-
-
-
-
-
-
R
R
Symbol
reserved
0
NDP[1:0]
Table 56:
HcRhDescriptorA register: bit description
Bit
Symbol
31 to 24
POTPGT PowerOnToPowerGoodTime: This byte specifies the duration HCD
[7:0]
has to wait before accessing a powered-on port of the Root Hub. It is
implementation-specific (IS). The unit of time is 2 ms. The duration is
calculated as POTPGT × 2 ms.
23 to 13
-
reserved
12
NOCP
NoOverCurrentProtection: This bit describes how the overcurrent
status for the Root Hub ports are reported. When this bit is cleared, the
OverCurrentProtectionMode (OCPM) field specifies global or per-port
reporting.
Description
0 — overcurrent status is collectively reported for all downstream ports
1 — no overcurrent reporting supported
11
OCPM
OverCurrentProtectionMode: This bit describes how the overcurrent
status for the Root Hub ports are reported. At reset, this field should
reflect the same mode as PowerSwitchingMode. This field is valid only
if the NoOverCurrentProtection (NOCP) field is cleared.
0 — overcurrent status is reported collectively for all downstream ports
1 — overcurrent status is reported on a per-port basis. On power up,
clear this bit and then set it to logic 1
10
DT
DeviceType: This bit specifies that the Root Hub is not a compound
device; it is not permitted. This field should always read as 0.
9
NPS
NoPowerSwitching: This bit is used to specify whether power
switching is supported or ports are always powered. It is
implementation specific. When this bit is cleared, the
PowerSwitchingMode (PSM) bit specifies global or per-port switching.
0 — ports are power switched
1 — ports are always powered on when the HC is powered on
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Table 56:
HcRhDescriptorA register: bit description…continued
Bit
Symbol
Description
8
PSM
PowerSwitchingMode: This bit is used to specify how the power
switching of the Root Hub ports is controlled. It is implementation
specific. This field is valid only if the NoPowerSwitching (NPS) field is
cleared.
0 — all ports are powered at the same time
1 — each port is individually powered. This mode allows port power to
be controlled by either the global switch or per-port switching. If the
PortPowerControlMask (PPCM) bit is set, the port responds to only
port power commands (Set/ClearPortPower). If the port mask is
cleared, then the port is controlled only by the global power switch
(Set/ClearGlobalPower).
15.3.2
7 to 2
-
reserved
1 to 0
NDP[1:0] NumberDownstreamPorts: These bits specify the number of
downstream ports supported by the Root Hub. It is implementation
specific. The maximum number of ports supported is 2.
HcRhDescriptorB register (R/W: 13H/93H)
The HcRhDescriptorB register is the second register of two describing the
characteristics of the Root Hub. These fields are written during initialization to
correspond with the system implementation. Reset values are implementation
specific. Table 57 shows the bit allocation of the register.
Code (Hex): 13 — read
Code (Hex): 93 — write
Table 57:
HcRhDescriptorB register: bit allocation
Bit
31
30
29
28
Symbol
27
26
25
24
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
Bit
Symbol
reserved
PPCM[2:0]
Reset
-
-
-
-
-
Access
-
-
-
-
-
R/W
R/W
R/W
15
14
13
12
11
10
9
8
Bit
Symbol
IS
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
DR[2:0]
Reset
-
-
-
-
-
Access
-
-
-
-
-
R/W
R/W
R/W
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Single-chip USB OTG controller
Table 58:
HcRhDescriptorB register: bit description
Bit
Symbol
Description
31 to 19
-
reserved
18 to 16
PPCM[2:0]
PortPowerControlMask: Each bit indicates whether a port is
affected by a global power control command when
PowerSwitchingMode is set. When set, the power state of the port
is only affected by per-port power control (Set/ClearPortPower).
When cleared, the port is controlled by the global power switch
(Set/ClearGlobalPower). If the device is configured to global
switching mode (PowerSwitchingMode = 0), this field is not valid.
Bit 2 — Ganged-power mask on port 2
Bit 1 — Ganged-power mask on port 1
Bit 0 — reserved
15 to 3
-
reserved
2 to 0
DR[2:0]
DeviceRemovable: Each bit is dedicated to a port of the Root
Hub. When cleared, the attached device is removable. When set,
the attached device is not removable.
Bit 2 — Device attached to port 2
Bit 1 — Device attached to port 1
Bit 0 — reserved
15.3.3
HcRhStatus register (R/W: 14H/94H)
The HcRhStatus register is divided into two parts. The lower word of a DWord
represents the Hub Status field and the upper word represents the Hub Status
Change field. Reserved bits should always be written as logic 0. See Table 59 for bit
allocation of the register.
Code (Hex): 14 — read
Code (Hex): 94 — write
Table 59:
HcRhStatus register: bit allocation
Bit
Symbol
31
30
29
28
CRWE
27
26
25
24
reserved
Reset
0
-
-
-
-
-
-
-
Access
W
-
-
-
-
-
-
-
Bit
23
22
21
20
19
18
17
16
CCIC
LPSC
Reset
-
-
-
-
-
-
0
0
Access
-
-
-
-
-
-
R/W
R/W
15
14
13
12
11
10
9
8
0
-
-
-
-
-
-
-
R/W
-
-
-
-
-
-
-
Symbol
Bit
Symbol
Reset
Access
reserved
DRWE
reserved
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Bit
7
6
5
4
3
2
Reset
-
-
-
-
-
-
Access
-
-
-
-
-
-
Symbol
reserved
Table 60:
1
0
OCI
LPS
0
0
R
R/W
HcRhStatus register: bit description
Bit
Symbol
Description
31
CRWE
On write—ClearRemoteWakeupEnable: Writing logic 1 clears
DeviceRemoveWakeupEnable (DRWE). Writing logic 0 has no
effect.
30 to 18
-
reserved
17
CCIC
OverCurrentIndicatorChange: This bit is set by hardware when a
change has occurred to the OverCurrentIndicator (OCI) field of this
register. The HCD clears this bit by writing logic 1. Writing logic 0
has no effect.
16
LPSC
On read—LocalPowerStatusChange: The Root Hub does not
support the local power status feature. Therefore, this bit is always
read as logic 0.
On write—SetGlobalPower: In the global power mode
(PowerSwitchingMode = 0), logic 1 is written to this bit to turn on
power to all ports (clear PortPowerStatus). In the per-port power
mode, it sets PortPowerStatus only on ports whose
PortPowerControlMask bit is not set. Writing logic 0 has no effect.
15
DRWE
On read—DeviceRemoteWakeupEnable: This bit enables the
bit ConnectStatusChange as a resume event, causing a state
transition from USBSuspend to USBResume and setting the
ResumeDetected interrupt.
0 — ConnectStatusChange is not a remote wake-up event
1 — ConnectStatusChange is a remote wake-up event
On write—SetRemoteWakeupEnable: Writing logic 1 sets
DeviceRemoveWakeupEnable. Writing logic 0 has no effect.
14 to 2
-
reserved
1
OCI
OverCurrentIndicator: This bit reports overcurrent conditions
when global reporting is implemented. When set, an overcurrent
condition exists. When cleared, all power operations are normal. If
per-port overcurrent protection is implemented, this bit is always
logic 0.
0
LPS
On read—LocalPowerStatus: The Root Hub does not support the
local power status feature. Therefore, this bit is always read as
logic 0.
On write—ClearGlobalPower: In the global power mode
(PowerSwitchingMode = 0), logic 1 is written to this bit to turn off
power to all ports (clear PortPowerStatus). In the per-port power
mode, it clears PortPowerStatus only on ports whose
PortPowerControlMask bit is not set. Writing logic 0 has no effect.
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15.3.4
HcRhPortStatus[1:2] register (R/W [1]: 15H/95H; [2]: 16H/96H)
The HcRhPortStatus[1:2] register is used to control and report port events on a
per-port basis. NumberDownstreamPorts represents the number of HcRhPortStatus
registers that are implemented in hardware. The lower word is used to reflect the port
status, whereas the upper word reflects the status change bits. Some status bits are
implemented with special write behavior. If a transaction (token through handshake)
is in progress when a write to change port status occurs, the resulting port status
change must be postponed until the transaction completes. Reserved bits should
always be written logic 0. The bit allocation of the HcRhPortStatus[1:2] register is
given in Table 61.
Code (Hex): [1] = 15, [2] = 16 — read
Code (Hex): [1] = 95, [2] = 96 — write
Table 61:
HcRhPortStatus[1:2] register: bit allocation
Bit
31
30
29
28
27
26
25
24
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
Symbol
Bit
reserved
Symbol
PRSC
OCIC
PSSC
PESC
CSC
Reset
-
-
-
0
0
0
0
0
Access
-
-
-
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
LSDA
PPS
Reset
-
-
-
-
-
-
0
0
Access
-
-
-
-
-
-
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Bit
reserved
Symbol
reserved
Symbol
PRS
POCI
PSS
PES
CCS
Reset
-
reserved
-
-
0
0
0
0
0
Access
-
-
-
R/W
R/W
R/W
R/W
R/W
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Single-chip USB OTG controller
Table 62:
HcRhPortStatus[1:2] register: bit description
Bit
Symbol
Description
31 to 21
-
reserved
20
PRSC
PortResetStatusChange: This bit is set at the end of the 10 ms
port reset signal. The HCD can write logic 1 to clear this bit.
Writing logic 0 has no effect.
0 — port reset is not complete
1 — port reset is complete
19
OCIC
PortOverCurrentIndicatorChange: This bit is valid only if
overcurrent conditions are reported on a per-port basis. This bit is
set when the Root Hub changes the PortOverCurrentIndicator
(POCI) bit. The HCD can write logic 1 to clear this bit. Writing
logic 0 has no effect.
0 — no change in PortOverCurrentIndicator (POCI)
1 — PortOverCurrentIndicator (POCI) has changed
18
PSSC
PortSuspendStatusChange: This bit is set when the full resume
sequence is complete. This sequence includes the 20 ms resume
pulse, LS EOP and 3 ms re-synchronization delay. The HCD can
write logic 1 to clear this bit. Writing logic 0 has no effect. This bit is
also cleared when ResetStatusChange is set.
0 — resume is not completed
1 — resume is completed
17
PESC
PortEnableStatusChange: This bit is set when hardware events
cause the PortEnableStatus (PES) bit to be cleared. Changes from
the HCD writes do not set this bit. The HCD can write logic 1 to
clear this bit. Writing logic 0 has no effect.
0 — no change in PortEnableStatus (PES)
1 — change in PortEnableStatus (PES)
16
CSC
ConnectStatusChange: This bit is set whenever a connect or
disconnect event occurs. The HCD can write logic 1 to clear this
bit. Writing logic 0 has no effect. If CurrentConnectStatus (CCS) is
cleared when a SetPortReset, SetPortEnable or SetPortSuspend
write occurs, this bit is set to force the driver to re-evaluate the
connection status because these writes should not occur if the port
is disconnected.
0 — no change in CurrentConnectStatus (CCS)
1 — change in CurrentConnectStatus (CCS)
Remark: If the DeviceRemovable[NDP] bit is set, this bit is set only
after a Root Hub reset to inform the system that the device is
attached.
15 to 10
-
reserved
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Single-chip USB OTG controller
Table 62:
HcRhPortStatus[1:2] register: bit description…continued
Bit
Symbol
Description
9
LSDA
On read—LowSpeedDeviceAttached: This bit indicates the
speed of the device attached to this port. When set, a low-speed
device is attached to this port. When cleared, a full-speed device is
attached to this port. This field is valid only when
CurrentConnectStatus (CCS) is set.
0 — full-speed device attached
1 — low-speed device attached
On write—ClearPortPower: The HCD clears the PortPowerStatus
(PPS) bit by writing logic 1 to this bit. Writing logic 0 has no effect.
8
PPS
On read—PortPowerStatus: This bit reflects the port power
status, regardless of the type of power switching implemented.
This bit is cleared if an overcurrent condition is detected. The HCD
sets this bit by writing SetPortPower or SetGlobalPower. The HCD
clears this bit by writing ClearPortPower or ClearGlobalPower.
PowerSwitchingMode (PCM) and PortPowerControlMask[NDP]
(PPCM[NDP]) determine which power control switches are
enabled. In the global switching mode (PowerSwitchingMode = 0),
only the Set/ClearGlobalPower command controls this bit. In the
per-port power switching (PowerSwitchingMode = 1), if the
PortPowerControlMask[NDP] (PPCM[NDP]) bit for the port is set,
only Set/ClearPortPower commands are enabled. If the mask is
not set, only Set/ClearGlobalPower commands are enabled. When
port power is disabled, CurrentConnectStatus (CCS),
PortEnableStatus (PES), PortSuspendStatus (PSS) and
PortResetStatus (PRS) should be reset.
0 — port power is OFF
1 — port power is ON
On write—SetPortPower: The HCD writes logic 1 to set the
PortPowerStatus (PPS) bit. Writing logic 0 has no effect.
Remark: This bit always reads logic 1 if power switching is not
supported.
7 to 5
-
reserved
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Single-chip USB OTG controller
Table 62:
HcRhPortStatus[1:2] register: bit description…continued
Bit
Symbol
Description
4
PRS
On read—PortResetStatus: When this bit is set by a write to
SetPortReset, port reset signaling is asserted. When reset is
completed, this bit is cleared when PortResetStatusChange
(PRSC) is set. This bit cannot be set if CurrentConnectStatus
(CCS) is cleared.
0 — port reset signal is not active
1 — port reset signal is active
On write—SetPortReset: The HCD sets the port reset signaling
by writing logic 1 to this bit. Writing logic 0 has no effect. If
CurrentConnectStatus (CCS) is cleared, this write does not set
PortResetStatus (PRS) but instead sets ConnectStatusChange
(CSC). This informs the driver that it attempted to reset a
disconnected port.
3
POCI
On read—PortOverCurrentIndicator: This bit is valid only when
the Root Hub is configured in such a way that overcurrent
conditions are reported on a per-port basis. If per-port overcurrent
reporting is not supported, this bit is set to logic 0. If cleared, all
power operations are normal for this port. If set, an overcurrent
condition exists on this port. This bit always reflects the overcurrent
input signal
0 — no overcurrent condition
1 — overcurrent condition detected
On write—ClearSuspendStatus: The HCD writes logic 1 to
initiate a resume. Writing logic 0 has no effect. A resume is
initiated only if PortSuspendStatus (PSS) is set.
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Single-chip USB OTG controller
Table 62:
HcRhPortStatus[1:2] register: bit description…continued
Bit
Symbol
Description
2
PSS
On read—PortSuspendStatus: This bit indicates whether the port
is suspended or is in the resume sequence. It is set by a
SetSuspendState write and cleared when
PortSuspendStatusChange (PSSC) is set at the end of the resume
interval. This bit cannot be set if CurrentConnectStatus (CCS) is
cleared. This bit is also cleared when PortResetStatusChange
(PRSC) is set at the end of the port reset or when the HC is placed
in the USBResume state. If an upstream resume is in progress, it
should propagate to the HC.
0 — port is not suspended
1 — port is suspended
On write—SetPortSuspend: The HCD sets the
PortSuspendStatus (PSS) bit by writing logic 1 to this bit. Writing
logic 0 has no effect. If CurrentConnectStatus (CCS) is cleared,
this write does not set PortSuspendStatus (PSS); instead it sets
ConnectStatusChange (CSC). This informs the driver that it
attempted to suspend a disconnected port.
1
PES
On read—PortEnableStatus: This bit indicates whether the port is
enabled or disabled. The Root Hub may clear this bit when an
overcurrent condition, disconnect event, switched-off power or
operational bus error, such as babble, is detected. This change
also causes PortEnabledStatusChange to be set. The HCD sets
this bit by writing SetPortEnable and clears it by writing
ClearPortEnable. This bit cannot be set when
CurrentConnectStatus (CCS) is cleared. This bit is also set, if it is
not already, at the completion of a port reset when
ResetStatusChange is set or port suspend when
SuspendStatusChange is set.
0 — port is disabled
1 — port is enabled
On write—SetPortEnable: The HCD sets PortEnableStatus (PES)
by writing logic 1. Writing logic 0 has no effect. If
CurrentConnectStatus (CCS) is cleared, this write does not set
PortEnableStatus (PES), but instead sets ConnectStatusChange
(CSC). This informs the driver that it attempted to enable a
disconnected port.
0
CCS
On read—CurrentConnectStatus: This bit reflects the current
state of the downstream port.
0 — no device connected
1 — device connected
On write—ClearPortEnable: The HCD writes logic 1 to this bit to
clear the PortEnableStatus (PES) bit. Writing logic 0 has no effect.
CurrentConnectStatus (CSC) is not affected by any write.
Remark: This bit always reads 1B when the attached device is
nonremovable (DeviceRemoveable[NDP]).
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15.4 HC DMA and interrupt control registers
15.4.1
HcHardwareConfiguration register (R/W: 20H/A0H)
The bit allocation of the HcHardwareConfiguration register is given in Table 63.
Code (Hex): 20 — read
Code (Hex): A0 — write
Table 63:
HcHardwareConfiguration register: bit allocation
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
15
14
13
12
11
10
9
8
Disable
Suspend_
Wakeup
Global
Power
Down
Connect
PullDown
_DS2
Connect
PullDown
_DS1
Suspend
ClkNotStop
AnalogOC
Enable
OneINT
DACKMode
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
4
3
7
6
5
OneDMA
DACKInput
Polarity
DREQ
Output
Polarity
0
0
1
0
R/W
R/W
R/W
R/W
Table 64:
2
1
0
Interrupt
Output
Polarity
Interrupt
PinTrigger
InterruptPin
Enable
1
0
0
0
R/W
R/W
R/W
R/W
DataBusWidth[1:0]
HcHardwareConfiguration register: bit description
Bit
Symbol
Description
15
DisableSuspend_Wakeup This bit when set to logic 1 disables the function of the
D_SUSPEND/D_WAKEUP and
H_SUSPEND/H_WAKEUP pins. Therefore, these pins
will always remain HIGH and pulling them LOW does
not wake up the HC and the DC.
14
GlobalPowerDown
Set this bit to logic 1 to reduce power consumption of
the OTG ATX in the suspend mode.
13
ConnectPullDown_DS2
0 — disconnect built-in pull-down resistors on H_DM2
and H_DP2
1 — connect built-in pull-down resistors on H_DM2
and H_DP2 for the downstream port 2
Remark: Port 2 is always used as a host port.
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Single-chip USB OTG controller
Table 64:
HcHardwareConfiguration register: bit description…continued
Bit
Symbol
Description
12
ConnectPullDown_DS1
0 — disconnect built-in pull-down resistors on
OTG_DM1 and OTG_DP1
1 — connect built-in pull-down resistors on OTG_DM1
and OTG_DP1
Remark: This bit is effective only when port 1 is
configured as the host port (the OTGMODE pin is
HIGH, and the ID pin is LOW). When port 1 is
configured as the OTG port, (the OTGMODE pin is
LOW), the pull-down resistors on OTG_DM1 and
OTG_DP1 are controlled by the LOC_PULL_DN_DP
and LOC_PULL_DN_DM bits of the OtgControl
register.
11
SuspendClkNotStop
0 — clock can be stopped when suspended
1 — clock cannot be stopped when suspended
10
AnalogOCEnable
0 — use external OC detection; digital input
1 — use on-chip OC detection; analog input
9
OneINT
0 — HC interrupt routed to INT1, DC interrupt routed to
INT2
1 — HC and DC interrupts routed to INT1 only, INT2 is
unused
8
DACKMode
0 — normal operation; DACK1 is used with read and
write signals; power-up value
1 — reserved
7
OneDMA
0 — HC DMA request and acknowledge routed to
DREQ1 and DACK1, DC DMA request and
acknowledge routed to DREQ2 and DACK2
1 — HC and DC DMA requests and acknowledges
routed to DREQ1 and DACK1; DREQ2 and DACK2
unused
6
DACKInputPolarity
5
DREQOutputPolarity
0 — DACK1 is active LOW; power-up value
1 — DACK1 is active HIGH
0 — DREQ1 is active LOW
1 — DREQ1 is active HIGH; power-up value
4 to 3
DataBusWidth[1:0]
01 — microprocessor interface data bus width is 16 bits
Others — reserved
2
InterruptOutputPolarity
0 — INT1 interrupt is active LOW; power-up value
1
InterruptPinTrigger
0 — INT1 interrupt is level-triggered; power-up value
1 — INT1 interrupt is active HIGH
1 — INT1 interrupt is edge-triggered
0
InterruptPinEnable
0 — power-up value
1 — global interrupt pin INT1 is enabled; this bit should
be used with the HcµPInterruptEnable register to
enable pin INT1
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15.4.2
HcDMAConfiguration register (R/W: 21H/A1H)
Table 65 contains the bit allocation of the HcDMAConfiguration register.
Code (Hex): 21 — read
Code (Hex): A1 — write
Table 65:
HcDMAConfiguration register: bit allocation
Bit
15
14
13
12
11
10
9
8
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
Symbol
Symbol
Reset
Access
reserved
DMACounter
Enable
BurstLen[1:0]
DMA
Enable
Buffer_Type_Select[2:0]
DMARead
WriteSelect
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 66:
HcDMAConfiguration register: bit description
Bit
Symbol
Description
15 to 8
-
reserved
7
DMACounterEnable
0 — reserved
1 — DMA counter is enabled. Once the counter is
enabled, the HCD must initialize the HcTransferCounter
register to a non-zero value for DREQ to be raised after
the DMAEnable bit is set to HIGH.
6 to 5
BurstLen[1:0]
00 — single-cycle burst DMA
01 — 4-cycle burst DMA
10 — 8-cycle burst DMA
11 — reserved
I/O bus with 32-bit data path width supports only single
and four cycle DMA burst.
4
DMAEnable
0 — DMA is disabled
1 — DMA is enabled
This bit needs to be reset when the DMA transfer is
completed.
3 to 1
0
Buffer_Type_Select
[2:0]
DMAReadWriteSelect
Bit 3
Bit 2
Bit 1
Buffer Type
0
0
0
ISTL0 (default)
0
0
1
ISTL1
0
1
0
INTL
0
1
1
ATL
1
X
X
Direct Addressing
0 — read from the buffer memory of the HC
1 — write to the buffer memory of the HC
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15.4.3
HcTransferCounter register (R/W: 22H/A2H)
Regardless of the programmed I/O (PIO) or DMA data transfer modes, this register is
used to initialize the number of bytes to be transferred to or from the ISTL, INTL or
ATL buffer RAM. For the count value loaded in the register to take effect, the HCD is
required to set bit 7 of the HcDMAConfiguration register to HIGH. When the count
value has reached, the HC needs to generate an internal EOT signal to set bit 2 of
the HcµPInterrupt register, AllEOInterrupt, and update the HcBufferStatus register.
The bit allocation of the HcTransferCounter register is given in Table 67.
Code (Hex): 22 — read
Code (Hex): A2 — write
Table 67:
15.4.4
HcTransferCounter register: bit description
Bit
Symbol
Access
Value
Description
15 to 0
CounterValue
[15:0]
R/W
0000H
Number of data bytes to be read from or
written to the buffer RAM.
HcµPInterrupt register (R/W: 24H/A4H)
All the bits in this register are active at power-on reset. None of the active bits,
however, will cause an interrupt on the interrupt pin (INT1) unless they are set by the
respective bits in the HcµPInterruptEnable register and bit 0 of the
HcHardwareConfiguration register is also set.
After this register (24H–read) is read, the bits that are active will not be reset until
logic 1 is written to the bits in this register (A4H–write) to clear it.
The bits in this register are cleared only when you write to this register indicating the
bits to be cleared. To clear all the enabled bits in this register, the HCD must write
FFH to this register.
The bit allocation of the HcµPInterrupt register is given in Table 68.
Code (Hex): 24 — read
Code (Hex): A4 — write
Table 68:
HcµPInterrupt register: bit allocation
Bit
15
14
13
Symbol
12
11
10
reserved
9
8
OTG_IRQ
ATL_IRQ
Reset
-
-
-
-
-
-
0
0
Access
-
-
-
-
-
-
R/W
R/W
Bit
Symbol
Reset
Access
7
6
5
4
3
2
1
0
INTL_IRQ
ClkReady
HC
Suspended
OPR_Reg
AllEOT
Interrupt
ISTL_1_
INT
ISTL_0_
INT
SOF_INT
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Table 69:
HcµPInterrupt register: bit description
Bit
Symbol
Description
15 to 10
-
reserved
9
OTG_IRQ
0 — no event
1 — The OTG interrupt event needs to read the OtgInterrupt
register to get the cause of the interrupt.
8
ATL_IRQ
0 — no event
1 — Count value of the HcATLDoneThresholdCount register or the
time-out value of the HcATLPTDDoneThresholdTimeOut register
has reached. The microprocessor is required to read
HcINTLPTDDoneMap to check the PTDs that have completed
their transactions.
7
INTL_IRQ
0 — no event
1 — The HC has detected the last PTD, and there is at least one
interrupt transaction that has received ACK from the device. The
microprocessor is required to read HcINTLPTDDoneMap to check
the PTDs that have received ACK from the device.
6
ClkReady
0 — no event
1 — The HC has awakened from the ‘suspend’ state, and its
internal clock has turned on again.
5
HC
0 — no event
Suspended 1 — The HC has been suspended and no USB activities are sent
from the microprocessor for each ms. The microprocessor can
suspend the HC by setting bits 6 and 7 of the HcControl register to
logic 1. Once the HC is suspended, no SOF needs to be sent to
the devices connected to downstream ports.
4
OPR_Reg
0 — no event
1 — An HC operation has caused a hardware interrupt. It is
necessary for the HCD to read the HcInterruptStatus register to
determine the cause of the interrupt.
3
AllEOT
Interrupt
0 — no event
1 — Data transfer has been completed by using the PIO transfer or
the DMA transfer. This bit is set either when the value of the
HcTransferCounter register has reached zero, or the EOT pin of
the HC is triggered by an external signal.
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Table 69:
HcµPInterrupt register: bit description…continued
Bit
Symbol
Description
2
ISTL_1_
INT
0 — no event
1
ISTL_0_
INT
0
SOF_INT
1 — The transaction of the last PTD stored on the ISTL1 buffer has
been completed. The microprocessor is required to read data from
the ISTL1 buffer. The HCD must first read the HcBufferStatus
register to check the status of the ISTL1 buffer before reading data
to the microprocessor.
0 — no event
1 — The transaction of the last PTD stored on the ISTL0 buffer has
been completed. The microprocessor is required to read data from
the ISTL0 buffer. The HCD must first read the HcBufferStatus
register to check the status of the ISTL0 buffer before reading data
to the microprocessor.
0 — no event
1 — The HC is in the SOF state and it indicates the start of a new
frame. The HCD must first read the HcBufferStatus register to
check the status of the ISTL buffer before reading data to the
microprocessor. For the microprocessor to perform the DMA
transfer of ISO data from or to the ISTL buffer, the HC must first
initialize the HcDMAConfiguration register.
15.4.5
HcµPInterruptEnable register (R/W: 25H/A5H)
The bits 9:0 in this register are the same as those in the HcµPInterrupt register. The
bits in this register are used together with bit 0 of the HcHardwareConfiguration
register to enable or disable the bits in the HcµPInterrupt register.
At power-on, all the bits in this register are masked with logic 0. This means no
interrupt request output on the interrupt pin INT1 can be generated. When a bit is set
to logic 1, the interrupt for that bit is enabled.
The bit allocation of the register is given in Table 70.
Code (Hex): 25 — read
Code (Hex): A5 — write
Table 70:
HcµPInterruptEnable register: bit allocation
Bit
15
14
13
Symbol
12
11
10
reserved
9
8
OTG_IRQ_
Interrupt
Enable
ATL_IRQ_
Interrupt
Enable
Reset
-
-
-
-
-
-
0
0
Access
-
-
-
-
-
-
R/W
R/W
Bit
Symbol
Reset
Access
7
6
5
4
3
2
1
0
INTL_IRQ_
Interrupt
Enable
ClkReady
HC
Suspended
Enable
OPR
Interrupt
Enable
EOT
Interrupt
Enable
ISTL_1
Interrupt
Enable
ISTL_0
Interrupt
Enable
SOF
Interrupt
Enable
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Table 71:
HcµPInterruptEnable register: bit description
Bit
Symbol
Description
15 to 10
-
reserved
9
OTG_IRQ_
InterruptEnable
0 — power-up value
8
ATL_IRQ_
InterruptEnable
0 — power-up value
INTL_IRQ_
InterruptEnable
0 — power-up value
ClkReady
0 — power-up value
7
6
1 — enables the OTG_IRQ interrupt
1 — enables the ATL_IRQ interrupt
1 — enables the INT_IRQ interrupt
1 — enables the ClkReady interrupt
5
HCSuspendedEnable
0 — power-up value
1 — enables the HC suspended interrupt
4
OPRInterruptEnable
3
EOTInterruptEnable
0 — power-up value
1 — enables the 32-bit operational register’s interrupt
0 — power-up value
1 — enables the EOT interrupt
2
ISTL_1Interrupt
Enable
0 — power-up value
1
ISTL_0Interrupt
Enable
0 — power-up value
0
SOFInterrupt
Enable
0 — power-up value
1 — enables the ISTL_1 interrupt
1 — enables the ISTL_0 interrupt
1 — enables the SOF interrupt
15.5 HC miscellaneous registers
15.5.1
HcChipID register (R: 27H)
This register contains the ID of the ISP1362. The upper byte identifies the product
name (here 36H stands for the ISP1362). The lower byte indicates the revision
number of the product including engineering samples. Table 72 contains the bit
description of the register.
Code (Hex): 27 — read only
Table 72:
15.5.2
HcChipID register: bit description
Bit
Symbol
Access Value
15 to 0
CHIPID[15:0] R
3630H
Description
Chip ID of the ISP1362.
HcScratch register (R/W: 28H/A8H)
This register is for the HCD to save and restore values when required. The bit
description is given in Table 73.
Code (Hex): 28 — read
Code (Hex): A8 — write
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Table 73:
15.5.3
HcScratch register: bit description
Bit
Symbol
Access
15 to 0
Scratch[15:0] R/W
Value
Description
0000H
Scratch register value.
HcSoftwareReset register (W: A9H)
This register provides a means for software reset of the HC. To reset the HC, the
HCD must write a reset value of F6H to this register. On receiving this reset value,
the HC resets all the HC and OTG registers, except its buffer memory.
Table 74 contains the bit description of the register.
Code (Hex): A9 — write only
Table 74:
HcSoftwareReset register: bit description
Bit
Symbol
Access
Value
Description
15 to 0
ResetValue
[15:0]
W
0000H
Writing a reset value of F6H causes the HC to
reset all the registers except its buffer memory.
15.6 HC buffer RAM control registers
15.6.1
HcBufferStatus register (R/W: 2CH/ACH)
The bit allocation of the HcBufferStatus register is given in Table 75.
Code (Hex): 2C — read
Code (Hex): AC — write
Table 75:
HcBufferStatus register: bit allocation
Bit
15
14
Symbol
Reset
13
12
11
10
9
8
PairedPTD
PingPong
ISTL1
BufferDone
ISTL0
BufferDone
-
0
0
0
reserved
-
-
-
-
Access
-
-
-
-
-
R
R
R
Bit
7
6
5
4
3
2
1
0
reserved
ISTL1_
Active
Status
ISTL0_
Active
Status
Reset_HW
PingPong
Reg
ATL_Active
INTL_
Active
ISTL1
BufferFull
ISTL0
BufferFull
Symbol
Reset
-
0
0
0
0
0
0
0
Access
-
R
R
R/W
R/W
R/W
R/W
R/W
Table 76:
HcBufferStatus register: bit description
Bit
Symbol
Description
15 to 11
-
reserved
10
PairedPTDPingPong
0 — Ping of paired PTD in ATL is active.
1 — Pong of paired PTD in ATL is active.
9
ISTL1
BufferDone
0 — The ISTL1 buffer has not yet been read by the HC.
8
ISTL0
BufferDone
0 — The ISTL0 buffer has not yet been read by the HC.
1 — The ISTL1 buffer has been read by the HC.
1 — The ISTL0 buffer has been read by the HC.
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Table 76:
HcBufferStatus register: bit description…continued
Bit
Symbol
Description
7
-
reserved
6
ISTL1_ActiveStatus
0 — The ISTL1 buffer is not accessed by the slave host.
1 — The ISTL1 buffer is accessed by the slave host.
5
ISTL0_ActiveStatus
4
Reset_HW
PingPong
Reg
0 — The ISTL0 buffer is not accessed by the slave host.
1 — The ISTL0 buffer is accessed by the slave host.
0 to 1 — resets internal hardware ping pong register to 0
when ATL_Active is 0. The hardware ping pong register
can be read from bit 10 of this register.
1 to 0 — has no effect.
3
ATL_Active
2
INTL_Active
0 — The HC does not process the ATL buffer.
1 — The HC processes the ATL buffer.
0 — The HC does not process the INTL buffer.
1 — The HC processes the INTL buffer.
1
ISTL1BufferFull
0 — The HC does not process the ISTL1 buffer.
1 — The HC processes the ISTL1 buffer.
0
ISTL0BufferFull
0 — The HC does not process the ISTL0 buffer.
1 — The HC processes the ISTL0 buffer.
15.6.2
HcDirectAddressLength register (R/W: 32H/B2H)
The HcDirectAddressLength register is used for direct addressing of the ISTL, INTL
or ATL buffers. This register specifies the starting address of the buffer and byte count
of the data to be addressed. Therefore, it allows the programmer to randomly access
the buffer. The bit allocation of the register is given in Table 77.
Code (Hex): 32 — read
Code (Hex): B2 — write
Table 77:
HcDirectAddressLength register: bit allocation
Bit
31
30
29
Symbol
Reset
Access
Bit
Access
Bit
Symbol
27
26
25
24
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
23
22
21
20
19
18
17
16
Symbol
Reset
28
DataByteCount[15:8]
DataByteCount[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
reserved
BufferStartAddress[14:8]
Reset
0
0
0
0
0
0
0
0
Access
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Bit
7
6
5
4
0
0
0
0
R/W
R/W
R/W
R/W
Symbol
Reset
Access
3
2
1
0
0
0
0
0
R/W
R/W
R/W
R/W
BufferStartAddress[7:0]
15.6.3
Table 78:
HcDirectAddressLength register: bit description
Bit
Symbol
Description
31 to 16
DataByteCount [15:0]
Total number of bytes to be accessed.
15
-
reserved
14 to 0
BufferStartAddress[14:0] The starting address of the buffer for accessing of data.
HcDirectAddressData register (R/W: 45H/C5H)
This is a data port for the HCD to access the ISTL, INTL or ATL buffers under the
direct addressing mode. Table 79 contains the bit description of the register.
Code (Hex): 45 — read
Code (Hex): C5 — write
Table 79:
HcDirectAddressData register: bit description
Bit
Symbol
Access Value
15 to 0
DataWord R/W
[15:0]
Description
0000H The data port for accessing the ISTL, INTL or ATL
buffers. The address of the buffer and byte count of
the data must be specified in the
HcDirectAddressLength register.
15.7 Isochronous (ISO) transfer registers
15.7.1
HcISTLBufferSize register (R/W: 30H/B0H)
This register requires you to allocate the size of the buffer to be used for ISO
transactions. The buffer size specified in the register is applied to the ISTL0 and
ISTL1 buffers. Therefore, ISTL0 and ISTL1 always have the same buffer size.
Table 80 shows the bit description of the register.
Code (Hex): 30 — read
Code (Hex): B0 — write
Table 80:
15.7.2
HcISTLBufferSize register: bit description
Bit
Symbol
Access Value
15 to 0
ISTLBuffer R/W
Size[15:0]
0000H
Description
The size of the buffer to be used for ISO
transactions and must be specified in bytes.
HcISTL0BufferPort register (R/W: 40H/C0H)
In addition to the HcDirectAddressData register, the ISP1362 provides this register to
act as another data port for accessing the ISTL0 buffer. The starting address for
accessing the buffer is always fixed at 0000H. Therefore, random access of the ISTL0
buffer is not allowed. The bit description of the register is given in Table 81.
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Code (Hex): 40 — read
Code (Hex): C0 — write
Table 81:
Bit
HcISTL0BufferPort register: bit description
Symbol
Access Value
15 to 0 DataWord R/W
[15:0]
0000H
Description
The data in the ISTL0 buffer to be accessed
through this data port.
The HCD is first required to initialize the HcTransferCounter register with the byte
count to be transferred and check the HcBufferStatus register. The HCD then sends
the command (40H for reading from the ISTL0 buffer, and C0H for writing to the
ISTL0 buffer) to the HC through the I/O port of the microprocessor. After the
command is sent, the HCD starts reading data from the ISTL0 buffer or writing data to
the ISTL0 buffer. While the HCD is accessing the buffer, the buffer pointer of ISTL0
also increases automatically. When the pointer has reached the initialized byte count
of the HcTransferCounter register, the HC sets the AllEOTInterrupt bit of the
HcµPInterrupt register to logic 1 and updates the HcBufferStatus register.
15.7.3
HcISTL1BufferPort register (R/W: 42H/C2H)
In addition to the HcDirectAddressData register, the ISP1362 provides this register to
act as another data port for accessing the ISTL1 buffer. The starting address for
accessing the buffer is always fixed at 0000H. Therefore, random access of the ISTL1
buffer is not allowed. The bit description of the register is given in Table 82.
Code (Hex): 42 — read
Code (Hex): C2 — write
Table 82:
Bit
HcISTL1BufferPort register: bit description
Symbol
Access Value
15 to 0 DataWord R/W
[15:0]
0000H
Description
The data in the ISTL1 buffer to be accessed
through this data port.
The HCD is first required to initialize the HcTransferCounter register with the byte
count to be transferred and check the HcBufferStatus register. The HCD then sends
the command (42H for reading from the ISTL1 buffer, and C2H for writing to the
ISTL1 buffer) to the HC through the I/O port of the microprocessor. After the
command is sent, the HCD starts reading data from the ISTL1 buffer or writing data to
the ISTL1 buffer. While the HCD is accessing the buffer, the buffer pointer of ISTL1
also increases automatically. When the pointer has reached the initialized byte count
of the HcTransferCounter register, the HC sets the AllEOTInterrupt bit in the
HcµPInterrupt register to logic 1 and updates the HcBufferStatus register.
15.7.4
HcISTLToggleRate register (R/W: 47H/C7H)
The rate of toggling between ISTL0 and ISTL1 is programmable. The
HcISTLToggleRate register is provided for programming the required toggle rate in
the range of 0 ms to 15 ms at intervals of 1 ms. The bit allocation of the register is
shown in Table 83.
Code (Hex): 47 — read
Code (Hex): C7 — write
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Table 83:
HcISTLToggleRate register: bit allocation
Bit
15
14
13
12
Symbol
11
10
9
8
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
ISTLToggleRate[3:0]
Reset
-
-
-
-
0
0
0
0
Access
-
-
-
-
R/W
R/W
R/W
R/W
Table 84:
HcISTLToggleRate register: bit description
Bit
Symbol
Description
15 to 4
-
reserved
3 to 0
ISTLToggleRate[3:0]
The required toggle rate in ms.
15.8 Interrupt transfer registers
15.8.1
HcINTLBufferSize register (R/W: 33H/B3H)
This register allows you to allocate the size of the INTL buffer to be used for interrupt
transactions. The default value of the buffer size is set to 128 bytes, and the
maximum allowable allocated size is 4096 bytes. Table 85 shows the bit description
of the register.
Code (Hex): 33 — read
Code (Hex): B3 — write
Table 85:
Bit
HcINTLBufferSize register: bit description
Symbol
15 to 0 INTLBuffer
Size[15:0]
15.8.2
Access Value
Description
R/W
The size of the buffer to be used for interrupt
transactions and must be specified in bytes.
0080H
HcINTLBufferPort register (R/W: 43H/C3H)
In addition to the HcDirectAddressData register, the ISP1362 provides this register to
act as another data port for accessing the INTL buffer. The starting address for
accessing the buffer is always fixed at 0000H. Therefore, random access of the INTL
buffer is not allowed. The bit description of the HcINTLBufferPort register is given in
Table 86.
Code (Hex): 43 — read
Code (Hex): C3 — write
Table 86:
Bit
HcINTLBufferPort register: bit description
Symbol
Access Value
15 to 0 DataWord R/W
[15:0]
0000H
Description
The data in the INTL buffer to be accessed through
this data port.
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The HCD is first required to initialize the HcTransferCounter register with the byte
count to be transferred and check the HcBufferStatus register. The HCD then sends
the command (43H for reading of the INTL buffer, and C3H for writing to the INTL
buffer) to the HC through the I/O port of the microprocessor. After the command is
sent, the HCD starts reading data from the INTL buffer or writing data to the INTL
buffer. While the HCD is accessing the buffer, the buffer pointer of INTL also
increases automatically. When the pointer has reached the initialized byte count of
the HcTransferCounter register, the HC sets the AllEOTInterrupt bit of the
HcµPInterrupt register to logic 1 and updates the HcBufferStatus register.
15.8.3
HcINTLBlkSize register (R/W: 53H/D3H)
The ISP1362 requires the INTL buffer to be partitioned into several equal sized blocks
so that the HC can skip the current PTD and proceed to process the next PTD easily.
The block size of the INTL buffer is required to be specified in this register and must
be a multiple of 8 bytes. The default value of the block size is 64 bytes, and the
maximum allowable block size is 1024 bytes. Table 87 shows the bit allocation of the
register.
Code (Hex): 53 — read
Code (Hex): D3 — write
Table 87:
HcINTLBlkSize register: bit allocation
Bit
15
14
13
Symbol
12
11
10
reserved
9
8
BlockSize[9:8]
Reset
-
-
-
-
-
-
0
0
Access
-
-
-
-
-
-
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
Access
BlockSize[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 88:
15.8.4
HcINTLBlkSize register: bit description
Bit
Symbol
Description
15 to 10
-
reserved
9 to 0
BlockSize[9:0]
The block size of the INTL buffer.
HcINTLPTDDoneMap register (R: 17H)
This is a 32-bit register, and the bit description is given in Table 89. Every bit of the
register represents the processing status of a PTD. Bit 0 of the register represents the
first PTD stored in the INTL buffer, bit 1 represents the second PTD stored in the
buffer, and so on. The register is updated once every ms by the HC and is cleared
upon read by the HCD. Bits that are set representing its corresponding PTDs are
processed by the HC and the ACK token is received from the device.
Code (Hex): 17 — read only
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Table 89:
Bit
HcINTLPTDDoneMap register: bit description
Symbol
Access
31 to 0 PTDDone R
Bits[31:0]
Value
Description
0000H
0 — The PTD stored in the INTL buffer has not
been successfully processed by the HC.
1 — The PTD stored in the INTL buffer has been
successfully processed by the HC.
15.8.5
HcINTLPTDSkipMap register (R/W: 18H/98H)
This is a 32-bit register, and the bit description is given in Table 90. Bit 0 of the
register represents the first PTD stored in the INTL buffer, bit 1 represents the second
PTD stored in the buffer, and so on. When a bit is set by the HCD, the corresponding
PTD is skipped and is not processed by the HC. The HC processes the skipped PTD
if the HCD has reset its corresponding skipped bit to logic 0. Clearing the
corresponding bit in the HcINTLPTDSkipMap register when there is no valid data in
the block will cause unpredictable behavior of the HC.
Code (Hex): 18 — read
Code (Hex): 98 — write
Table 90:
Bit
HcINTLPTDSkipMap register: bit description
Symbol
31 to 0 SkipBits
[31:0]
15.8.6
Access Value
Description
R/W
0 — The HC processes the PTD.
0000H
1 — The HC skips processing the PTD.
HcINTLLastPTD register (R/W: 19H/99H)
This is a 32-bit register, and Table 91 shows its bit description. Bit 0 of the register
represents the first PTD stored in the INTL buffer, bit 1 represents the second PTD
stored in the buffer, and so on. The bit that is set to logic 1 by the HCD is used as an
indication to the HC that its corresponding PTD is the last PTD stored in the INTL
buffer. When the processing of the last PTD is complete, the HC proceeds to process
ATL transactions.
Code (Hex): 19 — read
Code (Hex): 99 — write
Table 91:
Bit
HcINTLLastPTD register: bit description
Symbol
31 to 0 LastPTD
Bits[31:0]
15.8.7
Acc
ess
Value
Description
R/W
0000H
0 — The PTD is not the last PTD stored in the buffer.
1 — The PTD is the last PTD stored in the buffer.
HcINTLCurrentActivePTD register (R: 1AH)
This register indicates which PTD stored in the INTL buffer is currently active and is
updated by the HC. The HCD can use it as a buffer pointer to decide which PTD
locations are currently free for filling in new PTDs to the buffer. This indication is to
prevent the HCD from accidentally writing into the currently active PTD buffer
location. Table 92 shows the bit allocation of the register.
Code (Hex): 1A — read only
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Table 92:
HcINTLCurrentActivePTD register: bit allocation
Bit
15
14
13
12
Symbol
11
10
9
8
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
ActivePTD[4:0]
Reset
-
-
-
0
0
0
0
0
Access
-
-
-
R
R
R
R
R
Table 93:
HcINTLCurrentActivePTD register: bit description
Bit
Symbol
Description
15 to 5
-
reserved
4 to 0
ActivePTD[4:0]
This 5-bit number represents the PTD that is currently active.
15.9 Control and bulk transfer (aperiodic transfer) registers
15.9.1
HcATLBufferSize register (R/W: 34H/B4H)
This register allows you to allocate the size of the ATL buffer to be used for aperiodic
transactions. The default value of the buffer size is set to 512 bytes, and the
maximum allowable allocated size is 4096 bytes. The bit description of the register is
given in Table 94.
Code (Hex): 34 — read
Code (Hex): B4 — write
Table 94:
Bit
HcATLBufferSize register: bit description
Symbol
15 to 0 ATLBuffer
Size[15:0]
15.9.2
Access Value
Description
R/W
The size of the buffer to be used for aperiodic
transactions and must be specified in bytes.
0200H
HcATLBufferPort register (R/W: 44H/C4H)
In addition to the HcDirectAddressData register, the ISP1362 provides this register to
act as another data port for accessing the ATL buffer. The starting address for
accessing the buffer is always fixed at 0000H. Therefore, random access of the ATL
buffer is not allowed. The bit description of the HcATLBufferPort register is given in
Table 95.
Code (Hex): 44 — read
Code (Hex): C4 — write
Table 95:
Bit
HcATLBufferPort register: bit description
Symbol
15 to 0 DataWord
[15:0]
Access
Value
Description
R/W
0000H
The data of the ATL buffer to be accessed
through this data port.
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The HCD is first required to initialize the HcTransferCounter register with the byte
count to be transferred and check the HcBufferStatus register. The HCD then sends
the command (44H for reading from the ATL buffer, and C4H for writing to the ATL
buffer) to the HC through the I/O port of the microprocessor. After the command is
sent, the HCD starts reading data from the ATL buffer or writing data to the ATL
buffer. While the HCD is accessing the buffer, the buffer pointer of ATL also increases
automatically. When the pointer has reached the initialized byte count of the
HcTransferCounter register, the HC sets the AllEOTInterrupt bit of the HcµPInterrupt
register to logic 1 and updates the HcBufferStatus register.
15.9.3
HcATLBlkSize register (R/W: 54H/D4H)
The ISP1362 partitions the ATL buffer into several equal sized blocks so that the HC
can skip the current PTD and proceed to process the next PTD easily. The block size
of the ATL buffer must be specified in this register and must be a multiple of 8 bytes.
The bit allocation of the HcATLBlkSize register is given in Table 96.
Code (Hex): 54 — read
Code (Hex): D4 — write
Table 96:
HcATLBlkSize register: bit allocation
Bit
15
14
13
12
11
10
9
Reset
-
-
-
-
-
-
0
0
Access
-
-
-
-
-
-
R/W
R/W
Bit
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Symbol
reserved
Symbol
Reset
Access
8
BlockSize[9:8]
BlockSize[7:0]
Table 97:
15.9.4
HcATLBlkSize register: bit description
Bit
Symbol
Description
15 to 10
-
reserved
9 to 0
BlockSize[9:0] The block size of the ATL buffer.
HcATLPTDDoneMap register (R: 1BH)
This is a 32-bit register. The bit description of the register is given in Table 98. Every
bit of the register represents the processing status of a PTD. Bit 0 of the register
represents the first PTD stored in the ATL buffer, bit 1 represents the second PTD
stored in the buffer, and so on. The register is immediately updated after the
completion of each ATL PTD processing. It is cleared upon reading by the HCD. Bits
that are set representing its corresponding PTDs have been processed by the HC
and ACK token has been received from the device.
Code (Hex): 1B — read only
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Table 98:
HcATLPTDDoneMap register: bit description
Bit
Symbol
Access Value
Description
31 to 0
PTDDone
Bits[31:0]
R
0 — The PTD stored in the ATL buffer was not
successfully processed by the HC.
0000H
1 — The PTD stored in the ATL buffer was
successfully processed by the HC.
15.9.5
HcATLPTDSkipMap register (R/W: 1CH/9CH)
This is a 32-bit register, and the bit description is given in Table 99. Bit 0 of the
register represents the first PTD stored in the ATL buffer, bit 1 represents the second
PTD stored in the buffer, and so on. When the bit is set by the HCD, the
corresponding PTD is skipped and is not processed by the HC. The HC processes
the skipped PTD only if the HCD has reset its corresponding skipped bit to logic 0.
Clearing the corresponding bit in the HcATLPTDSkipMap register when there is no
valid data in the block will cause unpredictable behavior of the HC.
Code (Hex): 1C — read
Code (Hex): 9C — write
Table 99:
Bit
HcATLPTDSkipMap register: bit description
Symbol
31 to 0 SkipBits
[31:0]
15.9.6
Access Value
Description
R/W
0 — The HC processes the PTD.
0000H
1 — The HC skips processing the PTD.
HcATLLastPTD register (R/W: 1DH/9DH)
This is a 32-bit register. Table 100 gives the bit description of the register. Bit 0 of the
register represents the first PTD stored in the ATL buffer, bit 1 represents the second
PTD stored in the buffer, and so on. The bit that is set to logic 1 by the HCD is used
as an indication to the HC that its corresponding PTD is the last PTD stored in the
ATL buffer. When the processing of the last PTD is complete, the HC loops back to
process the first PTD stored in the buffer.
Code (Hex): 1D — read
Code (Hex): 9D — write
Table 100: HcATLLastPTD register: bit description
Bit
Symbol
Access Value
31 to 0
LastPTD
Bits[31:0]
R/W
Description
0000H 0 — The PTD is not the last PTD stored in the
buffer.
1 — The PTD is the last PTD stored in the buffer.
15.9.7
HcATLCurrentActivePTD register (R: 1EH)
This register indicates which PTD stored in the ATL buffer is currently active and is
updated by the HC. The HCD can use it as a buffer pointer to decide which PTD
locations are currently free for filling in new PTDs to the buffer. This indication helps
to prevent the HCD from accidentally writing into the currently active PTD buffer
location. Table 101 shows the bit allocation of the register.
Code (Hex): 1E — read only
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Table 101: HcATLCurrentActivePTD register: bit allocation
Bit
15
14
13
12
Symbol
11
10
9
8
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
ActivePTD[4:0]
Reset
-
-
-
0
0
0
0
0
Access
-
-
-
R
R
R
R
R
Table 102: HcATLCurrentActivePTD register: bit description
15.9.8
Bit
Symbol
Description
15 to 5
-
reserved
4 to 0
ActivePTD[4:0] This 5-bit number represents the PTD that is currently active.
HcATLPTDDoneThresholdCount register (R/W: 51H/D1H)
This register specifies the number of ATL PTD done required to trigger an ATL
PTDDoneCount. If set to 0x08, the HC would trigger the ATL interrupt (in the
HcµPInterrupt register) once for every 8 ATL PTD done. Table 103 shows the bit
allocation of the register.
Remark: Do not write 0x0000 to this register.
Code (Hex): 51 — read
Code (Hex): D1 — write
Table 103: HcATLPTDDoneThresholdCount register: bit allocation
Bit
15
14
13
12
Symbol
11
10
9
8
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
PTDDoneCount[4:0]
Reset
-
-
-
0
0
0
0
1
Access
-
-
-
R/W
R/W
R/W
R/W
R/W
Table 104: HcATLPTDDoneThresholdCount register: bit description
15.9.9
Bit
Symbol
Description
15 to 5
-
reserved
4 to 0
PTDDoneCount[4:0]
Number of PTDs processed by the HC.
HcATLPTDDoneThresholdTimeOut register (R/W: 52H/D2H)
This register indicates the number of ms from the last time when the ATL interrupt (in
the HcµPInterrupt register) was set, of which, if the number of ATL PTDDone is still
less than HcATLPTDDoneThresholdCount, the HC would trigger an ATL interrupt (in
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the HcµPInterrupt register) to indicate a time-out situation, provided
HcATLPTDDoneMap is currently 0x0000 0000. Table 105 shows the bit allocation of
the HcATLPTDDone register.
Remark: If the time-out indication is not required by software, or there is no active
PTD in the ATL buffer, write 0x0000 to this register.
Code (Hex): 52 — read
Code (Hex): D2 — write
Table 105: HcATLPTDDoneThresholdTimeOut register: bit allocation
Bit
15
14
13
12
Symbol
Reset
11
10
9
8
-
-
-
-
reserved
-
-
-
-
Access
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
Access
PTDDoneTimeOut[7:0]
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 106: HcATLPTDDoneThresholdTimeOut register: bit description
Bit
Symbol
Description
15 to 8
-
reserved
7 to 0
PTDDoneTimeOut[7:0]
Maximum allowable time in ms for the HC to retry a
transaction with NAK returned.
16. Device Controller (DC) registers
The functions and registers of the DC are accessed using commands, which consist
of a command code followed by optional data bytes (read or write action). An
overview of the available commands and registers is given in Table 107.
A complete access consists of two phases:
1. Command phase: when address pin A0 = HIGH, the DC interprets the data on
the lower byte of the bus (bits D7 to D0) as a command code. Commands without
a data phase are immediately executed.
2. Data phase (optional): when address pin A0 = LOW, the DC transfers the data
on the bus to or from a register or endpoint buffer memory. In case of multi-byte
registers, the least significant byte or word are accessed first.
The following applies to a register or buffer memory access in the 16-bit bus mode:
• The upper byte (bits D15 to D8) in the command phase or the undefined byte in
the data phase are ignored.
• The access of registers is word-aligned: byte access is not allowed.
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• If the packet length is odd, the upper byte of the last word in an IN endpoint buffer
is not transmitted to the host. When reading from an OUT endpoint buffer, the
upper byte of the last word must be ignored by the firmware. The packet length is
stored in the first two bytes of the endpoint buffer.
Table 107: DC command and register summary
Destination
Code (Hex)
Transaction[1]
Write Control OUT Configuration
DcEndpointConfiguration register
endpoint 0 OUT
20
write 1 byte[2]
Write Control IN Configuration
DcEndpointConfiguration register
endpoint 0 IN
21
write 1 byte[2]
Write Endpoint n Configuration
(n = 1 to 14)
DcEndpointConfiguration register
endpoint 1 to 14
22 to 2F
write 1 byte[2]
Read Control OUT Configuration
DcEndpointConfiguration register
endpoint 0 OUT
30
read 1 byte[2]
Read Control IN Configuration
DcEndpointConfiguration register
endpoint 0 IN
31
read 1 byte[2]
Read Endpoint n Configuration
(n = 1 to 14)
DcEndpointConfiguration register
endpoint 1 to 14
32 to 3F
read 1 byte[2]
Write or read Device Address
DcAddress register
B6/B7
write or read 1 byte[2]
Write or read Mode register
DcMode register
B8/B9
write or read 1 byte[2]
Write or read Hardware Configuration
DcHardwareConfiguration register BA/BB
write or read 2 bytes
Write or read DcInterruptEnable
register
DcInterruptEnable register
write or read 4 bytes
Name
Initialization commands
C2/C3
Write or read DMA Configuration
DcDMAConfiguration register
F0/F1
write or read 2 bytes
Write or read DMA Counter
DcDMACounter register
F2/F3
write or read 2 bytes
Reset Device
resets all registers
F6
-
Write Control OUT Buffer
illegal: endpoint is read-only
(00)
-
Write Control IN Buffer
buffer memory endpoint 0 IN
01
N ≤ 64 bytes
Write Endpoint n Buffer
(n = 1 to 14)
buffer memory endpoint 1 to 14
(IN endpoints only)
02 to 0F
isochronous:
N ≤ 1023 bytes
Read Control OUT Buffer
buffer memory endpoint 0 OUT
10
N ≤ 64 bytes
Read Control IN Buffer
illegal: endpoint is write-only
(11)
-
Read Endpoint n Buffer
(n = 1 to 14)
buffer memory endpoint 1 to 14
(OUT endpoints only)
12 to 1F
isochronous:
N ≤ 1023 bytes[4]
Data flow commands
interrupt/bulk: N ≤ 64 bytes
interrupt/bulk: N ≤ 64 bytes
Stall Control OUT Endpoint
Endpoint 0 OUT
40
-
Stall Control IN Endpoint
Endpoint 0 IN
41
-
Stall Endpoint n
(n = 1 to 14)
Endpoint 1 to 14
42 to 4F
-
Read Control OUT Status
DcEndpointStatus register
endpoint 0 OUT
50
read 1 byte[2]
Read Control IN Status
DcEndpointStatus register
endpoint 0 IN
51
read 1 byte[2]
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Table 107: DC command and register summary…continued
Name
Destination
Code (Hex)
Transaction[1]
Read Endpoint n Status
(n = 1 to 14)
DcEndpointStatus register n
endpoint 1 to 14
52 to 5F
read 1 byte[2]
Validate Control OUT Buffer
illegal: IN endpoints only[3]
(60)
-
61
-
IN[3]
Validate Control IN Buffer
buffer memory endpoint 0
Validate Endpoint n Buffer
(n = 1 to 14)
buffer memory endpoint 1 to 14
(IN endpoints only)[3]
62 to 6F
-
Clear Control OUT Buffer
buffer memory endpoint 0 OUT
70
-
Clear Control IN Buffer
illegal[5]
(71)
-
Clear Endpoint n Buffer
(n = 1 to 14)
buffer memory endpoint 1 to 14
(OUT endpoints only)[5]
72 to 7F
Unstall Control OUT Endpoint
Endpoint 0 OUT
80
-
Unstall Control IN Endpoint
Endpoint 0 IN
81
-
Unstall Endpoint n
(n = 1 to 14)
Endpoint 1 to 14
82 to 8F
-
Check Control OUT Status[6]
DcEndpointStatusImage register
endpoint 0 OUT
D0
read 1 byte[2]
Check Control IN Status[6]
DcEndpointStatusImage register
endpoint 0 IN
D1
read 1 byte[2]
Check Endpoint n Status
(n = 1 to 14)[6]
DcEndpointStatusImage register n D2 to DF
endpoint 1 to 14
read 1 byte[2]
Acknowledge Set-up
Endpoint 0 IN and OUT
F4
-
Read Control OUT Error Code
DcErrorCode register
endpoint 0 OUT
A0
read 1 byte[2]
Read Control IN Error Code
DcErrorCode register
endpoint 0 IN
A1
read 1 byte[2]
Read Endpoint n Error Code
(n = 1 to 14)
DcErrorCode register
endpoint 1 to 14
A2 to AF
read 1 byte[2]
General commands
Unlock Device
all registers with write access
B0
write 2 bytes
Write or read DcScratch register
DcScratch register
B2/B3
write or read 2 bytes
Read Frame Number
DcFrameNumber register
B4
read 1 or 2 bytes
Read Chip ID
DcChipID register
B5
read 2 bytes
Read DcInterrupt register
DcInterrupt register
C0
read 4 bytes
[1]
[2]
[3]
[4]
[5]
[6]
With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) divided by 2.
When accessing an 8-bit register in the 16-bit mode, the upper byte is invalid.
Validating an OUT endpoint buffer causes unpredictable behavior of the DC.
During the isochronous transfer in the 16-bit mode, because N ≤ 1023, the firmware must manage the upper byte.
Clearing an IN endpoint buffer causes unpredictable behavior of the DC.
Reads a copy of the Status register: executing this command does not clear any status bits or interrupt bits.
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16.1 Initialization commands
Initialization commands are used during the enumeration process of the USB
network. These commands are used to configure and enable the embedded
endpoints. They also serve to set the USB assigned address of the DC and to
perform a device reset.
16.1.1
DcEndpointConfiguration register (R/W: 30H–3FH/20H–2FH)
This command is used to access the DcEndpointConfiguration register (ECR) of the
target endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction
(OUT/IN), buffer memory size and buffering scheme. It also enables the endpoint
buffer memory. The register bit allocation is shown in Table 108. A bus reset will
disable all endpoints.
The allocation of buffer memory only takes place after all 16 endpoints have been
configured in sequence (from endpoint 0 OUT to endpoint 14). Although the control
endpoints have fixed configurations, they must be included in the initialization
sequence and must be configured with their default values (see Table 14). Automatic
buffer memory allocation starts when endpoint 14 has been configured.
Remark: If any change is made to an endpoint configuration that affects the allocated
memory (size, enable/disable), the buffer memory contents of all endpoints becomes
invalid. Therefore, all valid data must be removed from enabled endpoints before
changing the configuration.
Code (Hex): 20 to 2F — write (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 30 to 3F — read (control OUT, control IN, endpoint 1 to 14)
Transaction — write or read 1 byte (code or data)
Table 108: DcEndpointConfiguration register: bit allocation
Bit
Symbol
Reset
Access
7
6
5
4
3
2
FIFOEN
EPDIR
DBLBUF
FFOISO
0
0
0
R/W
R/W
R/W
1
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
FFOSZ[3:0]
Table 109: DcEndpointConfiguration register: bit description
Bit
Symbol
Description
7
FIFOEN
Logic 1 indicates an enabled buffer memory with allocated
memory. Logic 0 indicates a disabled buffer memory (no bytes
allocated).
6
EPDIR
This bit defines the endpoint direction (0 = OUT, 1 = IN); it also
determines the DMA transfer direction (0 = read, 1 = write).
5
DBLBUF
Logic 1 indicates that this endpoint has double buffering.
4
FFOISO
Logic 1 indicates an isochronous endpoint. Logic 0 indicates a
bulk or interrupt endpoint.
3 to 0
FFOSZ[3:0]
Selects the buffer memory size according to Table 15.
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16.1.2
DcAddress register (R/W: B7H/B6H)
This command is used to set the USB assigned address in the DcAddress register
and enable the USB device. The DcAddress register bit allocation is shown in
Table 110.
A USB bus reset sets the device address to 00H (internally) and enables the device.
The value of the DcAddress register (accessible by the microprocessor) is not altered
by the bus reset. In response to the standard USB request Set Address, the firmware
must issue a Write Device Address command, followed by sending an empty packet
to the host. The new device address is activated when the host acknowledges the
empty packet.
Code (Hex): B6/B7 — write or read DcAddress register
Transaction — write or read 1 byte (code or data)
Table 110: DcAddress register: bit allocation
Bit
7
Symbol
Reset
Access
6
5
4
DEVEN
3
2
1
0
DEVADR[6:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 111: DcAddress register: bit description
16.1.3
Bit
Symbol
Description
7
DEVEN
Logic 1 enables the device.
6 to 0
DEVADR[6:0]
This field specifies the USB device address.
DcMode register (R/W: B9H/B8H)
This command is used to access the DcMode register, which consists of 1 byte (bit
allocation: see Table 112). In the 16-bit bus mode, the upper byte is ignored.
The DcMode register controls the DMA bus width, the resume and suspend modes,
interrupt activity, and SoftConnect operation. It can be used to enable the debug
mode, in which all errors and Not Acknowledge (NAK) conditions will generate an
interrupt.
Code (Hex): B8/B9 — write or read DcMode register
Transaction — write or read 1 byte (code or data)
Table 112: DcMode register: bit allocation
Bit
7
Symbol
6
reserved
5
4
3
2
1
0
GOSUSP
reserved
INTENA
DBGMOD
reserved
SOFTCT
Reset
1[1]
0
0
0
0[1]
0[1]
0[1]
0[1]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[1]
Unchanged by a bus reset.
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Table 113: DcMode register: bit description
Bit
Symbol
Description
7 to 6
-
reserved
5
GOSUSP
Writing logic 1 followed by logic 0 will activate the ‘suspend’
mode.
4
-
reserved
3
INTENA
Logic 1 enables all interrupts. Bus reset value: unchanged.
2
DBGMOD
Logic 1 enables debug mode, in which all NAKs and errors will
generate an interrupt. Logic 0 selects normal operation, in which
interrupts are generated on every ACK (bulk endpoints) or after
every data transfer (isochronous endpoints). Bus reset value:
unchanged.
1
-
reserved
0
SOFTCT
Logic 1 enables SoftConnect. This bit is ignored if EXTPUL = 1
in the DcHardwareConfiguration register (see Table 114). Bus
reset value: unchanged.
Remark: In the OTG mode, this bit is ignored. The LOC_CONN
bit of the OtgControl register controls the pull-up resistor on the
OTG_DP1 pin.
16.1.4
DcHardwareConfiguration register (R/W: BBH/BAH)
This command is used to access the DcHardwareConfiguration register, which
consists of two bytes. The first (lower) byte contains the device configuration and
control values, the second (upper) byte holds the clock control bits and the clock
division factor. The bit allocation is given in Table 114. A bus reset will not change any
of the programmed bit values.
The DcHardwareConfiguration register controls the connection to the USB bus, clock
activity and power supply during the ‘suspend’ state, as well as output clock
frequency, DMA operating mode and pin configurations (polarity, signalling mode).
Code (Hex): BA/BB — write or read DcHardwareConfiguration register
Transaction — write or read 2 bytes (code or data)
Table 114: DcHardwareConfiguration register: bit allocation
Bit
15
14
13
12
reserved
EXTPUL
NOLAZY
CLKRUN
Reset
-
0
1
0
0
Access
-
R/W
R/W
R/W
R/W
Symbol
Bit
Symbol
Reset
Access
11
9
8
0
1
1
R/W
R/W
R/W
CKDIV[3:0]
7
6
5
4
3
2
1
0
DAKOLY
DRQPOL
DAKPOL
reserved
WKUPCS
reserved
INTLVL
INTPOL
0
1
0
0
0
1
0
0
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
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Table 115: DcHardwareConfiguration register: bit description
16.1.5
Bit
Symbol
Description
15
-
reserved
14
EXTPUL
Logic 1 indicates that an external 1.5 kΩ pull-up resistor is used
on pin OTG_DP1 (in the device mode) and that SoftConnect is
not used. Bus reset value: unchanged.
13
NOLAZY
Logic 1 disables output on pin CLKOUT of the LazyClock
frequency (115 kHz ± 50 %) during the ‘suspend’ state. Logic 0
causes pin CLKOUT to switch to LazyClock output after
approximately 2 ms delay, following the setting of bit GOSUSP
of the DcMode register. Bus reset value: unchanged.
12
CLKRUN
Logic 1 indicates that the internal clocks are always running,
even during the ‘suspend’ state. Logic 0 switches off the internal
oscillator and PLL, when they are not needed. During the
‘suspend’ state, this bit must be made logic 0 to meet the
suspend current requirements. The clock is stopped after a
delay of approximately 2 ms, following the setting of
bit GOSUSP of the DcMode register. Bus reset value:
unchanged.
11 to 8
CKDIV[3:0]
This field specifies the clock division factor N, which controls the
clock frequency on output CLKOUT. The output frequency in
MHz is given by 48 ⁄ ( N + 1 ) . The clock frequency range is
3 MHz to 48 MHz (N = 0 to 15), with a reset value of 12 MHz
(N = 3). The hardware design guarantees no glitches during
frequency change. Bus reset value: unchanged.
7
DAKOLY
Logic 1 selects the DACK-only DMA mode. Logic 0 selects the
8237 compatible DMA mode. Bus reset value: unchanged.
6
DRQPOL
Selects the DREQ2 pin signal polarity (0 = active LOW;
1 = active HIGH). Bus reset value: unchanged.
5
DAKPOL
Selects the DACK2 pin signal polarity (0 = active LOW;
1 = active HIGH). Bus reset value: unchanged.
4
-
reserved
3
WKUPCS
Logic 1 enables remote wake-up using a LOW level on input CS.
Bus reset value: unchanged.
2
-
reserved
1
INTLVL
Selects the interrupt signalling mode on output (0 = level;
1 = pulsed). In the pulsed mode, an interrupt produces 166 ns
pulse. Bus reset value: unchanged.
0
INTPOL
Selects the INT2 signal polarity (0 = active LOW; 1 = active
HIGH). Bus reset value: unchanged.
DcInterruptEnable register (R/W: C3H/C2H)
This command is used to individually enable or disable interrupts from all endpoints,
as well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT,
suspend, resume, reset). A bus reset will not change any of the programmed bit
values.
The command accesses the DcInterruptEnable register, which consists of 4 bytes.
The bit allocation is given in Table 116.
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Code (Hex): C2/C3 — write or read InterruptEnable register
Transaction — write or read 4 bytes (code or data)
Table 116: DcInterruptEnable register: bit allocation
Bit
31
30
29
28
Symbol
27
26
25
24
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
IEP14
IEP13
IEP12
IEP11
IEP10
IEP9
IEP8
IEP7
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
IEP6
IEP5
IEP4
IEP3
IEP2
IEP1
IEP0IN
IEP0OUT
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
reserved
SP_IEEOT
IEPSOF
IESOF
IEEOT
IESUSP
IERESM
IERST
Reset
-
0
0
0
0
0
0
0
Access
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 117: DcInterruptEnable register: bit description
16.1.6
Bit
Symbol
Description
31 to 24
-
reserved; must write logic 0
23 to 10
IEP14 to IEP1 Logic 1 enables interrupts from the indicated endpoint.
9
IEP0IN
Logic 1 enables interrupts from the control IN endpoint.
8
IEP0OUT
Logic 1 enables interrupts from the control OUT endpoint.
7
-
reserved
6
SP_IEEOT
Logic 1 enables interrupt upon detection of a short packet.
5
IEPSOF
Logic 1 enables 1 ms interrupts upon detection of Pseudo SOF.
4
IESOF
Logic 1 enables interrupt upon the SOF detection.
3
IEEOT
Logic 1 enables interrupt upon the EOT detection.
2
IESUSP
Logic 1 enables interrupt upon detection of a ‘suspend’ state.
1
IERESM
Logic 1 enables interrupt upon detection of a ‘resume’ state.
0
IERST
Logic 1 enables interrupt upon detection of a bus reset.
DcDMAConfiguration (R/W: F1H/F0H)
This command defines the DMA configuration of the DC and enables or disables
DMA transfers. The command accesses the DcDMAConfiguration register, which
consists of two bytes. The bit allocation is given in Table 118. A bus reset will clear
bit DMAEN (DMA disabled), all other bits remain unchanged.
Code (Hex): F0/F1 — write or read DMA Configuration
Transaction — write or read 2 bytes (code or data)
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Table 118: DcDMAConfiguration register: bit allocation
Bit
15
14
CNTREN
SHORTP
Reset
0[1]
0[1]
-
-
-
-
-
-
Access
R/W
R/W
-
-
-
-
-
-
7
6
5
4
3
2
1
0
DMAEN
reserved
Reset
0[1]
0[1]
0[1]
0[1]
0
Access
R/W
R/W
R/W
R/W
R/W
Symbol
Bit
Symbol
[1]
13
12
11
10
9
8
reserved
EPDIX[3:0]
BURSTL[1:0]
-
0[1]
0[1]
-
R/W
R/W
Unchanged by a bus reset.
Table 119: DcDMAConfiguration register: bit description
Bit
Symbol
Description
15
CNTREN
Logic 1 enables the generation of an EOT condition, when the
DcDMACounter register reaches zero. Bus reset value:
unchanged.
14
SHORTP
Logic 1 enables the short or empty packet mode. When
receiving (OUT endpoint) a short or empty packet, an EOT
condition is generated. When transmitting (IN endpoint), this bit
should be cleared. Bus reset value: unchanged.
13 to 8
-
reserved
7 to 4
EPDIX[3:0]
Indicates the destination endpoint for DMA, see Table 17.
3
DMAEN
Writing logic 1 enables DMA transfer, logic 0 forces the end of
an ongoing DMA transfer. Reading this bit indicates whether
DMA is enabled (0 = DMA stopped; 1 = DMA enabled). This bit
is cleared by a bus reset.
2
-
reserved
1 to 0
BURSTL[1:0]
Selects the DMA burst length:
00 — single-cycle mode (1 byte)
01 — burst mode (4 bytes)
10 — burst mode (8 bytes)
11 — burst mode (16 bytes)
Bus reset value: unchanged.
16.1.7
DcDMACounter register (R/W: F3H/F2H)
This command accesses the DcDMACounter register, which consists of two bytes.
The bit allocation is given in Table 120. Writing to the register sets the number of
bytes for a DMA transfer. Reading the register returns the number of remaining bytes
in the current transfer. A bus reset will not change the programmed bit values.
The internal DMA counter is automatically reloaded from the DcDMACounter register
when DMA is re-enabled (DMAEN = 1). See Section 16.1.6 for more details.
Code (Hex): F2/F3 — write or read DcDMACounter register
Transaction — write or read 2 bytes (code or data)
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Table 120: DcDMACounter register: bit allocation
Bit
15
14
13
12
Symbol
Reset
Access
Bit
Access
10
9
8
DMACR[15:8]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Symbol
Reset
11
DMACR[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 121: DcDMACounter register: bit description
16.1.8
Bit
Symbol
Description
15 to 0
DMACR[15:0]
DcDMACounter register
Reset Device (F6H)
This command resets the DC in the same way as an external hardware reset by using
the input RESET. All registers are initialized to their ‘reset’ values.
Code (Hex): F6 — reset the device
Transaction — none (code only)
16.2 Data flow commands
Data flow commands are used to manage the data transmission between the USB
endpoints and the system microprocessor. Much of the data flow is initiated using an
interrupt to the microprocessor. The data flow commands are used to access the
endpoints and determine whether the endpoint buffer memory contains valid data.
Remark: The IN buffer of an endpoint contains input data for the host. The OUT
buffer receives output data from the host.
16.2.1
Write or read Endpoint Buffer (R/W: 10H,12H–1FH/01H–0FH)
This command is used to access endpoint buffer memory for reading or writing. First,
the buffer pointer is reset to the beginning of the buffer. Following the command, a
maximum of (N + 2) bytes can be written or read, N representing the size of the
endpoint buffer. For 16-bit access, the maximum number of words is (M + 1), with M
given by (N + 1) divided by 2. After each read or write action, the buffer pointer is
automatically incremented by two.
In direct memory access (DMA), the first two bytes or the first word (the packet
length) are skipped: transfers start at the third byte or the second word of the
endpoint buffer. When reading, the DC can detect the last byte or word by using the
EOP condition. When writing to a bulk or interrupt endpoint, the endpoint buffer must
be completely filled before sending data to the host. Exception: when a DMA transfer
is stopped by an external EOT condition, the current buffer content (full or not) is sent
to the host.
Remark: Reading data after a Write Endpoint Buffer command or writing data after a
Read Endpoint Buffer command data will cause unpredictable behavior of the DC.
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Code (Hex): 01 to 0F — write (control IN, endpoint 1 to 14)
Code (Hex): 10, 12 to 1F — read (control OUT, endpoint 1 to 14)
Transaction — write or read maximum N + 2 bytes (isochronous endpoint: N ≤ 1023,
bulk/interrupt endpoint: N ≤ 32) (code or data)
The data in the endpoint buffer memory must be organized as shown in Table 122. An
example of endpoint buffer memory access is given in Table 123.
Table 122: Endpoint buffer memory organization
Word #
Description
0 (lower byte)
packet length (lower byte)
0 (upper byte)
packet length (upper byte)
1 (lower byte)
data byte 1
1 (upper byte)
data byte 2
…
…
M = (N + 1)/2
data byte N
Table 123: Example of endpoint buffer memory access
A0
Phase
Bus lines
Word #
Description
HIGH
command
D[7:0]
-
command code (00H to 1FH)
D[15:8]
-
ignored
LOW
data
D[15:0]
0
packet length
LOW
data
D[15:0]
1
data word 1 (data byte 2, data byte 1)
LOW
data
D[15:0]
2
data word 2 (data byte 4, data byte 3)
…
…
…
…
…
Remark: There is no protection against writing or reading past a buffer’s boundary,
against writing into an OUT buffer or reading from an IN buffer. Any of these actions
could cause an incorrect operation. Data residing in an OUT buffer is only meaningful
after a successful transaction. Exception: during DMA access of a double-buffered
endpoint, the buffer pointer automatically points to the secondary buffer after
reaching the end of the primary buffer.
16.2.2
Read Endpoint Status (R: 50H–5FH)
This command is used to read the status of an endpoint buffer memory. The
command accesses the DcEndpointStatus register, the bit allocation of which is
shown in Table 124. Reading the DcEndpointStatus register will clear the interrupt bit
set for the corresponding endpoint in the DcInterrupt register (see Table 140).
All bits of the DcEndpointStatus register are read-only. Bit EPSTAL is controlled by
the Stall or Unstall commands and by the reception of a SET-UP token (see
Section 16.2.3).
Code (Hex): 50 to 5F — read (control OUT, control IN, endpoint 1 to 14)
Transaction — read 1 byte (code only)
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Table 124: DcEndpointStatus register: bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVER
WRITE
SETUPT
CPUBUF
reserved
Reset
0
0
0
0
0
0
0
-
Access
R
R
R
R
R
R
R
-
Table 125: DcEndpointStatus register: bit description
Bit
Symbol
Description
7
EPSTAL
This bit indicates whether the endpoint is stalled or not
(1 = stalled; 0 = not stalled).
Set to logic 1 by a Stall Endpoint command, cleared to logic 0 by
an Unstall Endpoint command. The endpoint is automatically
unstalled on receiving a SET-UP token.
6
EPFULL1
Logic 1 indicates that the secondary endpoint buffer is full.
5
EPFULL0
Logic 1 indicates that the primary endpoint buffer is full.
4
DATA_PID
This bit indicates the data PID of the next packet (0 = DATA PID;
1 = DATA1 PID).
3
OVERWRITE
This bit is set by hardware. Logic 1 indicates that a new Set-up
packet has overwritten the previous set-up information, before it
was acknowledged or before the endpoint was stalled. This bit is
cleared by reading, if writing the set-up data has finished.
Firmware must check this bit before sending an Acknowledge
Set-up command or stalling the endpoint. Upon reading logic 1,
the firmware must stop ongoing set-up actions and wait for a
new Set-up packet.
16.2.3
2
SETUPT
Logic 1 indicates that the buffer contains a Set-up packet.
1
CPUBUF
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer; 1 = secondary buffer).
0
-
reserved
Stall Endpoint or Unstall Endpoint (40H–4FH/80H–8FH)
These commands are used to stall or unstall an endpoint. The commands modify the
content of the DcEndpointStatus register (see Table 124).
A stalled control endpoint is automatically unstalled when it receives a SET-UP token,
regardless of the packet content. If the endpoint should stay in its stalled state, the
microprocessor can re-stall it with the Stall Endpoint command.
When a stalled endpoint is unstalled (either by using the Unstall Endpoint command
or by receiving a SET-UP token), it is also re-initialized. This flushes the buffer: if it is
an OUT buffer, it waits for a DATA 0 PID; if it is an IN buffer, it writes a DATA 0 PID.
Code (Hex): 40 to 4F — stall (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 80 to 8F — unstall (control OUT, control IN, endpoint 1 to 14)
Transaction — none (code only)
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16.2.4
Validate Endpoint Buffer (61H–6FH)
This command signals the presence of valid data for transmission to the USB host, by
setting the Buffer Full flag of the selected IN endpoint. This indicates that the data in
the buffer is valid and can be sent to the host, when the next IN token is received. For
a double-buffered endpoint, this command switches the current buffer memory for
CPU access.
Remark: For special aspects of the control IN endpoint, see Section 13.3.6.
Code (Hex): 61 to 6F — validate endpoint buffer (control IN, endpoint 1 to 14)
Transaction — none (code only)
16.2.5
Clear Endpoint Buffer (70H, 72H–7FH)
This command unlocks and clears the buffer of the selected OUT endpoint, allowing
the reception of new packets. Reception of a complete packet causes the Buffer Full
flag of an OUT endpoint to be set. Any subsequent packets are refused by returning a
NAK condition, until the buffer is unlocked using this command. For a double-buffered
endpoint, this command switches the current buffer memory for CPU access.
Remark: For special aspects of the control OUT endpoint, see Section 13.3.6.
Code (Hex): 70, 72 to 7F — clear endpoint buffer (control OUT, endpoint 1 to 14)
Transaction — none (code only)
16.2.6
DcEndpointStatusImage register (D0H–DFH)
This command is used to check the status of the selected endpoint buffer memory
without clearing any status or interrupt bits. The command accesses the
DcEndpointStatusImage register, which contains a copy of the DcEndpointStatus
register. The bit allocation of the DcEndpointStatusImage register is shown in
Table 126.
Code (Hex): D0 to DF — check status (control OUT, control IN, endpoint 1 to 14)
Transaction — write or read 1 byte (code or data)
Table 126: DcEndpointStatusImage register: bit allocation
Bit
7
6
5
4
3
2
1
0
EPSTAL
EPFULL1
EPFULL0
DATA_PID
OVER
WRITE
SETUPT
CPUBUF
reserved
Reset
0
0
0
0
0
0
0
-
Access
R
R
R
R
R
R
R
-
Symbol
Table 127: DcEndpointStatusImage register: bit description
Bit
Symbol
Description
7
EPSTAL
This bit indicates whether the endpoint is stalled or not
(1 = stalled; 0 = not stalled).
6
EPFULL1
Logic 1 indicates that the secondary endpoint buffer is full.
5
EPFULL0
Logic 1 indicates that the primary endpoint buffer is full.
4
DATA_PID
This bit indicates the data PID of the next packet
(0 = DATA0 PID; 1 = DATA1 PID).
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Table 127: DcEndpointStatusImage register: bit description…continued
Bit
Symbol
Description
3
OVERWRITE
This bit is set by hardware. Logic 1 indicates that a new Set-up
packet has overwritten the previous set-up information, before it
was acknowledged or before the endpoint was stalled. This bit is
cleared by reading, if writing the set-up data has finished.
Firmware must check this bit before sending an Acknowledge
Set-up command or stalling the endpoint. Upon reading logic 1,
the firmware must stop ongoing set-up actions and wait for a
new Set-up packet.
16.2.7
2
SETUPT
Logic 1 indicates that the buffer contains a Set-up packet.
1
CPUBUF
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer; 1 = secondary buffer).
0
-
reserved
Acknowledge Set-up (F4H)
This command acknowledges to the host that a Set-up packet was received. The
arrival of a Set-up packet disables the Validate Buffer and Clear Buffer commands for
the control IN and OUT endpoints. The microprocessor needs to re-enable these
commands by sending an Acknowledge Set-up command, see Section 13.3.6.
Code (Hex): F4 — acknowledge set-up
Transaction — none (code only)
16.3 General commands
16.3.1
Read Endpoint Error Code (R: A0H–AFH)
This command returns the status of the last transaction of the selected endpoint, as
stored in the DcErrorCode register. Each new transaction overwrites the previous
status information. The bit allocation of the DcErrorCode register is shown in
Table 128.
Code (Hex): A0 to AF — read error code (control OUT, control IN, endpoint 1 to 14)
Transaction — read 1 byte (code or data)
Table 128: DcErrorCode register: bit allocation
Bit
7
6
5
UNREAD
DATA01
reserved
Reset
0
0
-
0
0
0
0
0
Access
R
R
-
R
R
R
R
R
Symbol
4
3
2
1
ERROR[3:0]
0
RTOK
Table 129: DcErrorCode register: bit description
Bit
Symbol
Description
7
UNREAD
Logic 1 indicates that a new event occurred before the previous
status was read.
6
DATA01
This bit indicates the PID type of the last successfully received
or transmitted packet (0 = DATA0 PID; 1 = DATA1 PID).
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Table 129: DcErrorCode register: bit description…continued
Bit
Symbol
Description
5
-
reserved
4 to 1
ERROR[3:0]
Error code. For error description, see Table 130.
0
RTOK
Logic 1 indicates that data was successfully received or
transmitted.
Table 130: Transaction error codes
16.3.2
Error code
(Binary)
Description
0000
no error
0001
PID encoding error; bits 7 to 4 are not the inverse of bits 3 to 0
0010
PID unknown; encoding is valid, but PID does not exist
0011
unexpected packet; packet is not of the expected type (token, data or
acknowledge) or is a SET-UP token to a non-control endpoint
0100
token CRC error
0101
data CRC error
0110
time-out error
0111
babble error
1000
unexpected end-of-packet
1001
sent or received NAK (Not AcKnowledge)
1010
sent Stall; a token was received, but the endpoint was stalled
1011
overflow; the received packet was larger than the available buffer space
1100
sent empty packet (ISO only)
1101
bit stuffing error
1110
sync error
1111
wrong (unexpected) toggle bit in DATA PID; data was ignored
Unlock Device (B0H)
This command unlocks the DC from write-protection mode after a ‘resume’. In the
‘suspend’ state, all registers and buffer memory are write-protected to prevent data
corruption by external devices during a ‘resume’. Also, the register access for reading
is possible only after the ‘unlock device’ command is executed.
After waking up from the ‘suspend’ state, the firmware must unlock the registers and
buffer memory by using this command, by writing the unlock code (AA37H) into the
DcLock register (8-bit bus: lower byte first). The bit allocation of the DcLock register is
given in Table 131.
Code (Hex): B0 — unlock the device
Transaction — write 2 bytes (unlock code) (code or data)
Table 131: DcLock register: bit allocation
Bit
15
14
13
Symbol
12
11
10
9
8
UNLOCK[15:8] = AAH
Reset
1
0
1
0
1
0
1
0
Access
W
W
W
W
W
W
W
W
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ISP1362
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Single-chip USB OTG controller
Bit
7
6
5
4
Reset
0
0
1
1
Access
W
W
W
W
Symbol
3
2
1
0
0
1
1
1
W
W
W
W
UNLOCK[7:0] = 37H
Table 132: DcLock register: bit description
16.3.3
Bit
Symbol
Description
15 to 0
UNLOCK[15:0]
Sending data AA37H unlocks the internal registers and buffer
memory for writing, following a ‘resume’.
DcScratch register (R/W: B3H/B2H)
This command accesses the 16-bit DcScratch register, which can be used by the
firmware to save and restore information. For example, the device status before
powering down in the ‘suspend’ state. The register bit allocation is given in Table 133.
Code (Hex): B2/B3 — write or read DcScratch register
Transaction — write or read 2 bytes (code or data)
Table 133: DcScratch Information register: bit allocation
Bit
15
Symbol
14
13
12
11
reserved
10
9
8
SFIR[12:8]
Reset
-
-
-
0
0
0
0
0
Access
-
-
-
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Symbol
Reset
Access
SFIR[7:0]
Table 134: DcScratch Information register: bit description
16.3.4
Bit
Symbol
Description
15 to 13
-
reserved; must be logic 0
12 to 0
SFIR[12:0]
Scratch Information register
DcFrameNumber register (R: B4H)
This command returns the frame number of the last successfully received SOF. It is
followed by reading one word from the DcFrameNumber register, containing the
frame number. The DcFrameNumber register is shown in Table 135.
Remark: After a bus reset, the value of the DcFrameNumber register is undefined.
Code (Hex): B4 — read frame number
Transaction — read 1 or 2 bytes (code or data)
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Single-chip USB OTG controller
Table 135: DcFrameNumber register: bit allocation
Bit
15
14
Symbol
13
12
11
10
reserved
9
8
SOFR[9:8]
Reset [1]
-
-
-
-
-
0
0
0
Access
-
-
-
-
-
R
R
R
Bit
7
6
5
4
3
2
1
0
Symbol
SOFR[7:0]
Reset [1]
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
[1]
Reset value undefined after a bus reset.
Table 136: DcFrameNumber register: bit description
Bit
Symbol
Description
15 to 11
-
reserved
10 to 0
SOFR[9:0]
frame number
Table 137: Example of DcFrameNumber register access
A0
Phase
Bus lines
Word #
Description
HIGH
command
D[15:8]
-
ignored
D[7:0]
-
command code (B4H)
D[15:0]
0
frame number
LOW
16.3.5
data
DcChipID (R: B5H)
This command reads the chip identification code and hardware version number. The
firmware must check this information to determine the supported functions and
features. This command accesses the DcChipID register, which is shown in
Table 138.
Code (Hex): B5 — read chip ID
Transaction — read 2 bytes (code or data)
Table 138: DcChipID register: bit allocation
Bit
15
14
13
Symbol
12
11
10
9
8
CHIPIDH[7:0]
Reset
0
0
1
1
0
1
1
0
Access
R
R
R
R
R
R
R
R
Bit
7
6
5
4
3
2
1
0
Symbol
CHIPIDL[7:0]
Reset
0
0
1
1
0
0
0
0
Access
R
R
R
R
R
R
R
R
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Single-chip USB OTG controller
Table 139: DcChipID register: bit description
16.3.6
Bit
Symbol
Description
15 to 8
CHIPIDH[7:0]
chip ID code (36H)
7 to 0
CHIPIDL[7:0]
silicon version (30H, with 30 representing the BCD
encoded version number)
DcInterrupt register (R: C0H)
This command indicates the sources of interrupts as stored in the 4-byte DcInterrupt
register. Each individual endpoint has its own interrupt bit. The bit allocation of the
DcInterrupt register is shown in Table 140. Bit BUSTATUS is used to verify the current
bus status in the interrupt service routine. Interrupts are enabled using the
DcInterruptEnable register, see Section 16.1.5.
While reading the DcInterrupt register, it is recommended that both 2-byte words are
read completely.
Code (Hex): C0 — read DcInterrupt register
Transaction — read 4 bytes (code or data)
Table 140: DcInterrupt register: bit allocation
Bit
31
30
29
28
Symbol
27
26
25
24
reserved
Reset
-
-
-
-
-
-
-
-
Access
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
EP14
EP13
EP12
EP11
EP10
EP9
EP8
EP7
Bit
Symbol
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit
15
14
13
12
11
10
9
8
EP6
EP5
EP4
EP3
EP2
EP1
EP0IN
EP0OUT
Symbol
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit
7
6
5
4
3
2
1
0
BUSTATUS
SP_EOT
PSOF
SOF
EOT
SUSPND
RESUME
RESET
Symbol
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Table 141: DcInterrupt register: bit description
Bit
Symbol
Description
31 to 24
-
reserved
23 to 10
EP14 to EP1
Logic 1 indicates the interrupt source(s): endpoint 14 to 1.
9
EP0IN
Logic 1 indicates the interrupt source: control IN endpoint.
8
EP0OUT
Logic 1 indicates the interrupt source: control OUT endpoint.
7
BUSTATUS
Monitors the current USB bus status (0 = awake, 1 = suspend).
6
SP_EOT
Logic 1 indicates that an EOT interrupt has occurred for a short
period.
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Single-chip USB OTG controller
Table 141: DcInterrupt register: bit description…continued
Bit
Symbol
Description
5
PSOF
Logic 1 indicates that an interrupt is issued every 1 ms because
of the Pseudo SOF; after three missed SOFs, the ‘suspend’
state is entered.
4
SOF
Logic 1 indicates that an SOF condition was detected.
3
EOT
Logic 1 indicates that an internal EOT condition was generated
by the DMA Counter reaching zero.
2
SUSPND
Logic 1 indicates that an ‘awake’ to ‘suspend’ change of state
was detected on the USB bus.
1
RESUME
Logic 1 indicates that a ‘resume’ state was detected.
0
RESET
Logic 1 indicates that a bus reset condition was detected.
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17. Limiting values
Table 142: Absolute maximum ratings
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VCC
Conditions
Min
Max
Unit
supply voltage
−0.5
+4.6
V
VI
input voltage
−0.5
+6.0
V
-
100
mA
−2000
+2000
V
−60
+150
°C
Ilu
latch-up current
VI < 0 or VI > VCC
Vesd
electrostatic discharge voltage
ILI < 1 µA
Tstg
storage temperature
[1]
[1]
Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor (Human Body Model).
18. Recommended operating conditions
Table 143: Recommended operating conditions
DP represents OTG_DP1 and H_DP2, and DM represents OTG_DM1 and H_DM2.
Symbol
Parameter
VCC
supply voltage
VI
input voltage on digital I/O lines
Conditions
VI(AI/O)
input voltage on analog I/O lines (pins DP
and DM)
VO(od)
open-drain output pull-up voltage
Tamb
Typ
Max
Unit
3.0
3.3
3.6
V
1.8 V tolerant pins
0
1.8
2.0
V
3.3 V tolerant pins
0
3.3
3.6
V
5 V tolerant pins
0
5.0
5.5
V
0
-
3.6
V
5 V tolerant pins
0
-
5.5
V
non 5 V tolerant pins
0
-
3.6
V
−40
-
+85
°C
ambient temperature
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Philips Semiconductors
Single-chip USB OTG controller
19. Static characteristics
Table 144: Static characteristics: supply pins
VCC = 3.3 V to 3.6 V; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
ICC(HC)
Min
Typ
Max
Unit
operating supply current for the DC suspended
HC
-
33
-
mA
ICC(DC)
operating supply current for the HC suspended
DC
-
20
-
mA
ICC(HC+DC)
operating supply current for the
host and the device
-
50
-
mA
ICC(susp)
suspend supply current
-
60
-
µA
Min
Typ
Max
Unit
[1]
Conditions
HC and DC are
suspended
[1]
Power consumption on the charge pump is not included.
Table 145: Static characteristics: digital pins
VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Input levels
VIL
LOW-level input voltage
-
-
0.8
V
VIH
HIGH-level input voltage
2.0
-
-
V
Schmitt-trigger inputs
Vth(LH)
positive-going threshold voltage
1.4
-
1.9
V
Vth(HL)
negative-going threshold voltage
0.9
-
1.5
V
Vhys
hysteresis voltage
0.4
-
0.7
V
-
-
0.4
V
-
-
0.1
V
Output levels
LOW-level output voltage
VOL
IOL = 4 mA
IOL = 20 µA
VOH
HIGH-level output voltage
IOH = 4 mA
[1]
IOH = 20 µA
2.4
-
-
V
VCC − 0.1
-
-
V
−5
-
+5
µA
-
-
5
pF
−5
-
+5
µA
Leakage current
ILI
input leakage current
CIN
pin capacitance
[2]
pin to GND
Open-drain outputs
OFF-state output current
IOZ
[1]
[2]
Not applicable for open-drain outputs.
These values are applicable to transistor inputs. The value will be different if internal pull-up or pull-down resistors are used.
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ISP1362
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Single-chip USB OTG controller
Table 146: Static characteristics: analog I/O pins (D+, D−)[1]
VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDI
differential input sensitivity
|VI(D+) − VI(D−)|
0.2
-
-
V
VCM
differential common mode
voltage
includes VDI range
0.8
-
2.5
V
VIL
LOW-level input voltage
-
-
0.8
V
VIH
HIGH-level input voltage
2.0
-
-
V
Input levels
Output levels
VOL
LOW-level output voltage
RL = 1.5 kΩ to +3.6 V
-
-
0.3
V
VOH
HIGH-level output voltage
RL = 15 kΩ to GND
2.8
-
3.6
V
−10
-
+10
µA
-
-
10
pF
Leakage current
OFF-state leakage current
ILZ
Capacitance
transceiver capacitance
CIN
pin to GND
Resistance
Rpd(OTG)
pull-down resistance on
enable internal
pins OTG_DP1 and OTG_DM1 resistors
14.25
-
24.8
kΩ
Rpd(H)
pull-down resistance on
pins H_DP2 and H_DM2
enable internal
resistors
10
-
20
kΩ
Rpu(OTG)
pull-up resistance on
OTG_DP1
bus idle
900
-
1575
Ω
bus driven
1425
-
3090
Ω
29
-
44
Ω
10
-
-
MΩ
3.0
-
3.6
V
ZDRV
driver output impedance
ZINP
input impedance
steady-state drive
[2]
Termination
VTERM
[1]
[2]
[3]
[3]
termination voltage for
upstream port pull up (RPU)
DP represents OTG_DP1 and H_DP2, and DM represents OTG_DM1 and H_DM2. D+ is the USB positive data line and D− is the USB
negative data line.
Includes external resistors of 18 Ω ± 10% on H_DP2 and H_DM2, and 27 Ω ± 10% on OTG_DP1 and OTG_DM1.
In the suspend mode, the minimum voltage is 2.7 V.
Table 147: Static characteristics: charge pump
VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = −40 °C to +85 °C; CLOAD = 2 µF; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VBUS
regulated VBUS voltage
ILOAD = 8 mA from
VBUS(OTG); see Figure 29
-
5
5.25
V
ILOAD
maximum load current
external capacitor of 27 nF;
VCC = 3.0 V to 3.6 V
-
-
8
mA
external capacitor of 82 nF;
VCC = 3.0 V to 3.3 V
-
-
14
mA
external capacitor of 82 nF;
VCC = 3.3 V to 3.6 V
-
-
20
mA
1
-
6.5
µF
-
-
0.2
V
CLOAD
output capacitance
VBUS(LEAK)
VBUS(OTG) leakage voltage
VBUS(OTG) not driven
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Single-chip USB OTG controller
Table 147: Static characteristics: charge pump…continued
VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = −40 °C to +85 °C; CLOAD = 2 µF; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ICC(cp)(susp)
suspend supply current for
charge pump
GlobalPowerDown bit of the
HcHardwareConfiguration
register is logic 0
-
-
45
µA
GlobalPowerDown bit of the
HcHardwareConfiguration
register is logic 1
-
-
15
µA
ILOAD = 8 mA
-
-
20
mA
ILOAD = 0 mA
-
-
300
µA
ICC(cp)
operating supply current in
charge pump mode
ATX is idle
Vth(VBUS_VLD)
VBUS valid threshold
4.4
-
-
V
Vth(SESS_END)
VBUS session end threshold
0.2
-
0.8
V
Vhys(SESS_END)
VBUS session end hysteresis
-
150
-
mV
Vth(ASESS_VLD)
VBUS A valid threshold
0.8
-
2
V
Vhys(ASESS_VLD)
VBUS A valid hysteresis
-
200
-
mV
Vth(BSESS_VLD)
VBUS B valid threshold
2
-
4
V
Vhys(BSESS_VLD)
VBUS B valid hysteresis
-
200
-
mV
E
efficiency when loaded
-
75
-
%
IVBUS(leak)
leakage current from VBUS
-
15
-
µA
RVBUS(PU)
VBUS pull-up resistance
pull to VCC when enabled
281
-
-
Ω
RVBUS(PD)
VBUS pull-down resistance
pull to GND when enabled
656
-
-
Ω
RVBUS(IDLE)
VBUS idle impedance for the
A-device
when ID = LOW and
DRV_VBUS = 0
40
-
100
kΩ
RVBUS(ACTIVE)
VBUS active pull-down
impedance
when ID = HIGH and
DRV_VBUS =1
-
350
-
kΩ
ILOAD = 8 mA; VIN = 3 V;
see Figure 28
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ISP1362
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Single-chip USB OTG controller
004aaa211
100
E
efficiency
(%)
80
60
40
VCC = 3.0 V
20
VCC = 3.3 V
VCC = 3.6 V
0
0
5
10
15
20
ILOAD (mA)
25
82 nF charge pump capacitor.
Fig 28. Efficiency versus load current.
004aaa212
5.3
VBUS
(V)
5.2
5.1
5.0
4.9
4.8
VCC = 3.0 V
4.7
VCC = 3.3 V
VCC = 3.6 V
4.6
0
5
10
15
20
ILOAD (mA)
25
82 nF charge pump capacitor.
Fig 29. Output voltage versus load current.
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ISP1362
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Single-chip USB OTG controller
20. Dynamic characteristics
Table 148: Dynamic characteristics
VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
pulse width on input RESET
crystal oscillator running
Min
Typ
Max
Unit
Reset
tW(RESET)
crystal oscillator
stopped
10
-
-
ms
[1]
-
-
-
ms
[2]
-
12
-
MHz
Crystal oscillator
fXTAL
crystal frequency
RS
series resistance
CLOAD
load capacitance
CX1, CX2 = 22 pF
-
-
100
Ω
-
12
-
pF
-
500
ps
External clock input
J
external clock jitter
-
tDUTY
clock duty cycle
45
50
55
%
tCR, tCF
rise time and fall time
-
-
3
ns
[1]
[2]
Dependent on the crystal oscillator start-up time.
Tolerance of the clock frequency is ±50 ppm.
Table 149: Dynamic characteristics: analog I/O lines (D+, D−)[1]
VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = −40 °C to +85 °C; CL = 50 pF; RPU = 1.5 kΩ ± 5 % on DP to VTERM; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Driver characteristics
tFR
rise time
CL = 50 pF;
10% to 90% of
|VOH − VOL|
4
-
20
ns
tFF
fall time
CL = 50 pF;
90% to 10% of
|VOH − VOL|
4
-
20
ns
FRFM
differential rise/fall time
matching (tFR/tFF)
90
-
111.11
%
VCRS
output signal crossover voltage
1.3
-
2.0
V
[1]
[2]
[3]
[2]
[2][3]
DP represents OTG_DP1 and H_DP2, and DM represents OTG_DM1 and H_DM2. Test circuit.
Excluding the first transition from the idle state.
Characterized only, not tested. Limits guaranteed by design.
Table 150: Dynamic characteristics: charge pump
VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = −40 °C to +85 °C; CLOAD = 2 µF; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ILOAD = 8 mA;
CLOAD = 10 µF
-
-
100
ms
1.5
-
3
µs
Driver characteristics
tSTART-UP
rise time to VBUS = 4.4 V
tCOMP_CLK
clock period
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ISP1362
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Single-chip USB OTG controller
Table 150: Dynamic characteristics: charge pump…continued
VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = −40 °C to +85 °C; CLOAD = 2 µF; unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
tVBUS(VALID_dly)
minimum time VBUS(VALID)
error
Conditions
100
-
200
µs
tVBUS(PULSE)
VBUS pulsing time
10
-
30
ms
tVBUS(VALID_dly)
VBUS pull-down time
50
-
-
ms
VRIPPLE
output ripple with constant
load
-
-
50
mV
ILOAD = 8 mA
20.1 Programmed I/O timing
• If you are accessing only the HC, then the HC programmed I/O timing applies.
• If you are accessing only the DC, then the DC programmed I/O timing applies.
• If you are accessing both the HC and the DC, then the DC programmed I/O timing
applies.
20.1.1
HC Programmed I/O timing
Table 151: Dynamic characteristics: HC Programmed interface timing
Symbol
Parameter
Min
Typ
Max
Unit
tAS
address set-up time before CS
Conditions
5
-
-
ns
tAH
address hold time after CS
2
-
-
ns
Read timing
tSHSL_R
first RD/WR after command
(A0 = HIGH)
register access
300
-
-
ns
tSHSL_B
first RD/WR after command
(A0 = HIGH)
buffer access
462
-
-
ns
tSLRL
CS LOW to RD LOW
0
-
-
ns
tRHSH
RD HIGH to CS HIGH
0
-
-
ns
tRL
RD LOW pulse width
33
-
-
ns
tRHRL
RD HIGH to next RD LOW
110
-
-
ns
TRC
RD cycle
143
-
-
ns
tRHDZ
RD data hold time
-
-
3
ns
tRLDV
RD LOW to data valid
-
-
22
ns
tWL
WR LOW pulse width
26
-
-
ns
tWHWL
WR HIGH to next WR LOW
110
-
-
ns
TWC
WR cycle
136
-
-
ns
tSLWL
CS LOW to WR LOW
0
-
-
ns
tWHSH
WR HIGH to CS HIGH
0
-
-
ns
tWDSU
WR data set-up time
3
-
-
ns
tWDH
WR data hold time
4
-
-
ns
Write timing
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ISP1362
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Single-chip USB OTG controller
CS
t SLWL
t SLRL
t SHSL
t RLRH
A0
t WHSH
t RHSH
t RHRL
T RC
RD
t RLDV
t RHDZ
D [15:0]
data
valid
tAS
data
valid
data
valid
data
valid
t WHWL
t
t WL
AH
TWC
WR
t WDH
data
valid
D [15:0]
data
valid
t WDSU
data
valid
data
valid
data
valid
MGT969
Fig 30. HC Programmed interface timing.
20.1.2
DC Programmed I/O timing
Table 152: Dynamic characteristics: DC Programmed interface timing
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Read timing (see Figure 31)
tRHAX
address hold time after RD HIGH
3
-
-
ns
tAVRL
address set-up time before RD LOW
0
-
-
ns
tSHDZ
data outputs high-impedance time after
CS HIGH
-
-
3
ns
tRHSH
chip deselect time after RD HIGH
0
-
-
ns
tRLRH
RD pulse width
25
-
-
ns
tRLDV
data valid time after RD LOW
-
-
22
ns
tSHRL + tRLRH + tRHSH
read cycle time
180
-
-
ns
3
-
-
ns
Write timing (see Figure 32)
tWHAX
address hold time after WR HIGH
tAVWL
address set-up time before WR LOW
tSHWL + tWLWH + tWHSH
write cycle time
tWLWH
0
-
-
ns
180
-
-
ns
WR pulse width
22
-
-
ns
tWHSH
chip deselect time after WR HIGH
0
-
-
ns
tDVWH
data set-up time before WR HIGH
5
-
-
ns
tWHDZ
data hold time after WR HIGH
3
-
-
ns
[1]
[1]
In the command to data phase, the minimum value of the write command to the read data or write data cycle time should be 205 ns.
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t RHAX
A0
tAVRL
t SHDZ
CS/DACK2(2)
t SHRL(1)
t RLRH
RD
t RHSH
t RLDV
D[15:0]
004aaa105
(1) For tSHRL both CS and RD must be deasserted.
(2) Programmable polarity: shown as active LOW.
Fig 31. DC Programmed interface read timing (I/O and 8237 compatible DMA).
t WHAX
A0
tAVWL
CS/DACK2(2)
t WLWH
t SHWL(1)
t WHSH
WR
t DVWH
t WHDZ
D[15:0]
004aaa106
(1) For tSHWL both CS and WR must be deasserted.
(2) Programmable polarity: shown as active LOW.
Fig 32. DC Programmed interface write timing (I/O and 8237 compatible DMA).
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20.2 DMA timing
20.2.1
HC single-cycle DMA timing
Table 153: Dynamic characteristics: HC single-cycle DMA timing
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Read/write timing
tRL
RD pulse width
33
-
-
ns
tRLDV
read process data set-up time
30
-
-
ns
tRHDZ
read process data hold time
0
-
-
ns
tWSU
write process data set-up time
5
-
-
ns
tWHD
write process data hold time
0
-
-
ns
tAHRH
DACK1 HIGH to DREQ1 HIGH
72
-
-
ns
tALRL
DACK1 LOW to DREQ1 LOW
-
-
21
ns
TDC
DREQ1 cycle
[1]
-
-
ns
tSHAH
RD/WR HIGH to DACK1 HIGH
0
-
-
ns
tRHAL
DREQ1 HIGH to DACK1 LOW
0
-
-
ns
tDS
DREQ1 pulse spacing
146
-
-
ns
[1]
tRHAL + tDS +tALRL
T DC
DREQ1
t DS
t ALRL
t SHAH
t RHAL
DACK1
t AHRH
t RLDV
D [15:0]
(read)
D [15:0]
(write)
t RHDZ
data
valid
data
valid
t WSU
RD or WR
t WHD
004aaa107
Fig 33. HC single-cycle DMA timing.
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20.2.2
HC burst mode DMA timing
Table 154: Dynamic characteristics: HC burst mode DMA timing
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Read/write timing (for 4-cycle and 8-cycle burst mode)
tRL
WR/RD LOW pulse width
42
-
-
ns
tRHRL
WR/RD HIGH to next WR/RD LOW
60
-
-
ns
TRC
WR/RD cycle
102
-
-
ns
tSLRL
RD/WR LOW to DREQ1 LOW
22
-
64
ns
tSHAH
RD/WR HIGH to DACK1 HIGH
0
-
-
ns
tRHAL
DREQ1 HIGH to DACK1 LOW
0
-
TDC
DREQ1 cycle
[1]
-
-
ns
tDS(read)
DREQ1 pulse spacing (read)
4-cycle burst mode
105
-
-
ns
8-cycle burst mode
150
-
-
ns
4-cycle burst mode
72
-
-
ns
8-cycle burst mode
167
-
-
ns
tDS(write)
[1]
DREQ1 pulse spacing (write)
ns
tSLAL + (4 or 8)tRC + tDS
t DS
DREQ1
t RHSH
t SLRL
t RHAL
DACK1
t RHRL
t SHAH
RD or WR
004aaa108
T RC
t RLRH
Fig 34. HC burst mode DMA timing.
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20.2.3
DC single-cycle DMA timing (8237 mode)
Table 155: Dynamic characteristics: DC single-cycle DMA timing (8237 mode)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tASRP
DREQ2 off after DACK2 on
-
-
40
ns
Tcy(DREQ2)
cycle time signal DREQ2
180
-
-
ns
T RC
t ASRP
DREQ2
DACK2(1)
004aaa111
(1) Programmable polarity: shown as active LOW.
Fig 35. DC single-cycle DMA timing (8237 mode).
20.2.4
DC single-cycle DMA read timing in DACK-only mode
Table 156: Dynamic characteristics: DC single-cycle DMA read timing in DACK-only mode
Symbol
Parameter
Min
Typ
Max
Unit
tASRP
DREQ off after DACK on
Conditions
-
-
40
ns
tASAP
DACK pulse width
25
-
-
ns
tASAP + tAPRS
DREQ on after DACK off
180
-
-
ns
tASDV
data valid after DACK on
-
-
22
ns
tAPDZ
data hold after DACK off
-
-
3
ns
t ASRP
t APRS
DREQ2
t ASAP
DACK2(1)
t ASDV
t APDZ
DATA
004aaa112
(1) Programmable polarity: shown as active LOW.
Fig 36. DC single-cycle DMA read timing in DACK-only mode.
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20.2.5
DC single-cycle DMA write timing in DACK-only mode
Table 157: Dynamic characteristics: DC single-cycle DMA write timing in DACK-only mode
Symbol
Parameter
tASRP
tASAP
Conditions
Min
Typ
Max
Unit
DREQ2 off after DACK2 on
-
-
40
ns
DACK2 pulse width
25
-
-
ns
tASAP + tAPRS
DREQ2 on after DACK2 off
180
-
-
ns
tASDV
data valid after DACK2 on
-
-
22
ns
tAPDZ
data hold after DACK2 off
-
-
3
ns
t ASAP
t ASRP
t APRS
DREQ2
t ASDV
t APDZ
DACK2(1)
DATA
004aaa113
(1) Programmable polarity: shown as active LOW.
Fig 37. DC single-cycle DMA write timing in DACK-only mode.
20.2.6
DC burst mode DMA timing
Table 158: Dynamic characteristics: DC burst mode DMA timing
Symbol
Parameter
Conditions
tRSIH
input RD/WR HIGH after DREQ on
22
-
-
ns
tILRP
DREQ off after input RD/WR LOW
-
-
-
ns
tIHAP
DACK off after input RD/WR HIGH
0
-
60
ns
tIHIL
DMA burst repeat interval (input
RD/WR HIGH to LOW)
160
-
-
ns
tRL or tWL is 30 ns (min)
Typ
Max
Unit
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Single-chip USB OTG controller
t RSIH
t ILRP
DREQ2
t IHAP
DACK2(1)
t IHIL
RD or WR
004aaa115
(1) Programmable polarity: shown as active LOW.
Fig 38. DC burst mode DMA timing.
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21. Package outline
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
c
y
X
A
48
33
49
32
ZE
e
E HE
A
A2
(A 3)
A1
wM
θ
bp
pin 1 index
64
Lp
L
17
1
detail X
16
ZD
e
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
10.1
9.9
10.1
9.9
0.5
HD
HE
12.15 12.15
11.85 11.85
L
Lp
v
w
y
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
1.45
1.05
1.45
1.05
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT314-2
136E10
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 39. LQFP64 package outline.
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TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls; body 6 x 6 x 0.8 mm
D
SOT543-1
A
B
ball A1
index area
A
A2
E
A1
detail X
C
e1
e
1/2
∅v M
e b
∅w M
y
y1 C
C A B
C
K
J
H
e
G
F
e2
E
1/2
D
e
C
B
A
ball A1
index area
1
2
3
4
5
6
7
8
9 10
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
mm
1.1
0.25
0.15
0.85
0.75
0.35
0.25
6.1
5.9
6.1
5.9
0.5
4.5
4.5
0.15
0.05
0.08
0.1
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT543-1
---
MO-195
---
EUROPEAN
PROJECTION
ISSUE DATE
00-11-22
02-04-09
Fig 40. TFBGA64 package outline.
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22. Soldering
22.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all IC packages. Wave soldering can still
be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In
these situations reflow soldering is recommended. In these situations reflow
soldering is recommended.
22.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 270 °C depending on solder
paste material. The top-surface temperature of the packages should preferably be
kept:
• below 225 °C (SnPb process) or below 245 °C (Pb-free process)
– for all BGA, HTSSON..T and SSOP..T packages
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.
22.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
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• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.
22.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
22.5 Package related soldering information
Table 159: Suitability of surface mount IC packages for wave and reflow soldering
methods
Package[1]
Soldering method
BGA, HTSSON..T[3], LBGA, LFBGA, SQFP,
SSOP..T[3], TFBGA, USON, VFBGA
Reflow[2]
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, not suitable[4]
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
suitable
PLCC[5], SO, SOJ
suitable
suitable
recommended[5][6]
suitable
LQFP, QFP, TQFP
not
SSOP, TSSOP, VSO, VSSOP
not recommended[7]
suitable
CWQCCN..L[8],
not suitable
not suitable
[1]
[2]
PMFP[9],
WQCCN..L[8]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note
(AN01026); order a copy from your Philips Semiconductors sales office.
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
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Product data
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Single-chip USB OTG controller
[3]
[4]
[5]
[6]
[7]
[8]
[9]
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow
oven. The package body peak temperature must be kept as low as possible.
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex
foil by using a hot bar soldering process. The appropriate soldering profile can be provided on
request.
Hot bar soldering or manual soldering is suitable for PMFP packages.
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23. Revision history
Table 160: Revision history
Rev Date
03
20040106
CPCN
Description
-
Product data (9397 750 12337)
Modifications:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Added the OTG logo.
Changed reference to OTG specification from Rev.1.0 to Rev. 1.0a
Table 1 and Figure 3: added type number ISP1362EE/01.
Figure 1: updated.
Figure 3: added index area.
Table 2: updated.
Section 9.7.1: updated.
Section 10: added.
Section 11.4.1: changed 3 ms to 5 ms in list item 2.
Section 11.6: added a remark.
Section 12.2: updated list item 5.
Section 12.3: updated.
Section 12.5.1: updated.
Section 12.8: updated.
Section 13.5.1: updated
Table 23: updated.
Table 33: updated.
Table 72: changed symbol to CHIPID.
Table 76: updated.
Table 143: updated.
Table 145: changed minimum value of VOH to VCC.
Table 146: updated Rpd and Rpu.
Table 147: changed various symbols.
Table 152: changed symbols of read and write cycle time.
Deleted table on timing symbols (old Section 18.1).
02
20030219
-
Product data (9397 750 10767)
01
20021120
-
Preliminary data (9397 750 10087)
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24. Data sheet status
Level
Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
25. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
26. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
27. Trademarks
ARM — is a trademark of ARM Ltd.
DragonBall — is a trademark of Motorola, Inc.
Fujitsu — is a registered trademark of Fujitsu Corp.
GoodLink — is a trademark of Koninklijke Philips Electronics N.V.
Hitachi — is a registered trademark of Hitachi Ltd.
Intel — is a registered trademark of Intel Corp.
Motorola — is a registered trademark of Motorola, Inc.
NEC — is a registered trademark of NEC Corp.
PowerPC — is a trademark of IBM Corp.
SoftConnect — is a trademark of Koninklijke Philips Electronics N.V.
SPARClite — is a registered trademark of Sparc International.
StrongARM — is a trademark of ARM Ltd.
Toshiba — is a registered trademark of Toshiba Corp.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected].
Product data
Fax: +31 40 27 24825
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Contents
1
2
3
3.1
4
5
6
7
7.1
7.2
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
10
11
11.1
11.2
11.3
11.4
11.5
11.6
12
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
13
13.1
13.2
13.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Host/peripheral roles . . . . . . . . . . . . . . . . . . . . . . . . . 3
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional description . . . . . . . . . . . . . . . . . . . . . . . 13
On-The-Go (OTG) controller . . . . . . . . . . . . . . . . . . 13
Advanced Philips Slave Host Controller (PSHC) . . . 13
Philips Device Controller (DC) . . . . . . . . . . . . . . . . . 13
Phase-Locked Loop (PLL) clock multiplier . . . . . . . . 13
USB and OTG transceivers . . . . . . . . . . . . . . . . . . . 13
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . 13
Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC and HC buffer memory. . . . . . . . . . . . . . . . . . . . 13
GoodLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Host and device bus interface . . . . . . . . . . . . . . . . . 14
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . 15
PIO access mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PIO access to internal control registers . . . . . . . . . . 21
PIO access to the buffer memory. . . . . . . . . . . . . . . 24
Setting up a DMA transfer . . . . . . . . . . . . . . . . . . . . 26
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . 30
On-The-Go (OTG) controller . . . . . . . . . . . . . . . . . . . 31
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Dual-role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Session Request Protocol (SRP) . . . . . . . . . . . . . . . 33
Host Negotiation Protocol (HNP) . . . . . . . . . . . . . . . 34
Power saving in the idle state and during wake-up . 38
Current capacity of the OTG charge pump . . . . . . . 38
USB Host Controller (HC) . . . . . . . . . . . . . . . . . . . . . 39
USB states of the HC . . . . . . . . . . . . . . . . . . . . . . . . 39
USB traffic generation . . . . . . . . . . . . . . . . . . . . . . . 40
USB ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Philips Transfer Descriptor (PTD). . . . . . . . . . . . . . . 41
Features of the control and bulk transfer
(aperiodic transfer) . . . . . . . . . . . . . . . . . . . . . . . . . 44
Features of the interrupt transfer . . . . . . . . . . . . . . . 46
Features of the isochronous (ISO) transfer . . . . . . . 46
Overcurrent protection circuit . . . . . . . . . . . . . . . . . . 46
ISP1362 HC Power Management . . . . . . . . . . . . . . 49
USB Device Controller (DC) . . . . . . . . . . . . . . . . . . . 50
DC data transfer operation . . . . . . . . . . . . . . . . . . . . 50
Device DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . 51
Endpoint description . . . . . . . . . . . . . . . . . . . . . . . . 52
© Koninklijke Philips Electronics N.V. 2004.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 06 January 2004
Document order number: 9397 750 12337
13.4
13.5
14
14.1
14.2
14.3
14.4
14.5
14.6
15
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
16
16.1
16.2
16.3
17
18
19
20
20.1
20.2
21
22
22.1
22.2
22.3
22.4
22.5
23
24
25
26
27
DC direct memory access (DMA) transfer . . . . . . . . 54
ISP1362 DC suspend and resume . . . . . . . . . . . . . . 58
OTG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
OtgControl register (R/W: 62H/E2H) . . . . . . . . . . . . 60
OtgStatus register (R: 67H) . . . . . . . . . . . . . . . . . . . 62
OtgInterrupt register (R/W: 68H/E8H). . . . . . . . . . . . 63
OtgInterruptEnable register (R/W: 69H/E9H) . . . . . . 66
OtgTimer register (R/W: 6AH/EAH) . . . . . . . . . . . . . 67
OtgAltTimer register (R/W: 6CH/ECH) . . . . . . . . . . . 68
HC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
HC control and status registers . . . . . . . . . . . . . . . . 71
HC Frame Counter registers. . . . . . . . . . . . . . . . . . . 78
HC Root Hub registers . . . . . . . . . . . . . . . . . . . . . . . 82
HC DMA and interrupt control registers . . . . . . . . . . 92
HC miscellaneous registers . . . . . . . . . . . . . . . . . . . 98
HC buffer RAM control registers . . . . . . . . . . . . . . . . 99
Isochronous (ISO) transfer registers. . . . . . . . . . . . 101
Interrupt transfer registers. . . . . . . . . . . . . . . . . . . . 103
Control and bulk transfer (aperiodic transfer) registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Device Controller (DC) registers . . . . . . . . . . . . . . . 110
Initialization commands . . . . . . . . . . . . . . . . . . . . . 113
Data flow commands . . . . . . . . . . . . . . . . . . . . . . . 119
General commands . . . . . . . . . . . . . . . . . . . . . . . . 123
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Recommended operating conditions . . . . . . . . . . . 129
Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . 130
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . 134
Programmed I/O timing. . . . . . . . . . . . . . . . . . . . . . 135
DMA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Introduction to soldering surface mount packages . 145
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Manual soldering . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Package related soldering information . . . . . . . . . . 146
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149