PHILIPS SAA7111AHZ

INTEGRATED CIRCUITS
DATA SHEET
SAA7111A
Enhanced Video Input Processor
(EVIP)
Product specification
Supersedes data of 1997 May 26
File under Integrated Circuits, IC22
1998 May 15
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
CONTENTS
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
QUICK REFERENCE DATA
5
ORDERING INFORMATION
6
BLOCK DIAGRAM
7
PINNING
8
FUNCTIONAL DESCRIPTION
8.1
8.2
8.2.1
8.2.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.13.1
Analog input processing
Analog control circuits
Clamping
Gain control
Chrominance processing
Luminance processing
RGB matrix
VBI-data bypass
VPO-bus (digital outputs)
Reference signals HREF, VREF and CREF
Synchronization
Clock generation circuit
Power-on reset and CE input
RTCO output
The Line-21 text slicer
Suggestions for I2C-bus interface of the display
software reading line-21 data
9
BOUNDARY-SCAN TEST
9.1
9.2
Initialization of boundary-scan circuit
Device identification codes
10
GAIN CHARTS
11
LIMITING VALUES
12
CHARACTERISTICS
13
TIMING DIAGRAMS
14
CLOCK SYSTEM
14.1
14.2
Clock generation circuit
Power-on control
15
OUTPUT FORMATS
16
APPLICATION INFORMATION
16.1
Layout hints
17
I2C-BUS DESCRIPTION
17.1
17.2
I2C-bus format
I2C-bus detail
1998 May 15
2
SAA7111A
17.2.1
17.2.2
17.2.3
17.2.4
17.2.5
17.2.6
17.2.7
17.2.8
17.2.9
17.2.10
17.2.11
17.2.12
17.2.13
17.2.14
17.2.15
17.2.16
17.2.17
17.2.18
17.2.19
17.2.20
17.2.21
17.2.22
17.2.23
17.2.24
17.2.25
Subaddress 00
Subaddress 02
Subaddress 03
Subaddress 04
Subaddress 05
Subaddress 06
Subaddress 07
Subaddress 08
Subaddress 09
Subaddress 0A
Subaddress 0B
Subaddress 0C
Subaddress 0D
Subaddress 0E
Subaddress 10
Subaddress 11
Subaddress 12
Subaddress 13
Subaddress 15
Subaddress 16
Subaddress 17
Subaddress 1A (read-only register)
Subaddress 1B (read-only register)
Subaddress 1C (read-only register)
Subaddress 1F (read-only register)
18
FILTER CURVES
18.1
18.2
18.3
18.4
Anti-alias filter curve
TUF-block filter curve
Luminance filter curves
Chrominance filter curves
19
I2C-BUS START SET-UP
20
PACKAGE OUTLINES
21
SOLDERING
21.1
21.2
21.3
21.4
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
22
DEFINITIONS
23
LIFE SUPPORT APPLICATIONS
24
PURCHASE OF PHILIPS I2C COMPONENTS
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
1
SAA7111A
FEATURES
• Four analog inputs, internal analog source selectors,
e.g. 4 × CVBS or 2 × Y/C or (1 × Y/C and 2 × CVBS)
• Two analog preprocessing channels
• Fully programmable static gain for the main channels or
automatic gain control for the selected CVBS or Y/C
channel
• Odd/even field identification by a non interlace CVBS
input signal
• Switchable white peak control
• Two built-in analog anti-aliasing filters
• Fix level for RGB output format during horizontal
blanking
• Two 8-bit video CMOS analog-to-digital converters
• 720 active samples per line on the YUV bus
• On-chip clock generator
• One user programmable general purpose switch on an
output pin
• Line-locked system clock frequencies
• Built-in line-21 text slicer
• Digital PLL for horizontal-sync processing and clock
generation
• Requires only one crystal (24.576 MHz) for all standards
• A 27 MHz Vertical Blanking Interval (VBI) data bypass
programmable by I2C-bus for INTERCAST applications
• Horizontal and vertical sync detection
• Power-on control
• Automatic detection of 50 and 60 Hz field frequency,
and automatic switching between PAL and NTSC
standards
• Two via I2C-bus switchable outputs for the digitized
CVBS or Y/C input signals AD1 (7 to 0) and AD2 (7 to 0)
• Chip enable function (reset for the clock generator and
power save mode up from chip version 3)
• Luminance and chrominance signal processing for
PAL BGHI, PAL N, PAL M, NTSC M, NTSC N,
NTSC 4.43, NTSC-Japan and SECAM
• Compatible with memory-based features (line-locked
clock)
• User programmable luminance peaking or aperture
correction
• Boundary scan test circuit complies with the
‘IEEE Std. 1149.1 − 1990’ (ID-Code = 0 F111 02 B)
• Cross-colour reduction for NTSC by chrominance comb
filtering
• I2C-bus controlled (full read-back ability by an external
controller)
• PAL delay line for correcting PAL phase errors
• Real time status information output (RTCO)
• Low power (<0.5 W), low voltage (3.3 V), small package
(LQFP64)
• Brightness Contrast Saturation (BCS) control on-chip
• 5 V tolerant digital I/O ports.
• The YUV (CCIR-601) bus supports a data rate of:
– 864 × fH = 13.5 MHz for 625 line sources
2
– 858 × fH = 13.5 MHz for 525 line sources.
• Desktop/Notebook (PCMCIA) video
APPLICATIONS
• Multimedia
• Data output streams for 16, 12 or 8-bit width with the
following formats:
• Digital television
– YUV 4 : 1 : 1 (12-bit)
• Image processing
– YUV 4 : 2 : 2 (16-bit)
• Video phone
– YUV 4 : 2 : 2 (CCIR-656) (8-bit)
• Intercast.
– RGB (5, 6, and 5) (16-bit) with dither
– RGB (8, 8, and 8) (24-bit) with special application.
1998 May 15
3
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
3
The pure 3.3 V CMOS circuit SAA7111A, analog
front-end and digital video decoder, is a highly integrated
circuit for desktop video applications. The decoder is
based on the principle of line-locked clock decoding and
is able to decode the colour of PAL, SECAM and NTSC
signals into CCIR-601 compatible colour component
values. The SAA7111A accepts as analog inputs CVBS
or S-video (Y/C) from TV or VTR sources. The circuit is
I2C-bus controlled. The SAA7111A then supports several
text features as Line 21 data slicing and a high-speed VBI
data bypass for Intercast.
GENERAL DESCRIPTION
The Enhanced Video Input Processor (EVIP) is a
combination of a two-channel analog preprocessing
circuit including source selection, anti-aliasing filter and
ADC, an automatic clamp and gain control, a Clock
Generation Circuit (CGC), a digital multi-standard
decoder (PAL BGHI, PAL M, PAL N, NTSC M,
NTSC-Japan NTSC N and SECAM), a
brightness/contrast/saturation control circuit, a colour
space matrix (see Fig.1) and a 27 MHz VBI-data bypass.
4
SAA7111A
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDDD
digital supply voltage
3.0
3.3
3.6
V
VDDA
analog supply voltage
3.1
3.3
3.5
V
Tamb
operating ambient temperature
0
25
70
°C
PA+D
analog and digital power
−
0.5
−
W
5
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
SAA7111AHZ
LQFP64
plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm
SOT314-2
SAA7111AH
QFP64
plastic quad flat package; 64 leads (lead length 1.6 mm);
body 14 × 14 × 2.7 mm
SOT393-1
1998 May 15
4
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
6
SAA7111A
BLOCK DIAGRAM
handbook, full pagewidth
VBI DATA BYPASS
UPSAMPLING FILTER
BYPASS
AOUT
14
AI11
AI12
12
AI21
8
AI22
6
ANALOG
PROCESSING
AND
ANALOG-TODIGITAL
CONVERSION
10
AD2
n.c.
VSSS
CHROMINANCE
CIRCUIT
AND
BRIGHTNESS
C/CVBS
CONTRAST
SATURATION
CONTROL
UV
52
Y
31
AD1
FEI
HREF
13
ANALOG
PROCESSING
CONTROL
Y
10
I2C-BUS
CONTROL
53
I2C-BUS
INTERFACE
LUMINANCE
CIRCUIT
61
62
Y/CVBS
63
Y
V
SSA1-2
V
DDA1-2
VPO
(0 : 15)
64
CON
n.c.
34 to 39
42 to 51
YUV-to-RGB
CONVERSION
AND
OUTPUT
FORMATTER
GPSW
IICSA
SDA
SCL
9,5
SAA7111A
11,7
CLOCKS
TDI
TCK
3
TMS
4
58
TRST
TDO
54
TEST
CONTROL
BLOCK
FOR
BOUNDARY
SCAN TEST
AND
SCAN TEST
59
2
57,41,33,25,18
56,40,32,26,19
SYNCHRONIZATION
CIRCUIT
LFCO
30
27
17
29
28
60
55
CLOCK
GENERATION
CIRCUIT
21
POWER-ON
CONTROL
20
23
15
16
22
24
MGG061
V
DDD1-5
VSSD1-5
VS
HS VREF RTS0 RTS1 RTCO
Fig.1 Block diagram.
1998 May 15
5
V
DDA0
V
SSA0
CE
XTAL
XTALI
LLC2
CREF
LLC
RES
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
7
SAA7111A
PINNING
PIN
SYMBOL
I/O/P
DESCRIPTION
(L)QFP64
n.c.
1
−
Do not connect.
TDO
2
O
Test data output for boundary scan test; note 1.
TDI
3
I
Test data input for boundary scan test; note 1.
TMS
4
I
Test mode select input for boundary scan test or scan test; note 1.
VSSA2
5
P
Ground for analog supply voltage channel 2.
AI22
6
I
Analog input 22.
VDDA2
7
P
Positive supply voltage for analog channel 2 (+3.3 V).
AI21
8
I
Analog input 21.
VSSA1
9
P
Ground for analog supply voltage channel 1.
AI12
10
I
Analog input 12.
VDDA1
11
P
Positive supply voltage for analog channel 1 (+3.3 V).
AI11
12
I
Analog input 11.
VSSS
13
P
Substrate ground connection.
AOUT
14
O
Analog test output; for testing the analog input channels.
VDDA0
15
P
Positive supply voltage for internal Clock Generator Circuit (CGC) (+3.3 V).
VSSA0
16
P
Ground for internal CGC.
VREF
17
O
Vertical reference output signal (I2C-bit COMPO = 0) or inverse composite blanking
signal (I2C-bit COMPO = 1) (enabled via I2C-bus bit OEHV).
VDDD5
18
P
Digital supply voltage 5 (+3.3 V).
VSSD5
19
P
Ground for digital supply voltage 5.
LLC
20
O
Line-locked system clock output (27 MHz).
LLC2
21
O
Line-locked clock 1⁄2 output (13.5 MHz).
CREF
22
O
Clock reference output: this is a clock qualifier signal distributed by the internal CGC
for a data rate of LLC2. Using CREF all interfaces on the VPO bus are able to
generate a bus timing with identical phase. If CCIR 656 format is selected
(OFTS0 = 1 and OFTS1 = 1) an inverse composite blanking signal (pixel qualifier) is
provided on this pin.
RES
23
O
Reset output (active LOW); sets the device into a defined state. All data outputs are
in high impedance state. The I2C-bus is reset (waiting for start condition).
CE
24
I
Chip enable; connection to ground forces a reset, up from version 3 power save
function additionally available.
VDDD4
25
P
Digital supply voltage input 4 (+3.3 V).
VSSD4
26
P
Ground for digital supply voltage input 4.
HS
27
O
Horizontal sync output signal (programmable); the positions of the positive and
negative slopes are programmable in 8 LLC increments over a complete line
(equals 64 µs) via I2C-bus bytes HSB and HSS. Fine position adjustment in 2 LLC
increments can be performed via I2C-bus bits HDEL1 and HDEL0.
RTS1
28
O
Two functions output; controlled by I2C-bus bit RTSE1.
RTSE1 = 0: PAL line identifier (LOW = PAL line); indicates the inverted and
non-inverted R − Y component for PAL signals. RTSE1 = 1: H-PLL locked indicator;
a high state indicates that the internal horizontal PLL has locked.
1998 May 15
6
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
PIN
SYMBOL
I/O/P
DESCRIPTION
(L)QFP64
RTS0
29
O
Two functions output; controlled by I2C-bus bit RTSE0.
RTSE0 = 0: odd/even field identification (HIGH = odd field). RTSE0 = 1: vertical
locked indicator; a HIGH state indicates that the internal Vertical Noise Limiter (VNL)
has locked.
VS
30
O
Vertical sync signal (enabled via I2C-bus bit OEHV); this signal indicates the vertical
sync with respect to the YUV output. The HIGH period of this signal is approximately
six lines if the VNL function is active. The positive slope contains the phase
information for a deflection controller.
HREF
31
O
Horizontal reference output signal (enabled via I2C-bus bit OEHV); this signal is used
to indicate data on the digital YUV bus. The positive slope marks the beginning of a
new active line. The HIGH period of HREF is 720 Y samples long. HREF can be used
to synchronize data multiplexer/demultiplexer. HREF is also present during the
vertical blanking interval.
VSSD3
32
P
Ground for digital supply voltage input 3.
VDDD3
VPO
(15 to 10)
VSSD2
33
P
Digital supply voltage 3 (+3.3 V).
34 to 39
O
Digital VPO-bus (Video Port Out) signal; higher bits of the 16-bit VPO-bus or the
16-bit RGB-bus output signal. The output data rate, the format and multiplexing
scheme of the VPO-bus are controlled via I2C-bus bits OFTS0 and OFTS1. If I2C-bus
bit VIPB = 1 the six MSBs of the digitized input signal are connected to these outputs,
configured by the I2C-bus ‘MODE’ bits (see Figs 33 to 40):
LUMA → VPO15 to VPO8, CHROMA → VPO7 to VPO0.
40
P
Ground for digital supply voltage input 2.
VDDD2
41
P
Digital supply voltage 2 (+3.3 V).
VPO
(9 to 0)
42 to 51
O
Digital VPO-bus output signal; lower bits of the 16-bit YUV-bus or the 16-bit RGB-bus
output signal. The output data rate, the format and multiplexing schema of the
VPO-bus are controlled via I2C-bus bits OFTS0 and OFTS1. If I2C-bus bit VIPB = 1
the digitized input signal are connected to these outputs, configured by the I2C-bus
‘MODE’ bits (see Figs 33 to 40): LUMA → VPO15 to VPO8,
CHROMA → VPO7 to VPO0.
FEI
52
I
Fast enable input signal (active LOW); this signal is used to control fast switching on
the digital YUV-bus. A HIGH at this input forces the IC to set its Y and UV outputs to
the high impedance state.
GPSW
53
O
General purpose switch output; the state of this signal is set via I2C-bus control and
the levels are TTL compatible.
XTAL
54
O
Second terminal of crystal oscillator; not connected if external clock signal is used.
XTALI
55
I
Input terminal for 24.576 MHz crystal oscillator or connection of external oscillator
with CMOS compatible square wave clock signal.
VSSD1
56
P
Ground for digital supply voltage input 1.
VDDD1
57
P
Digital supply voltage input 1 (+3.3 V).
TRST
58
I
Test reset input not (active LOW), for boundary scan test; notes 1, 2 and 3.
TCK
59
I
Test clock for boundary scan test; note 1.
RTCO
60
O
Real time control output: contains information about actual system clock frequency,
subcarrier frequency and phase and PAL sequence.
1998 May 15
7
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
PIN
SYMBOL
I/O/P
DESCRIPTION
(L)QFP64
I2C-bus slave address select;
0 = 48H for write, 49H for read
1 = 4AH for write, 4BH for read.
IICSA
61
I
SDA
62
I/O
Serial data input/output (I2C-bus).
SCL
63
I/O
Serial clock input/output (I2C-bus).
n.c.
64
−
Not connect.
Notes
1. In accordance with the ‘IEEE1149.1’ standard the pads TCK, TDI, TMS and TRST are input pads with an internal
pull-up transistor and TDO a 3-state output pad.
2. This pin provides easy initialization of BST circuit. TRST can be used to force the TAP (Test Access Port) controller
to the Test-Logic-Reset state (normal operation) at once.
3. For board design without boundary scan implementation (pin compatibility with the SAA7110) connect the TRST pin
to ground.
1998 May 15
8
Philips Semiconductors
Product specification
n.c.
SCL
SDA
IICSA
RTCO
TCK
TRST
VDDD1
VSSD1
XTALI
XTAL
GPSW
FEI
VPO0
VPO1
VPO2
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SAA7111A
64
Enhanced Video Input Processor (EVIP)
handbook, full pagewidth
n.c.
1
48 VPO3
TDO
2
47 VPO4
TDI
3
46 VPO5
TMS
4
45 VPO6
VSSA2
5
44 VPO7
AI22
6
43 VPO8
VDDA2
7
42 VPO9
AI21
8
VSSA1
41 VDDD2
SAA7111A
Fig.2 Pin configuration (LQFP64/QFP64).
1998 May 15
9
VSSD3 32
HREF 31
33 VDDD3
VS 30
34 VPO15
VSSA0 16
RTS0 29
VDDA0 15
RTS1 28
35 VPO14
HS 27
AOUT 14
VSSD4 26
36 VPO13
VDDD4 25
VSSS 13
CE 24
37 VPO12
RES 23
AI11 12
CREF 22
38 VPO11
LLC2 21
VDDA1 11
LLC 20
39 VPO10
VSSD5 19
AI12 10
VDDD5 18
40 VSSD2
VREF 17
9
MGG060
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
8
The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range.
The AGC active time is the sync bottom of the video signal.
FUNCTIONAL DESCRIPTION
8.1
Analog input processing
The SAA7111A offers four analog signal inputs, two
analog main channels with source switch, clamp circuit,
analog amplifier, anti-alias filter and video CMOS ADC
(see Fig.5).
8.2
Analog control circuits
handbook, halfpage
The anti-alias filters are adapted to the line-locked clock
frequency via a filter control circuit. During the vertical
blanking time, gain and clamping control are frozen.
8.2.1
0 dB
(1 V(p-p) 27/47 Ω)
−7.5 dB
The clamp control circuit controls the correct clamping of
the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. An internal
digital clamp comparator generates the information with
respect to clamp-up or clamp-down. The clamping levels
for the two ADC channels are fixed for luminance (60) and
chrominance (128). Clamping time in normal use is set
with the HCL pulse at the back porch of the video signal.
8.3
CLAMP
HCL
MGL065
minimum
Chrominance processing
• AGC (Automatic Gain Control for chrominance
PAL and NTSC)
Analog line with clamp (HCL) and gain
range (HSY).
• Chrominance amplitude matching (different gain factors
for R − Y and B − Y to achieve CCIR-601 levels
Cr and Cb for all standards)
GAIN CONTROL
• Chrominance saturation control
Signal (white) peak control limits the gain at signal
overshoots. The flow charts (see Figs 13 and 14) show
more details of the AGC. The influence of supply voltage
variation within the specified range is automatically
eliminated by clamp and automatic gain control.
• Luminance contrast and brightness
• Limiting YUV to the values 1 (min.) and 254 (max.) to
fulfil CCIR-601 requirements.
The gain control circuit receives (via the I2C-bus) the static
gain levels for the two analog amplifiers or controls one of
these amplifiers automatically via a built-in automatic gain
control (AGC) as part of the Analog Input Control (AICO).
1998 May 15
0 dB
The colour difference signals are fed to the
Brightness/Contrast/Saturation block (BCS), which
includes the following five functions:
1
8.2.2
range tbf
The 8-bit chrominance signal is fed to the multiplication
inputs of a quadrature demodulator, where two subcarrier
signals from the local oscillator DTO1 are applied
(0 and 90° phase relationship to the demodulator axis).
The frequency is dependent on the present colour
standard. The output signals of the multipliers are
low-pass filtered (four programmable characteristics) to
achieve the desired bandwidth for the colour difference
signals (PAL and NTSC) or the 0 and 90° FM-signals
(SECAM).
60
HSY
maximum
Fig.4 Automatic gain range.
TV line
analog line blanking
GAIN
controlled
ADC input level
MGG063
255
Fig.3
analog input level
+4.5 dB
CLAMPING
handbook, halfpage
SAA7111A
10
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
The SECAM-processing contains the following blocks:
SAA7111A
The high frequency components of the luminance signal
can be peaked (control for sharpness improvement via
I2C-bus) in two band-pass filters with selectable transfer
characteristic. This signal is then added to the original
(unpeaked) signal. A switchable amplifier achieves
common DC amplification, because the DC gains are
different in both chrominance trap modes. The improved
luminance signal is fed to the BCS control located in the
chrominance processing block (see Fig.7).
• Baseband ‘bell’ filters to reconstruct the amplitude and
phase equalized 0 and 90° FM-signals
• Phase demodulator and differentiator
(FM-demodulation)
• De-emphasis filter to compensate the pre-emphasised
input signal, including frequency offset compensation
(DB or DR white carrier values are subtracted from the
signal, controlled by the SECAM-switch signal).
8.5
The burst processing block provides the feedback loop of
the chroma PLL and contains;
RGB matrix
Y, Cr and Cb data are converted after interpolation into
RGB data in accordance with CCIR-601
recommendations. The realized matrix equations consider
the digital quantization:
• Burst gate accumulator
• Colour identification and killer
• Comparison nominal/actual burst amplitude (PAL/NTSC
standards only)
R = Y + 1.371 Cr
G = Y − 0.336 Cb − 0.698 Cr
• Loop filter chrominance gain control (PAL/NTSC
standards only)
B = Y + 1.732 Cb.
• Loop filter chrominance PLL (only active for PAL/NTSC
standards)
After dithering (noise shaping) the RGB data is fed to the
output interface within the VPO-bus output formatter.
• PAL/SECAM sequence detection, H/2-switch
generation
8.6
• Increment generation for DTO1 with divider to generate
stable subcarrier for non-standard signals.
For a 27 MHz VBI-data bypass the offset binary CVBS
signal is upsampled behind the ADCs. Upsampling of the
CVBS signal from 13.5 to 27 MHz is possible, because the
ADCs deliver high performance at 13.5 MHz sample clock.
Suppressing of the back folded CVBS frequency
components after upsampling is achieved by an
interpolation filter (see Fig.42).
The chrominance comb filter block eliminates crosstalk
between the chrominance channels in accordance with the
PAL standard requirements. For NTSC colour standards
the chrominance comb filter can be used to eliminate
crosstalk from luminance to chrominance (cross-colour)
for vertical structures. The comb filter can be switched off
if desired. The embedded line delay is also used for
SECAM recombination (cross-over switches).
The TUF block on the digital top level performs the
upsampling and interpolation for the bypassed CVBS
signal (see Fig.6).
For bypass details see Figs 8 to 10.
The resulting signals are fed to the variable Y-delay
compensation, RGB matrix, dithering circuit and output
interface, which contains the VPO output formatter and the
output control logic (see Fig.6).
8.4
8.7
VPO-bus (digital outputs)
The 16-bit VPO-bus transfers digital data from the output
interfaces to a feature box or a field memory, a digital
colour space converter (SAA7192 DCSC), a video
enhancement and digital-to-analog processor
(SAA7165 VEDA2) or a colour graphics board
(Targa-format) as a graphical user interface.
Luminance processing
The 8-bit luminance signal, a digital CVBS format or a
luminance format (S-VHS, HI8), is fed through a
switchable prefilter. High frequency components are
emphasized to compensate for loss. The following
chrominance trap filter (f0 = 4.43 or 3.58 MHz centre
frequency selectable) eliminates most of the colour carrier
signal, therefore, it must be bypassed for S-video
(S-VHS and HI8) signals.
1998 May 15
VBI-data bypass
11
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
• VREF: The VREF output delivers a vertical reference
signal or an inverse composite blank signal controlled
via the I2C-bus [subaddress 11, inverse composite
blank (COMPO)]. Furthermore four different modes of
vertical reference signals are selectable via the I2C-bus
[subaddress 13, vertical reference output control
(VCTR1 and VCTR0)]. The description of VREF timing
and position is illustrated in Figs 15, 16, 24 and 25.
The output data formats are controlled via the I2C-bus bits
OFTS0, OFTS1 and RGB888. Timing for the data stream
formats, YUV (4 : 1 : 1) (12-bit), YUV (4 : 2 : 2) (16-bit),
RGB (5, 6 and 5) (16-bit) and RGB (8, 8 and 8) (24-bit)
with an LLC2 data rate, is achieved by marking each
second positive rising edge of the clock LLC in conjunction
with CREF (clock reference) (except RGB (8, 8 and 8),
see special application in Fig.32). The higher output
signals VPO15 to VPO8 in the YUV format perform the
digital luminance signal. The lower output signals
VPO7 to VPO0 in the YUV format are the bits of the
multiplexed colour difference signals (B − Y) and (R − Y).
The arrangement of the RGB (5, 6 and 5) and
RGB (8, 8 and 8) data stream bits on the VPO-bus is given
in Table 6.
• CREF: The CREF output delivers a clock/pixel qualifier
signal for external interfaces to synchronize to the
VPO-bus data stream.
Four different modes for the clock qualifier signal are
selectable via the I2C-bus [subaddress 13, clock
reference output control (CCTR1 and CCTR0)].
The description of CREF timing and position is
illustrated in Figs 16, 18, 20 and 21.
The data stream format YUV 4 : 2 : 2 (the 8 higher output
signals VPO15 to VPO8) in LLC data rate fulfils the
CCIR-656 standard with its own timing reference code at
the start and end of each video data block.
8.9
Fast enable is achieved by setting input FEI to LOW.
The signal is used to control fast switching on the digital
VPO-bus. HIGH on this pin forces the VPO outputs to a
high-impedance state (see Figs 18 and 19). The I2C-bus
bit OEYC has to be set HIGH to use this function.
The digitized PAL, SECAM or NTSC signals AD1 (7 to 0)
and AD2 (7 to 0) are connected directly to the VPO-bus
via I2C-bus bit VIPB = 1 and MODE = 4, 5, 6 or 7.
AD1 (7 to 0) → VPO (15 to 8) and
AD2 (7 to 0) → VPO (7 to 0).
The selection of the analog input channels is controlled via
I2C-bus subaddress 02 MODE select.
8.10
Clock generation circuit
The internal CGC generates all clock signals required for
the video input processor. The internal signal LFCO is a
digital-to-analog converted signal provided by the
horizontal PLL. It is the multiple of the line frequency
429
6.75MHz = ---------- × f H
432
The upsampled 8-bit offset binary CVBS signal (VBI-data
bypass) is multiplexed under control of the I2C-bus to the
digital VPO-bus (see Fig.8).
Reference signals HREF, VREF and CREF
• HREF: The positive slope of the HREF output signal
indicates the beginning of a new active video line.
The high period is 720 luminance samples long and is
also present during the vertical blanking.
The description of timing and position from HREF is
illustrated in Figs 15, 16, 21 and 23.
1998 May 15
Synchronization
The prefiltered luminance signal is fed to the
synchronization stage. Its bandwidth is reduced to 1 MHz
in a low-pass filter. The sync pulses are sliced and fed to
the phase detectors where they are compared with the
sub-divided clock frequency. The resulting output signal is
applied to the loop filter to accumulate all phase
deviations. Internal signals (e. g. HCL and HSY) are
generated in accordance with analog front-end
requirements. The output signals HS, VS, and PLIN are
locked to the timing reference, guaranteed between the
input signal and the HREF signal, as further improvements
to the circuit may change the total processing delay. It is
therefore not recommended to use them for applications
which require absolute timing accuracy on the input
signals. The loop filter signal drives an oscillator to
generate the line frequency control signal LFCO
(see Fig.7).
A pixel in the format tables is the time required to transfer
a full set of samples. If 16-bit 4 : 2 : 2 format is selected
two luminance samples are transmitted in comparison to
one (B − Y) and one (R − Y) sample within a pixel.
The time frames are controlled by the HREF signal.
8.8
SAA7111A
Internally the LFCO signal is multiplied by a factor of 2 or 4
in the PLL circuit (including phase detector, loop filtering,
VCO and frequency divider) to obtain the LLC and LLC2
output clock signals. The rectangular output clocks have
a 50% duty factor (see Fig.26).
12
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
8.11
Power-on reset and CE input
8.13.1
A missing clock, insufficient digital or analog VDDA0 supply
voltages (below 2.7 V) will initiate the reset sequence; all
outputs are forced to 3-state. The indicator output RES is
LOW for approximately 128LLC after the internal reset and
can be applied to reset other circuits of the digital TV
system.
1. Synchronous reading once per frame (or once per
field); It can use either the rising edge (Line-21 Field 1)
or both edges (Line-21 Field 1 or 2) of the ODD signal
(pin RTSO) to initiate an I2C-bus read transfer of the
three registers 1A, 1B and 1C.
2. Asynchronous reading; It can poll either the F1RDY bit
(Line-21 Field 1) or both F1RDY/F2RDY bits (Line-21
Field 1 or 2). After valid data has been read the
corresponding F*RDY bit is set to LOW until new data
has arrived. The polling frequency has to be slightly
higher than the frame or field frequency, respectively.
RTCO output
The real time control and status output signal contains
serial information about the actual system clock
(increment of the HPLL), subcarrier frequency [increment
and phase (via reset) of the FSC-PLL] and PAL sequence
bit. The signal can be used for various applications in
external circuits, e.g. in a digital encoder to achieve clean
encoding (see Fig.20).
8.13
The Line-21 text slicer
The text slicer block detects and acquires Line-21 Closed
Captioning data from a 525-line CVBS signal. Extended
data services on Line-21 Field 2 are also supported.
If valid data is detected the two data bytes are stored in two
I2C-bus registers. A parity check is also performed and the
result is stored in the MSB of the corresponding byte.
A third I2C-bus register is provided for data valid and data
ready flags. The two bits F1VAL and F2VAL indicate that
the input signal carries valid Closed Captioning data in the
corresponding fields. The data ready bits F1RDY and
F2RDY have to be evaluated if asynchronous I2C-bus
reading is used.
1998 May 15
SUGGESTIONS FOR I2C-BUS INTERFACE OF THE
DISPLAY SOFTWARE READING LINE-21 DATA
There are two methods by which the software can acquire
the data:
It is possible to force a reset by pulling the chip enable
(CE) to ground. After the rising edge of CE and sufficient
power supply voltage, the outputs LLC, LLC2, CREF,
RTCO, RTS0, RTS1, GPSW and SDA return from 3-state
to active, while HREF, VREF, HS and VS remain in 3-state
and have to be activated via I2C-bus programming
(see Table 5).
8.12
SAA7111A
13
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AI22
AI21
VDDA1
VDDA2
AI12
AI11
5
AOSL (1 : 0)
6
8
SOURCE
SWITCH
CLAMP
CIRCUIT
ANALOG
AMPLIFIER
DAC9
ANTI-ALIAS
FILTER
BYPASS
SWITCH
ADC2
11
FUSE (1 : 0)
7
10
12
CLAMP
CIRCUIT
SOURCE
SWITCH
ANALOG
AMPLIFIER
DAC9
ANTI-ALIAS
FILTER
BYPASS
SWITCH
ADC1
14
FUSE (1 : 0)
MODE
CONTROL
HCL
GLIMB HSY
GLIMT
WIPA
SLTCA
ANALOG
CONTROL
VSSS
GAIN
CONTROL
13
ANTI-ALIAS
CONTROL
CROSS
CHR
8
8
MULTIPLEXER
Fig.5 Analog input processing.
AD2BYP AD1BYP
Product specification
LUM
VBLNK
SVREF
SAA7111A
MGC655
VERTICAL
BLANKING
CONTROL
VBSL
HOLDG
GAFIX
WPOFF
GUDL0-GUDL2
GAI20-GAI28
GAI10-GAI18
HLNRS
UPTCV
handbook, full pagewidth
MODE 0
MODE 1
MODE 2
CLAMP
CONTROL
AOUT
Philips Semiconductors
VSSA1
VSSA2
9
14
Enhanced Video Input Processor (EVIP)
1998 May 15
n.c.
TEST
SELECTOR
AND
BUFFER
64
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AD1BYP
SECAM
PROCESSING
1
sequential
UV signals
TRST
TCK
TDI
TMS
TDO
VDDD1-5
RES
58
59
3
4
QUADRATURE
DEMODULATOR
TEST
CONTROL
BLOCK
LOW-PASS
CHBW0
CHBW1
2
SUBCARRIER
GENERATION
57,41,33,
25,18
23
POWER-ON
CONTROL
HUEC
PHASE
DEMODULATOR
SUBCARRIER
INCREMENT
GENERATION
AND
DIVIDER
AMPLITUDE
DETECTOR
BURST GATE
ACCUMULATOR
LOOP FILTER
LEVEL
ADJUSTMENT,
BRIGHTNESS,
CONTRAST,
AND
SATURATION
CONTROL
GAIN
CONTROL
AND Y-DELAY
COMPENSATION
15
CE CLOCKS
CSTD 1
CSTD 0
INCS
V
SSD1-5
FCTC
CODE
BRIG
CONT
SATN
52
Y
RGB MATRIX
interpolation
dithering
DIT
UV
COMB
FILTERS
SECAM
RECOMBINATION
fH/2 switch signal
VBI DATA BYPASS
TUF
OUTPUT
FORMATTER
AND
INTERFACE
42 to 51
34 to 39
CBR
DCCF
56,40,32,26,19
RGB
31
GPSW
OFTS0
RTSE1
OFTS1
RGB888 RTSE0
VIPB
OEYC
VLOF
OEHV
COLO
FECO
COMPO
VRLN
VSTA (8 : 0)
VSTO (8 : 0)
60
FEI
VPO
(9 : 0)
VPO
(15 : 10)
HREF
Philips Semiconductors
n.c.
AD2BYP
CHR
Enhanced Video Input Processor (EVIP)
gewidth
1998 May 15
LUM
RTCO
MGG062
LUM
Y
Product specification
SAA7111A
Fig.6 Chrominance circuit.
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PREF
WEIGHTING
AND
ADDING
STAGE
VARIABLE
BAND-PASS
FILTER
CHROMINANCE
TRAP
PREFILTER
BYPS
VBLB
BPSS0
BPSS1
PREF
APER0
APER1
VBLB
MATCHING
AMPLIFIER
PREFILTER
SYNC
CLOCK CIRCUIT
CLOCKS
VBLB
LINE 21
TEXT
SLICER
SYNC SLICER
16
BYTE1
BYTE2
STATUS
SYNCHRONIZATION CIRCUIT
2
I C BUS CONTROL
53
2
I C-BUS
INTERFACE
61
63
FIDT
VERTICAL
PROCESSOR
62
30
29
17
AUFD
HSB
HSS
FSEL
VTRC
PHASE
DETECTOR
COARSE
DAC6
HLCK
STTC
VTRC
LOOP FILTER
2
COUNTER
27
HPLL
VTRC
EXFIL
22
20
21
CREF
LLC
LLC2
CLOCK
GENERATION
CIRCUIT
15
16
24
VDDA0
VSSA0
CE
INCS
DISCRETE
TIME
OSCILLATOR 2
CRYSTAL
CLOCK
GENERATOR
55
54
XTALI
XTAL
28
MGC654
IICSA SCL SDA
VS RTS0 VREF
HS
RTS1
Product specification
Fig.7 Luminance and sync processing.
SAA7111A
handbook, full pagewidth
GPSW
VNOI0
VNOI1
VTRC
PHASE
DETECTOR
FINE
LINE-LOCKED
CLOCK
GENERATOR
Philips Semiconductors
LUMINANCE CIRCUIT
Enhanced Video Input Processor (EVIP)
1998 May 15
Y
LUM
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
handbook, full pagewidth
TBP7 to 0
(CVBS)
0
Y or YUV
0
AD1BYP
MUX
CVBS
UP
1
(LUMA see Fig. 37)
MUX
BYP
UP
VPO15 to 8
REGISTER
1
SWHI
VBP0
VBP4
BCHI1 to 0
I2C-bus
BCHI1
BCHI0
SWHI
0
0
1
0
1
0
1
0
VBP0
1
1
VBP4
0
UV or YUV
0
AD2BYP
MUX
CVBS
UP
1
VIPB
I2C-bus
(CHROMA see Fig. 37)
MUX
BYP
UP
VPO7 to 0
REGISTER
1
SWLO
VBP0
VBP4
BCLO1 to 0
I2C-bus
BCLO1
BCLO0
SWLO
0
0
1
0
1
0
1
0
VBP0
1
1
VBP4
REG
4 × REG
VBP4
V_GATE
(programmable)
EN
HREFINT
CLOCK 0
CLOCK 0
VBP0
MGG064
HREFINT = internal horizontal reference.
TBP = upsampled CVBS input data (27 MHz).
AD1BYP/AD2BYP = digitized CVBS input data and Y/C input data (13.5 MHz).
VBP0 = programmable vertical reference signal.
VBP4 = delayed programmable vertical reference signal (4LLC clocks delay).
Fig.8 Multiplexing of the CVBS signal to the VPO-bus.
1998 May 15
17
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
handbook, full pagewidth
SAA7111A
REG
VREF CCIR 656
EN
CLOCK 0
HREFINT
VBP0
VBP4
REG
VREFINT
V V
C C
T T
R R
1 0
VREFOUT
REG
0
0
VREFINT
0
1
VREF CCIR 656
1
0
VBP0
1
1
VBP4
HREF
CLK0
0
EN
REG
HREFINT
CLOCK 0
VREF
MUX
VCTR1 to 0
1
CLOCK 0
COMPO
VREF_CCIR 656 = vertical reference signal referring to the field interval definitions of CCIR656.
HREFINT = internal horizontal reference signal.
VREFINT = internal vertical reference signal.
VBP0 = programmable vertical reference signal.
VBP4 = delayed programmable vertical reference signal (4LLC clocks delay).
Fig.9 VREF output signal generation.
handbook, full pagewidth
CREFINT
selected
VREF
CCTR1 to 0
C C
C C
T T
R R
1 0
CREFOUT
REG
0
0
CREFINT
0
1
0 if VREF = 0
1
0
1 if VREF = 0
1
1
1 (always HIGH)
CREF
CLOCK 0
MGG066
CREFINT = internal clock qualifier signal.
Fig.10 CREF output signal generation.
1998 May 15
18
MGG065
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
9
BOUNDARY-SCAN TEST
9.2
Device identification codes
A Device Identification Register (DIR) is specified in ‘IEEE
Std. 1149.1-1990 - IEEE Standard Test Access Port and
Boundary-Scan Architecture’ (IEEE Std. 1149.1b-1994).
It is a 32-bit register which contains fields for the
specification of the IC manufacturer, the IC part number
and the IC version number. Its biggest advantage is the
possibility to check for the correct ICs mounted after
production and determination of the version number of
ICs during field service.
The SAA7111A has built in logic and 5 dedicated pins to
support boundary-scan testing which allows board testing
without special hardware (nails). The SAA7111A follows
the ‘IEEE Std. 1149.1 - Standard Test Access Port and
Boundary-Scan Architecture’ set by the Joint Test Action
Group (JTAG) chaired by Philips.
The 5 special pins are Test Mode Select (TMS), Test
Clock (TCK), Test Reset (TRST), Test Data Input (TDI)
and Test Data Output (TDO).
When the IDCODE instruction is loaded into the BST
instruction register, the identification register will be
connected between TDI and TDO of the IC.
The identification register will load a component specific
code during the CAPTURE_DATA_REGISTER state of
the TAP controller and this code can subsequently be
shifted out. At board level this code can be used to verify
component manufacturer, type and version number.
The device identification register contains 32-bits,
numbered 31 to 0, where bit 31 is the Most Significant Bit
(MSB) (nearest to TDI) and bit 0 is the Least Significant
Bit (LSB) (nearest to TDO); see Fig.11.
The BST functions BYPASS, EXTEST, INTEST,
SAMPLE, CLAMP and IDCODE are all supported
(see Table 1). Details about the JTAG BST-TEST can be
found in the specification “EEE Std. 1149.1”. A file
containing the detailed Boundary-Scan Description
Language (BSDL) description of the SAA7111A is
available on request.
9.1
SAA7111A
Initialization of boundary-scan circuit
The Test Access Port (TAP) controller of an IC should be
in the reset state (TEST_LOGIC_RESET) when the IC is
in functional mode. This reset state also forces the
instruction register into a functional instruction such as
IDCODE or BYPASS.
To solve the power-up reset, the standard specifies that
the TAP controller will be forced asynchronously to the
TEST_LOGIC_RESET state by setting the TRST pin
LOW.
Table 1
BST instructions supported by the SAA7111A
INSTRUCTION
DESCRIPTION
BYPASS
This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO
when no test operation of the component is required.
EXTEST
This mandatory instruction allows testing of off-chip circuitry and board level interconnections.
SAMPLE
This mandatory instruction can be used to take a sample of the inputs during normal operation of
the component. It can also be used to preload data values into the latched outputs of the
boundary-scan register.
CLAMP
This optional instruction is useful for testing when not all ICs have BST. This instruction addresses
the bypass register while the boundary-scan register is in external test mode.
IDCODE
This optional instruction will provide information on the components manufacturer, part number and
version number.
INTEST
This optional instruction allows testing of the internal logic (no support for customers available).
USER1
This private instruction allows testing by the manufacturer (no support for customers available).
1998 May 15
19
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
MSB
handbook, full pagewidth
31
TDI
LSB
28 27
12 11
1
0010
1111000100010001
00000010101
4-bit
version
code
16-bit part number
11-bit manufacturer
indentification
Fig.11 32 bits of identification code.
1998 May 15
20
0
1
TDO
MGL111
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
10 GAIN CHARTS
MGC648
handbook, halfpage
factor dB = 20 x log 10 gain =
dB
5.5
(
512
768 − i
(
7.5
3.5
i > 256
bit [8] = 1
1.5
bit [8] = 0
i < 256
−0.5
factor dB = 20 x log 10 gain =
(
257 + i
512
(
−2.5
−4.5
0
256
512
gain value (i)
Fig.12 Amplifier curve.
handbook, full pagewidth
ANALOG INPUT
ADC
1
NO BLANKING ACTIVE
VBLK
0
<- CLAMP
1
1
+ CLAMP
CLL
HCL
0
1
0
0
− CLAMP
GAIN ->
NO CLAMP
+ GAIN
SBOT
HSY
1
− GAIN
0
1
fast − GAIN
WIPE
0
slow + GAIN
MGC647
WIPE = white peak level (254); SBOT = sync bottom level (1); CLL = clamp level [60 Y (128 C)];
HSY = horizontal sync pulse; HCL = horizontal clamp pulse.
Fig.13 Clamp and gain flow.
1998 May 15
21
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
handbook, full pagewidth
SAA7111A
ANALOG INPUT
gain
AMPLIFIER
9
DAC
ANTI-ALIAS FILTER
ADC
8
1
NO ACTION
VBLK
1
LUMA/CHROMA DECODER
0
HOLDG
0
1
0
X
1
0
0
<4
>254
1
1
1
1
0
<1
+1/F
STOP
>248
>254
0
X=1
X=0
1
0
HSY
0
+1/L
−1/LLC2
+1/LLC2
+/− 0
−1/LLC2
GAIN ACCUMULATOR (18 BITS)
ACTUAL GAIN VALUE 9-BIT (AGV) [−6/+6 dB]
1
0
X
1
0
HSY
1
AGV
Y
UPDATE
0
FGV
GAIN VALUE 9-BIT
MGC652
X = system variable; Y = IAGV − FGVI > GUDL; VBLK = vertical blanking pulse;
HSY = horizontal sync pulse; AGV = actual gain value; FGV = frozen gain value.
Fig.14 Gain flow chart.
1998 May 15
22
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
11 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); all ground pins connected together and all supply
pins connected together.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDDD
digital supply voltage
−0.5
+4.6
V
VDDA
analog supply voltage
−0.5
+4.6
V
Vi(A)
input voltage at analog inputs
−0.5
VDDA + 0.5
(4.6 max.)
V
Vo(A)
output voltage at analog output
−0.5
VDDA + 0.5
V
Vi(D)
input voltage at digital inputs and outputs
outputs in 3-state
−0.5
+5.5
V
Vo(D)
output voltage at digital outputs
outputs active
−0.5
VDDD + 0.5
V
∆VSS
voltage difference between VSSAall and VSSall
−
100
mV
Tstg
storage temperature
−65
+150
°C
Tamb
operating ambient temperature
0
70
°C
Tamb(bias)
operating ambient temperature under bias
−10
+80
°C
Vesd
electrostatic discharge all pins
−2000
+2000
V
note 1
Note
1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.
12 CHARACTERISTICS
VDDD = 3.0 to 3.6 V; VDDA = 3.1 to 3.5 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDD
digital supply voltage
3.0
3.3
3.6
V
IDDD
digital supply current
−
63
70
mA
PD
digital power
−
0.21
−
W
VDDA
analog supply voltage
3.1
3.3
3.5
V
IDDA
analog supply current
−
52
−
mA
PA
analog power
−
0.17
−
W
PA+D
analog and digital power
−
0.38
−
W
Ppd
analog and digital power in CE connected to ground
power-down mode
(since version 3)
−
0.02
−
W
Iclamp
clamping current
VI = 0.9 V DC
−
±3.5
−
µA
Vi(p-p)
input voltage
(peak-to-peak value)
for normal video levels
0.3
[1 V (p-p)]; −3 dB
termination 27/47 Ω and
AC coupling required;
coupling capacitor = 22 nF
0.7
1.2
V
|Zi|
input impedance
clamping current off
200
−
−
kΩ
Ci
input capacitance
−
−
10
pF
AOSL = [1:0] = 00b;
AOUT not connected
Analog part
1998 May 15
23
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SYMBOL
αcs
PARAMETER
channel crosstalk
SAA7111A
CONDITIONS
MIN.
TYP.
MAX.
UNIT
fi = 5 MHz
−
−
−50
dB
at −3 dB
−
7
−
MHz
Analog-to-digital converters
B
bandwidth
φdiff
differential phase
(amplifier plus anti-alias
filter = bypass)
−
2
−
deg
Gdiff
differential gain
(amplifier plus anti-alias
filter = bypass)
−
2
−
%
fclkADC
ADC clock frequency
12.8
−
14.3
MHz
DLE
DC differential linearity
error
−
0.7
−
LSB
ILE
DC integral linearity error
−
1
−
LSB
VIL(SCL,SDA)
LOW level input voltage
pins SDA and SCL
−0.5
−
+0.3VDDD
V
VIH
HIGH level input voltage
pins SDA and SCL
0.7VDDD
−
VDDD + 0.5
V
VIL(xtal)
LOW level CMOS input
voltage pin XTALI
−0.3
−
+0.8
V
VIH(xtal)
HIGH level CMOS input
voltage pin XTALI
2.0
−
VDDD + 0.3
V
VILn
LOW level input voltage all
other inputs
−0.3
−
+0.8
V
VIHn
HIGH level input voltage
all other inputs
2.0
−
5.5
V
−
−
1
µA
−
−
8
pF
−
−
5
pF
Digital inputs
ILI
input leakage current
Ci
input capacitance
Ci(n)
input capacitance all other
inputs
outputs at 3-state
Digital outputs
VOL(SCL,SDA)
LOW level output voltage
pins SDA and SCL
SDA/SCL at 3 mA (6 mA)
sink current
−
−
0.4 (0.6)
V
VOL
LOW level output voltage
VDDD = max; IOL = 2 mA
0
−
0.4
V
VOH
HIGH level output voltage
VDDD = min, IOH = −2 mA
2.4
−
VDDD + 0.5
V
VOL(clk)
LOW level output voltage
for clocks
−0.5
−
+0.6
V
VOH(clk)
HIGH level output voltage
for clocks
2.4
−
VDDD + 0.5
V
ILO
output leakage current
−
−
10
µA
at 3-state mode
FEI input timing
tSU;DAT
input data set-up time
13
−
−
ns
tHD;DAT
input data hold time
3
−
−
ns
1998 May 15
24
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SYMBOL
PARAMETER
SAA7111A
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Data and control output timing; note 1
CL
output load capacitance
15
−
40
pF
tOHD;DAT
output hold time
CL = 15 pF
4
−
−
ns
tPD
propagation delay
CL = 25 pF
−
−
20
ns
tPDZ
propagation delay to
3-state
−
−
20
ns
15
−
40
pF
LLC
35
−
39
ns
LLC2
70
−
78
ns
CL = 25 pF
40
−
60
%
Clock output timing (LLC and LLC2); note 2
CL(LLC)
output load capacitance
Tcy
cycle time
δLLC
duty factors for tLLCH/tLLC
and tLLC2H/tLLC2
tr
rise time LLC, LLC2
−
−
5
ns
tf
fall time LLC, LLC2
−
−
5
ns
td
delay time LLC output to
LLC2 output
at 1.5 V;
LLC/LLC2 = 25 pF
−4
−
+8
ns
Data qualifier output timing (CREF)
tOHD;CREF
output hold time
CL = 15 pF
4
−
−
ns
tPD;CREF
propagation delay from
positive edge of LLC
CL = 25 pF
−
−
20
ns
40
−
60
%
50 Hz field
−
15625
−
Hz
60 Hz field
−
15734
−
Hz
−
−
5.7
%
PAL BGHI
−
4433619
−
Hz
NTSC M; NTSC-Japan
−
3579545
−
Hz
PAL M
−
3575612
−
Hz
PAL N
−
3582056
−
Hz
±400
−
−
Hz
−
24.576
−
MHz
−
−
±50
10−6
Clock input timing (XTALI)
δXTALI
duty factor for tXTALIH/tXTALI nominal frequency
Horizontal PLL
fHn
∆fH/fHn
nominal line frequency
permissible static deviation
Subcarrier PLL
fSCn
∆fSC
nominal subcarrier
frequency
lock-in range
Crystal oscillator
fn
nominal frequency
∆f/fn
permissible nominal
frequency deviation
1998 May 15
3rd harmonic; note 3
25
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SYMBOL
PARAMETER
SAA7111A
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Crystal oscillator
fn
nominal frequency
−
24.576
−
MHz
∆f/fn
permissible nominal
frequency deviation
−
−
±50
10−6
∆Tf/fn
permissible nominal
frequency deviation with
temperature
−
−
±20
10−6
3rd harmonic; note 3
CRYSTAL SPECIFICATION (X1)
Tamb(X1)
operating ambient
temperature
0
−
70
°C
CL
load capacitance
8
−
−
pF
Rs
series resonance resistor
−
40
80
Ω
C1
motional capacitance
−
1.5 ±20%
−
fF
C0
parallel capacitance
−
3.5 ±20%
−
pF
Notes
1. The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); CL = 50 pF.
2. The effects of rise and fall times are included in the calculation of tOHD;DAT, tPD and tPDZ. Timings and levels refer to
drawings and conditions illustrated in Figs 15 and 16.
3. Order number: Philips 4322 143 05291.
Table 2
Processing delay
FUNCTION
TYPICAL ANALOG DELAY
AI22 → ADCIN (AOUT) (ns)
Without amplifier or anti-alias filter
15
With amplifier, without anti-alias filter
25
With amplifier and anti-alias filter
75
DIGITAL DELAY
ADCIN → VPO (LLC CLOCKS)
[YDEL(2 to 0) = 000]; note 1
179
Note
1. Digital processing delay (LLC CLOCKS) for VBI data is defined in Fig.23 ‘Horizontal timing diagram’.
1998 May 15
26
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
13 TIMING DIAGRAMS
tLLC
handbook, full pagewidth
tLLCL
2.6 V
1.5 V
0.6 V
CLOCK OUTPUT LLC
t
tr
f
t
LLCH
tPD
tOHD;DAT
2.4 V
0.6 V
OUTPUTS VPO, HREF,
VREF, VS, HS
MGC658
An explanation of the output formats is given in Table 6.
Fig.15 Clock/data timing (8-bit CCIR-656 format of the VPO-bus).
tLLC
tLLC
handbook, full pagewidth
tLLCL
2.6 V
1.5 V
0.6 V
CLOCK OUTPUT LLC
tf
tLLCH
tr
t
tPD
PD
2.4 V
0.6 V
OUTPUT CREF
tOHD;CREF
tOHD;CREF
tdLLC2
tdLLC2
2.6 V
1.5 V
0.6 V
CLOCK OUTPUT LLC2
tPD
tOHD;DAT
2.4 V
0.6 V
OUTPUTS VPO, HREF,
VREF, VS, HS
MGC659
An explanation of the output formats is given in Table 6. The FEI timing of the VPO-bus is illustrated in Figs 18 and 19.
Fig.16 Clock/data timing (12 and 16-bit CCIR-601 format of the VPO-bus).
1998 May 15
27
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
tLLC
handbook, full pagewidth
tLLC
tLLCL
2.4 V
1.5 V
0.6 V
CLOCK OUTPUT LLC
,,,,
,,,,,
,,,,,
,,,,
,,,,,
,,,,,
,,,, ,,,,, ,,,,,
tf
tr
tLLCH
tPD;CREF
OUTPUT CREF
tOHD;CREF
2.4 V
1.5 V
0.6 V
tOHD;CREF
tPD;CREF
RGB (8, 8, 8) data
VPO15 to VPO8
RGB (8, 8, 8) data
VPO7 to VPO0
tOHD;CREF
2.4 V
1.5 V
0.6 V
R(7 : 3)
G(7 : 5)
,,,
,,,
,,
,,
tOHD;DAT
R(2 : 0)
G(1 : 0)
B(2 : 0)
,,,
,,,
tOHD;DAT
G(4 : 2)
B(7 : 3)
tPD
An explanation of the output formats is given in Table 6.
Fig.17 Clock/data timing for RGB (8, 8 and 8) output format.
handbook, full pagewidth
LLC
CREF
HREF
tSU;DAT
tHD;DAT
FEI
tPDZ
tOHD;DAT
t
PD
VPO
MGC656
to 3-state
from 3-state
I2C-bus bit FECO = 1.
Fig.18 FEI timing diagram (FEI sampling at CREF = HIGH) for OFTS = 0, 1 or 2).
1998 May 15
28
2.4 V
1.5 V
0.6 V
MBH227
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
handbook, full pagewidth
SAA7111A
LLC
CREF
HREF
tSU;DAT
tHD;DAT
FEI
tPDZ
tOHD;DAT
tPD
VPO
MGC657
from 3-state
to 3-state
Timing is compatible with SAA7110; I2C-bus bit FECO = 0.
Fig.19 FEI timing diagram (FEI sampling at CREF = LOW) for OFTS = 0, 1 or 2).
transmitted once per line
handbook, full pagewidth
INCRHPLL
HIGH
16
128
BIT NO.:
TIME SLOT:
15
0 1
INCRFSCPLL
45
2
0
RESERVED
RESERVED
SEQUENCE
LOW
DTO RESET(1)
RESERVED
50 Hz fields: 235
60 Hz fields: 232
3 1
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
63 67 68
16 19
MGC649
(1) Set to zero for one transmission, if a phase reset of the fsc − DTO is applied via I2C-bus bit CDTO. RTCO sequence is generated in LLC/4.
The HPLL increment represents the actual LFCO frequency (fLFCO × 4 = fLLC); 16 LSB from 20, upper four bits are fixed to 0100b.
INCR HPLL × f XTAL
f LFCO = -----------------------------------------------word length DTO2
2
Where: fXTAL = 24.576 MHz, word length DTO2 = 20 bits.
The fsc increment represents the actual subcarrier frequency (related to the actual clock); 23 LSB from 24, MSB is 0b.
INCR FSCPLL × f XTAL INCR HPLL
f sc = ------------------------------------------------------ × --------------------------word length DTO1
19
2
2
Where: word length DTO1 = 24 bits.
Fig.20 Real time control output.
1998 May 15
29
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
handbook, full pagewidth
SAA7111A
LLC
CREF
LLC2
START OF ACTIVE LINE
HREF
Yn
0
1
2
3
4
UVn
U0
V0
U2
V2
U4
END OF ACTIVE LINE
HREF
Yn
715
716
717
718
719
UVn
V714
U716
V716
U718
V718
MGC646
Fig.21 HREF timing diagram.
handbook, full pagewidth
LLC
tSU
tHD
FEI
tOHD
VPO
tPDZ
,,,
,,,
tPD
Fig.22 FEI timing in CCIR 656 mode [OFTS (1 : 0) = 3].
1998 May 15
30
MBH766
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
handbook, full pagewidth
SAA7111A
burst
CVBS
26 × 1/LLC
burst
VBI
179 × 1/LLC
Y - output
processing delay CVBS->VPO(2)
0
sync clipped
HREF (50 Hz)
12 × 2/LLC
144 × 2/LLC
720 × 2/LLC
43 × 2/LLC
27 × 2/LLC
RTS1 (PLIN)(1)
4/LLC
HS
HS (50 Hz)
108
programming range
(step size: 8/LLC)
−107
0
HREF (60 Hz)
23 × 2/LLC
16 × 2/LLC
138 × 2/LLC
720 × 2/LLC
HS (60 Hz)
HS (60 Hz)
programming range
(step size: 8/LLC)
107
0
MGD701
(1) PLIN is switched to output RTS1 via I2C-bus bit RTSE1 = 0.
(2) See Table 2.
(3) HDEL (1 : 0) = 0 0, YDEL (2 : 0) = 0 0 0.
Fig.23 Horizontal timing diagram.
1998 May 15
−106
31
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
622
handbook, full pagewidth
623
624
625
1
2
3
SAA7111A
4
5
6
7
8
22
23
input CVBS
HREF
VREF VRLN = 1(2)
VREF VRLN = 0(2)
535 x 2/LLC
VS
RTS0 (ODD)(1)
(a) 1st field
310
311
312
313
314
315
316
317
318
319
320
335
336
337
input CVBS
HREF
VREF
VRLN = 1(2)
VREF
VRLN = 0(2)
77 x 2/LLC
VS
RTS0 (ODD)(1)
MGG069
(b) 2nd field
(1) ODD is switched to output RTS0 via I2C-bus bit RTSE0 = 0.
(2) Additional VREF positions can be achieved via I2C-bits VCTR1 and VCTR0 (see Fig.9).
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1.
The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
Fig.24 Vertical timing diagram for 50 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].
1998 May 15
32
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
handbook, full pagewidth
523
(1)
522
(525)
524
(2)
525
(3)
1
(4)
2
(5)
3
(6)
SAA7111A
4
(7)
5
(8)
6
(9)
7
(10)
8
(11)
17
(20)
18
(21)
19
(22)
(2)
input CVBS
HREF
VRLN = 1(3)
VREF
VRLN = 0(3)
VREF
520 x 2/LLC
VS
RTS0 (ODD)(1)
(a) 1st field
259
(262)
260
(263)
261
(264)
262
(265)
263
(266)
264
(267)
265
(268)
266
(269)
267
(270)
268
(271)
269
(272)
270
(273)
271
(274)
280
(283)
281
(284)
(2)
input CVBS
HREF
VRLN = 1(3)
VREF
VRLN = 0(3)
VREF
81 x 2/LLC
VS
RTS0 (ODD)(1)
(b) 2nd field
MGG070
(1) ODD is switched to output RTS0 via I2C-bus bit RTSE0 = 0.
(2) Line numbers in parenthesis refer to CCIR line counting.
(3) Additional VREF positions can be achieved via I2C-bus bits VCTR1 and VCTR0 (see Fig.9).
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I2C-bus bit VBLB is set to logic 1.
The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
Fig.25 Vertical timing diagram for 60 Hz [nominal input signal VNL in normal mode (VNOI = 00b)].
1998 May 15
282
(285)
33
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
Table 3
Digital output control
SAA7111A
14 CLOCK SYSTEM
VPO
15 to 8
14.1
VPO
7 to 0
Clock generation circuit
OEYC
FEI
TCLO(1)
0
0
0
Z
1
0
0
active
0
1
0
Z
1
1
0
Z
0
0
1
Z
Z
1
0
1
active
Z
0
1
1
Z
Z
CLOCK
FREQUENCY (MHz)
1
1
1
Z
Z
XTAL
24.576
Note
LLC
27
1. Only active in 656-format (OFTS = 3).
LLC2
13.5
LLC4
6.75
LLC8
3.375
handbook, full pagewidth
LFCO
BAND PASS
FC = LLC/4
ZERO
CROSS
DETECTION
The internal CGC generates the system clocks LLC, LLC2
and the clock reference signal CREF. The internally
generated LFCO (triangular waveform) is multiplied by 4
via the analog PLL (including phase detector, loop filter,
VCO and frequency divider). The rectangular output
signals have a 50% duty factor.
Table 4
PHASE
DETECTION
Clock frequencies
LOOP
FILTER
OSCILLATOR
LLC
DIVIDER
1/2
DIVIDER
1/2
LLC2
DELAY
CREF
MGC632
Fig.26 Block diagram of clock generation circuit.
1998 May 15
34
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
14.2
SAA7111A
Power-on control
Power-on reset is activated at power-on, chip enable, PLL clock generation failure and if the supply voltage falls below
2.7 V. The RES signal can be applied to reset other circuits of the digital picture processing system.
handbook, full pagewidth
POC VDDA
POC VDDD
ANALOG
DIGITAL
POC
LOGIC
POC
DELAY
CLOCK
PLL
LLC
RES
CE
CLK0
CE
XTAL
LLCINT
RESINT
LLC
RES
some ms
20 to 200 µs
PLL-delay
896 LCC
digital delay
<1 ms
CE = chip enable input; XTAL = crystal oscillator output; LLCINT = internal system clock;
RESINT = internal reset; LLC = line-locked clock output; RES = reset output (active LOW).
Fig.27 Power-on control circuit.
1998 May 15
35
128 LCC
MGC633
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
Table 5
SAA7111A
Power-on control sequence
INTERNAL POWER-ON CONTROL
SEQUENCE
PIN OUTPUT STATUS
FUNCTION
Directly after power-on
asynchronous reset
VPO15 to VPO0, RTCO, RTS0, RTS1, direct switching to high impedance for
GPSW, HREF, VREF, HS, VS, LLC,
20 to 200 ms
LLC2 and CREF are in high-impedance
state
Synchronous reset sequence
LLC, LLC2, CREF, RTCO, RTS0,
internal reset sequence
RTS1, GPSW and SDA become active;
VPO15 to VPO0, HREF, VREF, HS and
VS are held in high-impedance state
Status after power-on control
sequence
VPO15 to VPO0, HREF, VREF, HS and after power-on (reset sequence) a
VS are held in high-impedance state
complete I2C-bus transmission is
required
15 OUTPUT FORMATS
Table 6
Output formats of the VPO bus (note 1)
BUS
SIGNAL
VPO15
VPO14
VPO13
VPO12
VPO11
VPO10
VPO9
VPO8
VPO7
VPO6
VPO5
VPO4
VPO3
VPO2
VPO1
VPO0
Pixel
order Y
Pixel
order UV
Data rates
I2C-bus
control
signals
1998 May 15
422
(16-BIT)(2)
411 (12-BIT)
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
U07
U06
V07
V06
X
X
X
X
0
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
U05
U04
V05
V04
X
X
X
X
1
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
U03
U02
V03
V02
X
X
X
X
2
Y37
Y36
Y35
Y34
Y33
Y32
Y31
Y30
U01
U00
V01
V00
X
X
X
X
3
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
U07
U06
U05
U04
U03
U02
U01
U00
0
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
V07
V06
V05
V04
V03
V02
V01
V00
1
CCIR-656 (8-BIT)(3)
U07
U06
U05
U04
U03
U02
U01
U00
X
X
X
X
X
X
X
X
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
X
X
X
X
X
X
X
X
V07
V06
V05
V04
V03
V02
V01
V00
X
X
X
X
X
X
X
X
0
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
X
X
X
X
X
X
X
X
1
RGB (16-BIT)(4)
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
−
RGB (24-BIT)(4)
R7
R6
R5
R4
R3
G7
G6
G5
G4
G3
G2
B7
B6
B5
B4
B3
note 5
R7
R6
R5
R4
R3
G7
G6
G5
R2
R1
R0
G1
G0
B2
B1
B0
note 6
0
0
0
−
−
LLC2
OFTS0 = 0
OFTS1 = 1
RGB888 = X
LLC2
OFTS0 = 1
OFTS1 = 0
RGB888 = X
LLC
OFTS0 = 1
OFTS1 = 1
RGB888 = X
LLC2
OFTS0 = 0
OFTS1 = 0
RGB888 = 0
−
OFTS0 = 0
OFTS1 = 0
RGB888 = 1
36
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
Notes to Table 5
1. VPO bus allows connection to 5 V video data bus systems.
2. Values in accordance with CCIR 601.
3. Before and after the video data, video timing codes are inserted in accordance with CCIR 656.
a) VPO15 to VPO8 = VPO7 to VPO0 = CCIR 656 data if I2C-bus bit TCLO = 0
b) VPO15 to VPO8 = CCIR 656 data, VPO7 to VPO0 = 3-state if I2C-bus bit TCLO = 1.
4. During HREF = LOW RGB levels are set to 16 (10 hex). RGB 16-bit is achieved by dropping the LSBs of the 8-bit
signals (after dithering if desired).
5. CREF = 0 (see Fig.17).
6. CREF = 1 (see Fig.17).
+255
handbook, full pagewidth
+235
white
+128
LUMINANCE 100%
+255
+240
blue 100%
+255
+240
red 100%
+212
blue 75%
+212
red 75%
+128
colourless
+128
colourless
U-COMPONENT
+16
black
V-COMPONENT
+44
yellow 75%
+44
cyan 75%
+16
yellow 100%
+16
cyan 100%
0
0
0
MGC634
a.
Y output range.
b.
U output range (Cb).
c.
V output range (Cr).
CCIR Rec. 602 digital levels.
Equations for modification to the YUV levels via BCS control I2C-bus bytes BRIG, CONT and SATN.
Luminance:
CONT
Y OUT = Int ------------------ × ( Y – 128 ) + BRIG
71
Chrominance:
SATN
UV OUT = Int ----------------- × ( Cr, Cb – 128 ) + 128
64
It should be noted that the resulting levels are limited to 1 to 254 in accordance with CCIR-601/656 standard.
Fig.28 VPO output signal range with default BCS settings.
1998 May 15
37
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
handbook, full pagewidth
+255
SAA7111A
+255
+209
white
+199
LUMINANCE
+71
+60
white
LUMINANCE
black
black shoulder
+60
black shoulder = black
SYNC
SYNC
1
1
sync bottom
sync bottom
MGD700
a.
b.
For sources containing 7.5 IRE black level offset (e.g. NTSC−M).
For sources not containing black level offset.
VBI data levels are not dependent on BCS settings.
Fig.29 VBI data bypass output range.
handbook, full pagewidth
quartz (3rd harmonic)
24.576 MHz
XTAL
XTAL
54
C=
10 pF
54
SAA7111A
XTALI
SAA7111A
XTALI
55
55
MGG072
L = 10 µH ± 20%
C=
10 pF
a.
C=
1 nF
b.
With quartz crystal.
Order number: Philips 4322 143 05291.
Fig.30 Oscillator application.
1998 May 15
38
With external clock.
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
16 APPLICATION INFORMATION
VDD
VDDA
C15
100 nF C14
C9
C13 100 nF
BST
11
15
59
2
3
58
57
41
33
25
35
22 nF
36
VSSA 47 Ω
37
R9
C3
38
27 Ω
R3
22 nF
AI21
8
VDDD
42
44
C2
45
10
22 nF
46
47
VSSA 47 Ω
R7
AI11
27 Ω
R1
VSSA 47 Ω
39
43
VSSA 47 Ω
R8
AI12
27 Ω
R2
48
C1
49
12
SAA7111A
50
22 nF
51
R5
31
24
1 kΩ
SCL
63
SDA
62
52
FEI
R6
1 kΩ
VSS
XTAL
54
Q1(24.576 MHz)
XTALI
10
µH
VSS
19 61
VSS
VSS n.c.
Fig.31 Application diagram.
39
14
13
12
11
10
9
8
VPO(15 : 0)
7
6
5
4
3
2
1
0
HREF
17
VREF
27
HS
30
VS
60
RTCO
28
RTS1
29
RTS0
53
GPSW
14
AOUT
20
LLC
21
LLC2
22
CREF
23
RES
1
n.c.
VSSA
1998 May 15
64
15
IICSA
32 26
VSS5
56 40
VSS4
13
VSS3
5
VSS2
9
VSS1
10 pF 10 pF
16
VSSS
1 nF
C18
VSSA2
C17
VSSA1
C16
VSSA0
L1
55
VSS
100 nF
18
34
6
27 Ω
R4
C11 100 nF
VDD5
TRST
TCK
TDO
TDI
TMS
4
7
n.c.
C4
R10
AI22
n.c.
VDDA2
VDDA1
VDDA0
100 nF
VSSA
100 nF C12
VSS
n.c.
VDD4
100 nF
C7
VDD3
100 nF
VDD2
C8
VDD1
handbook, full pagewidth
MGG071
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
handbook, full pagewidth
34
35
36
VPO
(15 : 8)
37
38
39
42
43
VPO (15 : 11)
15
R (7 : 3)
3
14
13
G (7 : 5)
VPO (10 : 8)
12
3
11
VPO (7 : 5)
10
G (4 : 2)
3
9
8
VSS
VDD
OEN
44
45
46
VPO
(7 : 0)
47
48
49
50
51
SAA7111A
7
6
5
D7
O7
D6
O6
O5
D5
4
D4
3
e.g.
O4
D3 74HCT574 O3
2
1
0
D2
O2
D1
O1
VDD
R (2 : 0)
3
8
2
8
3
8
G (1 : 0)
B (2 : 0)
R (7 : 0)
G (7 : 0)
B (7 : 0)
00
D0
VSS
CLK
VSS
SAA7111A
VPO (4 : 0)
B (7 : 3)
5
31
HREF
17
VREF
27
HS
30
VS
60
RTCO
28
RTS1
29
RTS0
53
GPSW
14
AOUT
20
LLC
21
32
CREF
23
RES
e.g. 74HCT240
LLC2
LLC2N
MGG073
I2C-bus control bits:
OFTS(1 : 0) = 00 (subaddress 10H, bits D7 and D6).
RGB888 = 1 (subaddress 12H, bit D3).
Fig.32 Application diagram for RGB 24-bit output format.
16.1
Place the coupling (clamp) capacitors close to the analog
input pins. Place the termination resistors close to the
coupling capacitors. Care should be exercised concerning
the hidden layout capacitors around the crystal
application. To avoid reflection effects use serial resistors
in the clock, sync and data lines.
Layout hints
Use separate ground planes for analog and digital ground.
Connect these planes at one point directly under the
device, by using a zero Ω resistor. Use separate supply
lines for analog and digital supply. Place the supply
decoupling capacitors close to the supply pins.
1998 May 15
40
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17 I2C-BUS DESCRIPTION
17.1
I2C-bus format
Table 7
S
Write procedure
SLAVE ADDRESS W
Table 8
ACK-s
SUBADDRESS
ACK-s
DATA (N BYTES)
P
Read procedure (combined format)
S
SLAVE ADDRESS W
ACK-s
SUBADDRESS
Sr
SLAVE ADDRESS R
ACK-s
DATA (N BYTES)
Table 9
ACK-s
ACK-s
ACK-m
P
Description of I2C-bus format
CODE
DESCRIPTION
S
START condition
Sr
repeated START condition
Slave address W
0100 1000b (IICSA = LOW) or 0100 1010b (IICSA = HIGH)
Slave address R
0100 1001b (IICSA = LOW) or 0100 1011b (IICSA = HIGH)
ACK-s
acknowledge generated by the slave
ACK-m
acknowledge generated by the master
Subaddress
subaddress byte; see Table 10
Data
data byte; see Table 10; note 1
P
STOP condition
X = LSB slave
address
read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read
(the circuit is slave transmitter)
Slave address
read = 49H or 4BH; note 2
write = 48H or 4AH
IICSA = 0 or 1
Subaddresses
00H chip version
read and write; note 3
01H reserved
−
02h to 05H front-end part
read and write
06H to 13H decoder part
read and write
14H reserved
−
15H to 17H decoder part
read and write
18H to 19H reserved
−
1AH to 1CH Line-21 text slicer part
read only
1DH to 1EH reserved
−
1FH status byte
read only
Notes
1. If more than one byte DATA is transmitted then the auto-increment of the subaddress is performed.
2. During slave transmitter mode the SCL-LOW period may be extended by pulling SCL to LOW (in accordance with
the I2C-bus specification).
3. The I2C-bus subaddress 00 has to be initialized with 0 before being read.
1998 May 15
41
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
Table 10 I2C-bus receiver/transmitter overview
READ
WRITE
IICSA
49H
4BH
48H
4AH
0
1
SLAVE ADDRESS
REGISTER
FUNCTION
SUBADDR
D7
D6
D5
D4
D3
D2
D1
D0
00
ID07
ID06
ID05
ID04
ID03
ID02
ID01
ID00
Reserved
01
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Analog input contr 1
02
FUSE1
FUSE0
GUDL2
GUDL1
GUDL0
MODE2
MODE1
MODE0
Analog input contr 2
03
(1)
HLNRS
VBSL
WPOFF
HOLDG
GAFIX
GAI28
GAI18
Analog input contr 3
04
GAI17
GAI16
GAI15
GAI14
GAI13
GAI12
GAI11
GAI10
Analog input contr 4
05
GAI27
GAI26
GAI25
GAI24
GAI23
GAI22
GAI21
GAI20
Horizontal sync start
06
HSB7
HSB6
HSB5
HSB4
HSB3
HSB2
HSB1
HSB0
Horizontal sync stop
07
HSS7
HSS6
HSS5
HSS4
HSS3
HSS2
HSS1
HSS0
Chip version
Sync control
08
AUFD
FSEL
EXFIL
(1)
VTRC
HPLL
VNOI1
VNOI0
Luminance control
09
BYPS
PREF
BPSS1
BPSS0
VBLB
UPTCV
APER1
APER0
Luminance
brightness
0A
BRIG7
BRIG6
BRIG5
BRIG4
BRIG3
BRIG2
BRIG1
BRIG0
Luminance contrast
0B
CONT7
CONT6
CONT5
CONT4
CONT3
CONT2
CONT1
CONT0
Chroma saturation
0C
SATN7
SATN6
SATN5
SATN4
SATN3
SATN2
SATN1
SATN0
Chroma Hue control
0D
HUEC7
HUEC6
HUEC5
HUEC4
HUEC3
HUEC2
HUEC1
HUEC0
Chroma control
0E
CDTO
CSTD2
CSTD1
CSTD0
DCCF
FCTC
CHBW1
CHBW0
Reserved
0F
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Format/delay control
10
OFTS1
OFTS0
HDEL1
HDEL0
VRLN
YDEL2
YDEL1
YDEL0
Output control 1
11
GPSW
CM99
FECO
COMPO
OEYC
OEHV
VIPB
COLO
Output control 2
12
RTSE1
RTSE0
TCLO
CBR
RGB888
DIT
AOSL1
AOSL0
Output control 3
13
VCTR1
VCTR0
CCTR1
CCTR0
BCHI1
BCHI0
BCLO1
BCLO0
Reserved
14
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
V_GATE1_START
15
VSTA7
VSTA6
VSTA5
VSTA4
VSTA3
VSTA2
VSTA1
VSTA0
V_GATE1_STOP
16
VSTO7
VSTO6
VSTO5
VSTO4
VSTO3
VSTO2
VSTO1
VSTO0
V_GATE1_MSB
17
(1)
(1)
(1)
(1)
(1)
(1)
VSTO8
VSTA8
18-19
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Text slicer status
1A
(1)
(1)
(1)
(1)
F2VAL
F2RDY
F1VAL
F1RDY
Decoded bytes of
the text slicer
1B
P1
BYTE16 BYTE15 BYTE14
BYTE13
BYTE12
BYTE11
BYTE10
BYTE26 BYTE25 BYTE24
Reserved
Reserved
Status byte
1C
P2
BYTE23
BYTE22
BYTE21
BYTE20
1D-1E
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
1F
STTC
HLCK
FIDT
GLIMT
GLIMB
WIPA
SLTCA
CODE
Note
1. All unused control bits must be programmed with logic 0.
1998 May 15
42
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
17.2
SAA7111A
I2C-bus detail
The I2C-bus receiver slave address is 48H/49H. Subaddresses 0F, 14, 18, 19, 1D and 1E are reserved; subaddress 01
is reserved for chip version.
17.2.1
SUBADDRESS 00
Table 11 Chip version SA00; note 1
LOGIC LEVELS
FUNCTION
Chip version
ID07
ID06
ID05
ID04
ID03
ID02
ID01
ID00
V1
0
0
0
1
X
X
X
X
V2
0
0
1
0
X
X
X
X
Note
1. X = reserved.
17.2.2
SUBADDRESS 02
Table 12 Analog control 1 SA02; note 1
CONTROL BITS D2 TO D0
FUNCTION(2)
MODE 2
MODE 1
MODE 0
Mode 0 : CVBS (automatic gain)
0
0
0
Mode 1 : CVBS (automatic gain)
0
0
1
Mode 2 : CVBS (automatic gain)
0
1
0
Mode 3 : CVBS (automatic gain)
0
1
1
Mode 4 : Y (automatic gain) + C (gain channel 2 fixed to GAI2 level)
1
0
0
Mode 5 : Y (automatic gain) + C (gain channel 2 fixed to GAI2 level)
1
0
1
Mode 6 : Y (automatic gain) + C (gain channel 2 adapted to Y gain)
1
1
0
Mode 7 : Y (automatic gain) + C (gain channel 2 adapted to Y gain)
1
1
1
Notes
1. Mode select (see Figs 33 to 40).
2. For modes 0 to 3 use BYPS(SA09,D7) = 0 (chrominance trap active), for modes 4 to 7 use BYPS = 1 (chrominance
trap bypassed).
Table 13 Analog control 1 SA 02, D5 to D3 (see Fig.14)
CONTROL BITS D5 TO D3
DECIMAL VALUE
UPDATE HYSTERESIS FOR 9-BIT GAIN
GUDL 2
GUDL 1
GUDL 0
0....
off
0
0
0
....7
±7 LSB
1
1
1
1998 May 15
43
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
Table 14 Analog control
CONTROL BITS D7 AND D6
ANALOG FUNCTION SELECT FUSE
Amplifier plus anti-alias filter bypassed
FUSE 1
FUSE 0
0
0
0
1
Amplifier active
1
0
Amplifier plus anti-alias filter active
1
1
handbook,AI22
halfpage
AI21
AI12
AI11
AD2
AD1
handbook,AI22
halfpage
CHROMA
AI21
LUMA
AI12
AI11
AD2
AD1
handbook,AI22
halfpage
AI21
AI12
AI11
AD2
AD1
Fig.34 Mode 1; CVBS (automatic gain).
handbook,AI22
halfpage
CHROMA
AI21
LUMA
AI12
AI11
AD2
AD1
MGC639
AI21
AI12
AI11
AD2
AD1
LUMA
Fig.36 Mode 3; CVBS (automatic gain).
handbook,AI22
halfpage
CHROMA
AI21
LUMA
AI12
AI11
MGC641
AD2
AD1
CHROMA
LUMA
MGC642
Fig.37 Mode 4 Y (automatic gain) + C
(gain channel 2 fixed to GAI2 level).
1998 May 15
CHROMA
MGC640
Fig.35 Mode 2; CVBS (automatic gain).
handbook,AI22
halfpage
LUMA
MGC638
MGC637
Fig.33 Mode 0; CVBS (automatic gain).
CHROMA
Fig.38 Mode 5 Y (automatic gain) + C
(gain channel 2 fixed to GAI2 level).
44
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
handbook,AI22
halfpage
AD2
AI21
AI12
AI11
AD1
SAA7111A
handbook,AI22
halfpage
CHROMA
AI21
LUMA
AI12
AI11
AD2
AD1
MGC643
LUMA
MGC644
Fig.39 Mode 6 Y (automatic gain) + C
(gain channel 2 adapted to Y gain).
17.2.3
CHROMA
Fig.40 Mode 7 Y (automatic gain) + C
(gain channel 2 adapted to Y gain).
SUBADDRESS 03
Table 15 Analog control 2 (AICO2) SA03
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
GAI18
see Table 16
D0
GAI28
see Table 17
D1
Automatic gain controlled by MODE 1 and MODE 0
GAFIX
0
D2
Gain control is user programmable via GAI1 + GAI2
GAFIX
1
D2
AGC active
HOLDG
0
D3
AGC integration hold (freeze)
HOLDG
1
D3
White peak control active
WPOFF
0
D4
White peak off
WPOFF
1
D4
Long vertical blanking
VBSL
0
D5
Short vertical blanking
VBSL
1
D5
Normal clamping by HL not
HLNRS
0
D6
Reference select by HL not
HLNRS
1
D6
Static gain control channel 1 (GAI18) (see SA04)
Sign bit of gain control
Static gain control channel 2 (GAI28) (see SA05)
Sign bit of gain control
Gain control fix (GAFIX)
Automatic gain control integration (HOLDG)
White peak off (WPOFF)
Vertical blanking select (VBSL)
HL not reference select (HLNRS)
1998 May 15
45
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
17.2.4
SAA7111A
SUBADDRESS 04
Table 16 Gain control analog (AIC03); static gain control channel 1 GAI1 SA 04, D7 to D0
DECIMAL
VALUE
GAIN
(dB)
SIGN
BIT
CONTROL BITS D7 TO D0
GAI18
GAI17
GAI16
GAI15
GAI14
GAI13
GAI12
GAI11
GAI10
0....
−5.98
0
0
0
0
0
0
0
0
0
....255
0
0
1
1
1
1
1
1
1
1
256....
0
1
0
0
0
0
0
0
0
0
....511
5.98
1
1
1
1
1
1
1
1
1
17.2.5
SUBADDRESS 05
Table 17 Gain control analog (AIC04); static gain control channel 2 GAI2 SA 05, D7 to D0
DECIMAL
VALUE
GAIN
(dB)
SIGN BIT
(SA 03, D1)
CONTROL BITS D7 to D0
GAI28
GAI27
GAI26
GAI25
GAI24
GAI23
GAI22
GAI21
GAI20
0....
−5.98
0
0
0
0
0
0
0
0
0
....255
0
0
1
1
1
1
1
1
1
1
256....
0
1
0
0
0
0
0
0
0
0
....511
5.98
1
1
1
1
1
1
1
1
1
17.2.6
SUBADDRESS 06
Table 18 Horizontal sync begin SA 06, D7 to D0
DELAY TIME
(STEP SIZE = 8/LLC)
CONTROL BITS D7 to D0
HSB7
HSB6
−128...−108
HSB5
HSB4
HSB3
HSB2
HSB1
HSB0
forbidden (outside available central counter range)
−107...
1
0
0
1
0
1
0
1
...108 (50Hz)
0
1
1
0
1
1
0
0
...107 (60Hz)
0
1
1
0
1
0
1
1
109...127 (50Hz)
108...127 (60Hz)
1998 May 15
forbidden (outside available central counter range)
46
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
17.2.7
SAA7111A
SUBADDRESS 07
Table 19 Horizontal sync stop SA 07, D7 to D0
CONTROL BITS D7 to D0
DELAY TIME
(STEP SIZE = 8/LLC)
HSS7
HSS6
−128...−108
HSS4
HSS3
HSS2
HSS1
HSS0
forbidden (outside available central counter range)
−107...
1
0
0
1
0
1
0
1
...108 (50Hz)
0
1
1
0
1
1
0
0
...107 (60Hz)
0
1
1
0
1
0
1
1
109...127 (50Hz)
forbidden (outside available central counter range)
108...127 (60Hz)
17.2.8
HSS5
SUBADDRESS 08
Table 20 Sync control SA 08, D7 to D5, D3 to D0
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
VNOI1
0
D1
VNOI0
0
D0
VNOI1
0
D1
VNOI0
1
D0
VNOI1
1
D1
VNOI0
0
D0
VNOI1
1
D1
VNOI0
1
D0
PLL closed
HPLL
0
D2
PLL open, horizontal frequency fixed
HPLL
1
D2
TV mode
(recommended for poor quality TV signals only)
VTRC
0
D3
VTR mode (recommended as default setting)
VTRC
1
D3
Word width of the loop filter (LF2) amplification = 16-bit
EXFIL
0
D5
Word width of the loop filter (LF2) amplification = 14-bit
EXFIL
1
D5
50 Hz, 625 lines
FSEL
0
D6
60 Hz, 525 lines
FSEL
1
D6
Field state directly controlled via FSEL
AUFD
0
D7
Automatic field detection
AUFD
1
D7
Vertical noise reduction (VNOI)
Normal mode
Searching mode
Free running mode
Vertical noise reduction bypassed
Horizontal PLL (HPLL)
TV/VTR mode select (VTRC)
Extended loop filter (EXFIL)
Field selection (FSEL)
Automatic field detection (AUFD)
1998 May 15
47
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
17.2.9
SAA7111A
SUBADDRESS 09
Table 21 Luminance control SA 09, D7 to D0
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
Aperture factor (APER)
Aperture factor = 0
Aperture factor = 0.25
Aperture factor = 0.5
Aperture factor = 1.0
APER1
0
D1
APER0
0
D0
APER1
0
D1
APER0
1
D0
APER1
1
D1
APER0
0
D0
APER1
1
D1
APER0
1
D0
Horizontal update (once per line)
UPTCV
0
D2
Vertical update (once per field)
UPTCV
1
D2
Active luminance processing
VBLB
0
D3
Luminance bypass during vertical blanking
VBLB
1
D3
Update time interval for AGC value (UPTCV)
Vertical blanking luminance bypass (VBLB)
Aperture band pass (centre frequency) (BPSS)
Centre frequency = 4.1 MHz
Centre frequency = 3.8 MHz; note 1
Centre frequency = 2.6 MHz; note 1
BPSS1
0
D5
BPSS0
0
D4
BPSS1
0
D5
BPSS0
1
D4
BPSS1
1
D5
BPSS0
0
D4
BPSS1
1
D5
BPSS0
1
D4
Bypassed
PREF
0
D6
Active
PREF
1
D6
Chrominance trap active; default for CVBS mode
BYPS
0
D7
Chrominance trap bypassed; default for S-Video mode
BYPS
1
D7
Centre frequency = 2.9 MHz; note 1
Prefilter active (PREF)
Chrominance trap bypass (BYPS)
Note
1. Not to be used with bypassed chrominance trap.
1998 May 15
48
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.10 SUBADDRESS 0A
Table 22 Luminance brightness control BRIG7 to BRIG0 SA 0A
CONTROL BITS D7 to D0
OFFSET
BRIG7
BRIG6
BRIG5
BRIG4
BRIG3
BRIG2
BRIG1
BRIG0
255 (bright)
1
1
1
1
1
1
1
1
128 (CCIR level)
1
0
0
0
0
0
0
0
0 (dark)
0
0
0
0
0
0
0
0
17.2.11 SUBADDRESS 0B
Table 23 Luminance contrast control CONT7 to CONT0 SA 0B
CONTROL BITS D7 to D0
GAIN
CONT7
CONT6
CONT5
CONT4
CONT3
CONT2
CONT1
CONT0
1.999 (maximum)
0
1
1
1
1
1
1
1
1.109 (CCIR level)
0
1
0
0
0
1
1
1
1.0
0
1
0
0
0
0
0
0
0 (luminance off)
0
0
0
0
0
0
0
0
−1 (inverse luminance)
1
1
0
0
0
0
0
0
−2 (inverse luminance)
1
0
0
0
0
0
0
0
17.2.12 SUBADDRESS 0C
Table 24 Chrominance saturation control SATN7 to SATN0 SA 0C
CONTROL BITS D7 to D0
GAIN
SATN7
SATN6
SATN5
SATN4
SATN3
SATN2
SATN1
SATN0
1.999 (maximum)
0
1
1
1
1
1
1
1
1.0 (CCIR level)
0
1
0
0
0
0
0
0
0 (colour off)
0
0
0
0
0
0
0
0
−1 (inverse
chrominance)
1
1
0
0
0
0
0
0
−2 (inverse
chrominance)
1
0
0
0
0
0
0
0
17.2.13 SUBADDRESS 0D
Table 25 Chrominance hue control HUEC7 to HUEC0 SA 0D
CONTROL BITS D7 to D0
HUE PHASE (DEG)
HUEC7
HUEC6
HUEC5
HUEC4
HUEC3
HUEC2
HUEC1
HUEC0
+178.6....
0
1
1
1
1
1
1
1
....0....
0
0
0
0
0
0
0
0
....−180
1
0
0
0
0
0
0
0
1998 May 15
49
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.14 SUBADDRESS 0E
Table 26 Chrominance control SA 0E
FUNCTION
BIT NAME
LOGIC
LEVEL
CONTROL
BIT
CHBW1
CHBW0
CHBW1
CHBW0
CHBW1
CHBW0
CHBW1
CHBW0
0
0
0
1
1
0
1
1
D1
D0
D1
D0
D1
D0
D1
D0
FCTC
FCTC
0
1
D2
D2
DCCF
DCCF
0
1
D3
D3
Chroma bandwidth (CHBW0 and CHBW1)
Small bandwidth (≈ 620 kHz)
Nominal bandwidth (≈ 800 kHz)
Medium bandwidth (≈ 920 kHz)
Wide bandwidth (≈ 1000 kHz)
Fast colour time constant (FCTC)
Nominal time constant
Fast time constant
Disable chrominance comb filter (DCCF)
Chrominance comb filter on (during VREF = 1) (see Figs 24 and 25)
Chrominance comb filter off
Colour standard (CSTD0 to CSTD2); logic levels 100, 110 and 111 are reserved, do not use
Colour standard control automatic switching between PAL BGHI and
NTSC M (NTSC-Japan with special level adjustment; luminance
brightness subaddress 0A = 95H, luminance contrast
subaddress 0BH = 48H)
Colour standard control automatic switching between NTSC 4.43 (50 Hz)
and PAL 4.43 (60 Hz)
Colour standard control automatic switching between PAL N and
NTSC 4.43 (60 Hz)
Colour standard control automatic switching between NTSC N and
PAL M
Colour standard control automatic switching between SECAM and
PAL 4.43 (60 Hz)
CSTD2
CSTD1
CSTD0
0
0
0
D6
D5
D4
CSTD2
CSTD1
CSTD0
CSTD2
CSTD1
CSTD0
CSTD2
CSTD1
CSTD0
CSTD2
CSTD1
CSTD0
0
0
1
0
1
0
0
1
1
1
0
1
D6
D5
D4
D6
D5
D4
D6
D5
D4
D6
D5
D4
CDTO
CDTO
0
1
D7
D7
Clear DTO (CDTO)
Disabled
Every time CDTO is set, the internal subcarrier DTO phase is reset to 0°
and the RTCO output generates a logic 0 at time slot 68 (see RTCO
description Fig.20). So an identical subcarrier phase can be generated by
an external device (e.g. an encoder).
1998 May 15
50
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.15 SUBADDRESS 10
Table 27 Format/delay control SA 10
CONTROL BITS D2 to D0
LUMINANCE DELAY COMPENSATION
(STEPS IN 2/LLC)
YDEL2
YDEL1
YDEL0
−4...
1
0
0
...0...
0
0
0
...3
0
1
1
Table 28 VREF pulse position and length VRLN SA 10 (D3)
VREF at 60 Hz 525 LINES(1)
VREF at 50 Hz 625 LINES(1)
VRLN
Length
Line number
0
1
0
1
240
242
286
288
first
last
first
last
first
last
first
last
Field
1(2)
19 (22)
258 (261)
18 (21)
259 (262)
24
309
23
310
Field
2(2)
282 (285)
521 (524)
281 (284)
522 (525)
337
622
336
623
Notes
1. Additional VREF positions can be achieved via I2C-bus bits VCTR1 and VCTR0 (see Fig.9).
2. The numbers given in parenthesis refer to CCIR line counting.
Table 29 Fine position of HS HDEL0 and HDEL1 SA 10
CONTROL BITS D5 and D4
FINE POSITION OF HS WITH A STEP SIZE
OF 2/LLC
HDEL1
HDEL0
0
0
0
1
0
1
2
1
0
3
1
1
Table 30 Output format selection OFTS0 and OFTS1 SA 10
CONTROL BITS D7 and D6
FORMATS
OFTS1
OFTS0
RGB (5, 6 and 5), RGB (8, 8 and 8)
(dependent on control bit RGB888); see
Table 32
0
0
YUV 422 16 bits
0
1
YUV 411 12 bits
1
0
YUV CCIR-656 8 bits
1
1
1998 May 15
51
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.16 SUBADDRESS 11
Table 31 Output control 1 SA 11
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
Colour on (COLO)
Automatic colour killer
COLO
0
D0
Colour forced on
COLO
1
D0
DMSD data to YUV output
VIPB
0
D1
ADC data to YUV output; dependent on mode settings
VIPB
1
D1
HS, HREF, VREF and VS high-impedance inputs
OEHV
0
D2
Outputs HS, HREF, VREF and VS active
OEHV
1
D2
VPO-bus high-impedance inputs
OEYC
0
D3
Output VPO-bus active
OEYC
1
D3
VREF is vertical reference
COMPO
0
D4
VREF is inverse composite blank
COMPO
1
D4
FEI sampling at CREF = LOW
(SAA7110 compatible); (see Fig.19)
FECO
0
D5
FEI sampling at CREF = HIGH
FECO
1
D5
Decoder VIP bypassed (VIPB)
Output enable horizontal/vertical sync (OEHV)
Output enable YUV data (OEYC)
Inverse composite blank (COMPO)
FEI control (FECO)
Compatibility to SAA7199 (CM99)
Default value
CM99
0
D6
To be set if SAA7199 (digital encoder) is used for
re-encoding in conjunction with RTCO
CM99
1
D6
General purpose switch (GPSW)
Switches directly pin 64 GPSW
1998 May 15
52
GPSW
0
D7
GPSW
1
D7
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.17 SUBADDRESS 12
Table 32 Output control 2 SA 12, D7 to D6, D4 to D0
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
Analog test select (AOSL)
AOUT connected to internal test point 1
AOUT connected to input AD1
AOUT connected to input AD2
AOUT connected to internal test point 2
AOSL1
0
D1
AOSL0
0
D0
AOSL1
0
D1
AOSL0
1
D0
AOSL1
1
D1
AOSL0
0
D0
AOSL1
1
D1
AOSL0
1
D0
Dithering off
DIT
0
D2
Dithering on
DIT
1
D2
RGB (5, 6 and 5)
RGB888
0
D3
RGB (8, 8 and 8)
RGB888
1
D3
Dithering (noise shaping) control (DIT)
RGB output format selection (RGB888)
Chrominance interpolation filter function (CBR)
Cubic interpolation (default)
CBR
0
D4
Linear interpolation (lower bandwidth)
CBR
1
D4
VPO7 to VPO0 depends on OEYC, FEI only (default)
(see Figs 18, 19 and 22)
TCLO
0
D5
VPO7 to VPO0 in 3-state [and OFTS (1 : 0) = 3]
(see Tables 3 and 6)
TCLO
1
D5
ODD switched to output pin 40
RTSE0
0
D6
VL switched to output pin 40
RTSE0
1
D6
3-state control VPO7 to VPO0 (TCLO)
Real time outputs mode select (RTSE0)
Real time outputs mode select (RTSE1)
PLIN switched to output pin 39
RTSE1
0
D7
HL switched to output pin 39
RTSE1
1
D7
1998 May 15
53
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.18 SUBADDRESS 13
Table 33 Output control 3 SA 13
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
BCLO1
0
D1
BCLO0
0
D0
BCLO1
0
D1
BCLO0
1
D0
BCLO1
1
D1
BCLO0
0
D0
Bypass control LOW for VPO7 to VPO0
No bypass
Permanent bypass
Bypass controlled by V_GATE
Bypass controlled by delayed V_GATE
BCLO1
1
D1
BCLO0
1
D0
BCHI1
0
D3
BCHI0
0
D2
BCHI1
0
D3
BCHI0
1
D2
Bypass control HIGH for VPO15 to VPO8
No bypass
Permanent bypass
Bypass controlled by V_GATE
Bypass controlled by delayed V_GATE
BCHI1
1
D3
BCHI0
0
D2
BCHI1
1
D3
BCHI0
1
D2
CCTR1
0
D5
CCTR0
0
D4
CCTR1
0
D5
CCTR0
1
D4
CCTR1
1
D5
CCTR0
0
D4
CCTR1
1
D5
CCTR0
1
D4
VCTR1
0
D7
VCTR0
0
D6
VCTR1
0
D7
VCTR0
1
D6
Clock Reference Output Control
CREF is independent of VREF
CREF is LOW if VREF = 0
CREF is HIGH if VREF = 0
CREF always = 1
Vertical Reference Output Control (VREF)
Internal VREF
VREF_CCIR
Programmable V_GATE
Delayed programmable V_GATE
1998 May 15
54
VCTR1
1
D7
VCTR0
0
D6
VCTR1
1
D7
VCTR0
1
D6
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FIELD
50 Hz
60 Hz
FRAME
LINE(2)
COUNTING
1st
1
2nd
314
1st
2
2nd
315
1st
312
2nd
625
1st
1 (4)
2nd
264 (267)
1st
2 (5)
55
2nd
265 (268)
1st
262 (265)
2nd
525 (3)
DECIMA
L VALUE
MSB
(SA 17,
D0)
CONTROL BITS D7 to D0
VSTA8
VSTA7
VSTA6
VSTA5
VSTA4
VSTA3
VSTA2
VSTA1
VSTA0
312
1
0
0
1
1
1
0
0
0
0....
0
0
0
0
0
0
0
0
0
....310
1
0
0
1
1
0
1
1
1
262
1
0
0
0
0
0
1
1
0
0....
0
0
0
0
0
0
0
0
0
....260
1
0
0
0
0
0
1
0
1
Philips Semiconductors
Table 34 Start of decoded data on VPO-port SA 15; note 1
Enhanced Video Input Processor (EVIP)
1998 May 15
17.2.19 SUBADDRESS 15
Notes
1. Start of decoded data on VPO-port (end of bypassed region; start of VREF if selected by VCTR1 and VCTR0; see Figs 8 and 10).
2. Line numbers in brackets refer to CCIR line counting.
Product specification
SAA7111A
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FIELD
50 Hz
60 Hz
MSB
DECIMAL (SA 17, D0)
VALUE
VSTO8
FRAME
LINE(2)
COUNTING
1st
1
2nd
314
1st
2
2nd
315
1st
312
2nd
625
1st
1 (4)
2nd
264 (267)
1st
2 (5)
56
2nd
265 (268)
1st
262 (265)
2nd
525 (3)
CONTROL BITS D7 to D0
VSTO7
VSTO6
VSTO5
VSTO4
VSTO3
VSTO2
VSTO1
VSTO0
312
1
0
0
1
1
1
0
0
0
0....
0
0
0
0
0
0
0
0
0
....310
1
0
0
1
1
0
1
1
1
262
1
0
0
0
0
0
1
1
0
0....
0
0
0
0
0
0
0
0
0
....260
1
0
0
0
0
0
1
0
1
Philips Semiconductors
TABLE 35 STOP OF DECODED DATA ON VPO-PORT SA 16; NOTE 1
Enhanced Video Input Processor (EVIP)
1998 May 15
17.2.20 SUBADDRESS 16
NOTES
1. STOP OF DECODED DATA ON VPO-PORT (BEGIN OF BYPASSED REGION; STOP OF VREF IF SELECTED BY VCTR1 AND VCTR0; SEE FIGS 8 AND 10).
2. LINE NUMBERS IN BRACKETS REFER TO CCIR LINE COUNTING.
17.2.21 SUBADDRESS 17
Table 36 Sign bits of the VBI-data stream control
FUNCTION
BIT NAME
LOGIC LEVEL
CONTROL BIT
VSTA8
see Table 34
D0
VSTO8
see Table 35
D1
VBI-data stream start (VSTA8); see SA 15
Sign bit VBI-data stream start
Product specification
Sign bit VBI-data stream stop
SAA7111A
VBI-data stream stop (VSTO8); see SA 16
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
17.2.22 SUBADDRESS 1A (READ-ONLY REGISTER)
Table 37 Line-21 text slicer status SA 1A, D3 to D0
I2C-BUS
STATUS BIT
NAME
FUNCTION
STATUS BIT
F1RDY
new data on field 1 has been acquired (for asynchronous reading); active HIGH
D0
F1VAL
line-21 of field 1 carries valid data; active HIGH
D1
F2RDY
new data on field 2 has been acquired (for asynchronous reading); active HIGH
D2
F2VAL
line-21 of field 2 carries valid data; active HIGH
D3
17.2.23 SUBADDRESS 1B (READ-ONLY REGISTER)
Table 38 First decoded data byte of the text slicer SA 1B
I2C-BUS
TEXT DATA
BITS
BYTE1 (6 to 0)
P1
FUNCTION
data bit 6 to 0 of first data byte
DATA BITS
D6 to D0
parity error flag bit; bit goes HIGH when a parity error has occurred
D7
17.2.24 SUBADDRESS 1C (READ-ONLY REGISTER)
Table 39 Second decoded data byte of the text slicer SA 1C
I2C-BUS
TEXT DATA
BITS
BYTE2 (6 to 0)
P2
FUNCTION
data bit 6 to 0 of second data byte
DATA BITS
D6 to D0
parity error flag bit; bit goes HIGH when a parity error has occurred
D7
17.2.25 SUBADDRESS 1F (READ-ONLY REGISTER)
Table 40 Status byte SA 1F
I2C-BUS
STATUS BIT
NAME
FUNCTION
STATUS BIT
CODE
colour signal in accordance with selected standard has been detected; active
HIGH
SLTCA
slow time constant active in WIPA-mode; active HIGH
D1
white peak loop is activated; active HIGH
D2
gain value for active luminance channel is limited [min (bottom)]; active HIGH
D3
WIPA
GLIMB
D0
GLIMT
gain value for active luminance channel is limited [max (top)]; active HIGH
D4
FIDT
identification bit for detected field frequency; LOW = 50 Hz, HIGH = 60 Hz
D5
HLCK
status bit for locked horizontal frequency; LOW = locked, HIGH = unlocked
D6
STTC
status bit for horizontal phase loop; LOW = TV time-constant,
HIGH = VTR time-constant
D7
1998 May 15
57
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
18 FILTER CURVES
18.1
Anti-alias filter curve
MGD138
6
handbook, full pagewidth
V
(dB)
0
−6
−12
−18
−24
−30
−36
−42
0
2
4
6
8
10
12
f (MHz)
14
Fig.41 Anti-alias filter.
18.2
TUF-block filter curve
MGG067
6
V full pagewidth
handbook,
(dB)
0
−6
−12
−18
−24
−30
−36
−42
−48
−54
0
2
4
6
8
10
Fig.42 Interpolation filter for the upsampled CVBS-signal.
1998 May 15
58
12
f (MHz)
14
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
18.3
SAA7111A
Luminance filter curves
MGD139
18
handbook, full pagewidth
VY
(dB)
(1)
(2)
(4)
(3)
6
−6
(1)
(2)
(4)
(3)
−18
−30
0
2
4
6
(1) = 43H; (2) = 53H; (3) = 63H; (4) = 73H.
fY (MHz)
8
Fig.43 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter on, different aperture bandpass centre
frequencies.
MGD140
18
handbook, full pagewidth
VY
(dB)
6
(1)
(2)
(3)
(4)
−6
(4)
(3)
(2)
(1)
−18
−30
0
2
4
6
fY (MHz)
8
(1) = 40H; (2) = 41H; (3) = 42H; (4) = 43H.
Fig.44 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter on, different aperture factors.
1998 May 15
59
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
MGD141
18
handbook, full pagewidth
VY
(dB)
6
(1)
(2)
(4)
(3)
−6
(1)
(2)
(4)
(3)
−18
−30
0
2
4
6
fY (MHz)
8
(1) = 03H; (2) = 13H; (3) = 23H; (4) = 33H.
Fig.45 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter off, different aperture band-pass centre
frequencies.
MGD142
18
handbook, full pagewidth
VY
(dB)
(1)
(2)
(3)
(4)
6
−6
−18
−30
0
2
4
6
fY (MHz)
(1) = C0H; (2) = C1H; (3) = C2H; (4) = C3H.
Fig.46 Luminance control SA 09H, Y/C mode, prefilter on, different aperture factors.
1998 May 15
60
8
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
MGD143
18
handbook, full pagewidth
VY
(dB)
6
(1)
(2)
(3)
(4)
−6
−18
−30
0
2
4
6
fY (MHz)
8
(1) = 80H; (2) = 81H; (3) = 82H; (4) = 83H.
Fig.47 Luminance control SA 09H, Y/C mode, prefilter off, different aperture factors.
MGD144
18
handbook, full pagewidth
VY
(dB)
(1)
(2)
(4)
(3)
6
(1)
(2)
(4)
(3)
−6
−18
−30
0
2
4
6
8
f
Y (MHz)
(1) = 43H; (2) = 53H; (3) = 63H; (4) = 73H.
Fig.48 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter on, different aperture band-pass centre
frequencies.
1998 May 15
61
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
MGD145
18
handbook, full pagewidth
VY
(dB)
6
(1)
(2)
(3)
(4)
(4)
(3)
(2)
(1)
−6
−18
−30
0
2
4
6
fY (MHz)
8
(1) = 40H; (2) = 41H; (3) = 42H; (4) = 43H.
Fig.49 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter on, different aperture factors.
MGD146
18
handbook, full pagewidth
VY
(dB)
6
(1)
(2)
(4)
(3)
−6
(1)
(2)
(4)
(3)
−18
−30
0
2
4
6
8
f
Y (MHz)
(1) = 03H; (2) = 13H; (3) = 23H; (4) = 33H.
Fig.50 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter off, different aperture band-pass centre
frequencies.
1998 May 15
62
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
18.4
SAA7111A
Chrominance filter curves
MGD147
6
handbook,
V full pagewidth
(dB)
0
−6
(1)
(2)
(3)
(4)
−12
−18
−24
−30
(4)
(1)
(3)
(2)
−36
−42
−48
−54
0
0.54
1.08
1.62
2,16
f(MHz)
(1) Transfer characteristics of the chrominance low-pass dependent on CHBW[1 : 0] settings. CHBW [1 : 0] = 00; (2) CHBW [1 : 0] = 01; (3)
CHBW [1 : 0] = 10; (4) CHBW [1 : 0] = 11.
Fig.51 Chrominance filter.
19 I2C-BUS START SET-UP
• The given values force the following behaviour of the SAA7111A:
– The analog input AI11 expects a signal in CVBS format; analog anti-alias filter active
– Automatic field detection
– YUV 4 : 2 : 2 16-bit output format enabled
– Outputs HS, HREF, VREF and VS active
– Contrast, brightness and saturation control in accordance with CCIR standards
– Chrominance processing with nominal bandwidth (800 kHz).
1998 May 15
63
2.7
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
Table 41 I2C-bus start set-up values
SUB
(HEX)
00
01
02
NAME(1)
FUNCTION
chip version
reserved
analog input control 1
ID07 to ID00; see Table 9
VALUES (BIN)
7
6
5
4
3
2
(HEX)
1
read only
0 0 0 0
0 0 0 0
0
0 0 0
0
FUSE1 and FUSE0, GUDL2 to GUDL0,
1 1 0
0
MODE2 to MODE0
03
analog input control 2
X, HLNRS, VBSL, WPOFF, HOLDG,
0 0 1 0 0 0 1 1
GAFIX, GAI28 and GAI18
04
analog input control 3
GAI17 to GAI10
0 0 0 0 0 0 0 0
05
analog input control 4
GAI27 to GAI20
0 0 0 0 0 0 0 0
06
horizontal sync start
HSB7 to HSB0
1 1 1 0 1 0 1 1
07
horizontal sync stop
HSS7 to HSS0
1 1 1 0 0 0 0 0
08
sync control
AUFD, FSEL, EXFIL, X, VTRC, HPLL,
1 0 0 0 1 0 0 0
VNOI1 and VNOI0
09
luminance control
BYPS, PREF, BPSS1 and BPSS0, VBLB, 0 0 0 0 0 0 0 1
UPTCV, APER1 and APER0
0A
luminance brightness
BRIG7 to BRIG0
1 0 0 0 0 0 0 0
0B
luminance contrast
CONT7 to CONT0
0 1 0 0 0 1 1 1
0C
chrominance saturation SATN7 to SATN0
0 1 0 0 0 0 0 0
0D
chroma hue control
HUEC7 to HUEC0
0 0 0 0 0 0 0 0
0E
chrominance control
CDTO, CSTD2 to CSTD0, DCCF, FCTC, 0 0 0 0 0 0 0 1
CHBW1 and CHBW0
0F
reserved
0 0 0 0 0 0 0 0
10
format/delay control
OFTS1 and OFTS0, HDEL1 and HDEL0, 0 1 0 0 0 0 0 0
VRLN, YDEL2 to YDEL0
11
output control 1
GPSW, CM99, FECO, COMPO, OEYC,
0 0 0 1 1 1 0 0
OEHV, VIPB, and COLO
12
output control 2
RTSE1 and RTSE0, TCLO, CBR,
0 0 0 0 0 0 0 1
RGB888 DIT, AOSL1 and AOSL0
13
output control 3
CCTR1 and CCTR0, BCHI1 and BCHI0, 0 0 0 0 0 0 0 0
BCLO1 and BCLO0, VCTR1 and VCTR0
14
reserved
0 0 0 0 0 0 0 0
15
VBI-data stream start
VSTA7 to VSTA0
0 0 0 0 0 0 0 0
16
VBI-data stream stop
VSTO7 to VSTO0
0 0 0 0 0 0 0 0
17
MSBs for VBI control
X, X, X, X, X, X, VSTO8, and VSTA8
0 0 0 0 0 0 0 0
18-19 reserved
0 0 0 0 0 0 0 0
1A
text slicer status
0, 0, 0, 0, F2VAL, F2RDY,
read only register
F1VAL, and F1RDY
1B
decoded bytes of the
P1, BYTE1 (6 to 0)
text slicer
1C
P2, BYTE2 (6 to 0)
1D-1E reserved
0 0 0 0 0 0 0 0
1F
status byte
STTC, HLCK, FIDT, GLIMT, GLIMB,
read only register
WIPA, SLTCA and CODE
Note
1. All X values must be set to LOW.
1998 May 15
64
START
00
C0
33
00
00
EB
E0
88
01
80
47
40
00
01
00
40
1C
00
00
00
00
00
00
00
00
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
20 PACKAGE OUTLINES
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
c
y
X
A
48
33
49
32
ZE
e
E HE
A
A2
(A 3)
A1
wM
θ
bp
pin 1 index
64
Lp
L
17
detail X
16
1
ZD
e
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
10.1
9.9
10.1
9.9
0.5
HD
HE
12.15 12.15
11.85 11.85
L
Lp
v
w
y
1.0
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
1.45
1.05
7
0o
1.45
1.05
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-12-19
97-08-01
SOT314-2
1998 May 15
EUROPEAN
PROJECTION
65
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm
SOT393-1
c
y
X
A
48
33
49
32
ZE
e
E HE
A
A2
(A 3)
A1
θ
wM
Lp
bp
pin 1 index
L
17
64
detail X
16
1
w M
bp
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
3.00
0.25
0.10
2.75
2.55
0.25
0.45
0.30
0.23
0.13
14.1
13.9
14.1
13.9
0.8
HD
HE
L
17.45 17.45
1.60
16.95 16.95
Lp
v
w
y
1.03
0.73
0.16
0.16
0.10
Z D (1) Z E (1)
1.2
0.8
1.2
0.8
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT393-1
1998 May 15
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
96-05-21
97-08-04
MS-022
66
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
If wave soldering cannot be avoided, for LQFP and
QFP packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
21 SOLDERING
21.1
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
21.2
Reflow soldering
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering techniques are suitable for all LQFP and
QFP packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
21.4
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
Wave soldering
Wave soldering is not recommended for LQFP and QFP
packages. This is because of the likelihood of solder
bridging due to closely-spaced leads and the possibility of
incomplete solder penetration in multi-lead devices.
CAUTION
Wave soldering is NOT applicable for all LQFP and
QFP packages with a pitch (e) equal or less than
0.5 mm.
1998 May 15
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
21.3
SAA7111A
67
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
SAA7111A
22 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
23 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
24 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 May 15
68
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
NOTES
1998 May 15
69
SAA7111A
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
NOTES
1998 May 15
70
SAA7111A
Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
NOTES
1998 May 15
71
SAA7111A
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For all other countries apply to: Philips Semiconductors,
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
655102/1200/04/pp72
Date of release: 1998 May 15
Document order number:
9397 750 03118