INTEGRATED CIRCUITS DATA SHEET TDA8752 Triple high speed Analog-to-Digital Converter (ADC) Product specification Supersedes data of 1998 Aug 11 File under Integrated Circuits, IC02 1999 Mar 09 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 FEATURES • Triple 8-bit ADC • Sampling rate up to 100 MHz • IC controllable via a serial interface, which can be either I2C-bus or 3-wire, selected via a TTL input pin • IC analog voltage input from 0.4 to 1.2 V (p-p) to produce full-scale ADC input of 1 V (p-p) GENERAL DESCRIPTION The TDA8752 is a triple 8-bit ADC with controllable amplifiers and clamps for the digitizing of large bandwidth RGB signals. • 3 clamps for programming a clamping code between −63.5 and +64 in steps of 1⁄2LSB • 3 controllable amplifiers: gain controlled via the serial interface to produce a full scale resolution of 1⁄2LSB peak-to-peak The clamp level, the gain and all of the other settings are controlled via a serial interface (either I2C-bus or 3-wire serial bus, selected via a logic input). • Amplifier bandwidth of 250 MHz The IC also includes a PLL that can be locked on the horizontal line frequency and generates the ADC clock. The PLL jitter is minimized for high resolution PC graphics applications. An external clock can also be input to the ADC. • Low gain variation with temperature • PLL, controllable via the serial interface to generate the ADC clock, which can be locked to a line frequency from 15 to 280 kHz • Integrated PLL divider It is possible to set the TDA8752 serial bus address between four fixed values, in the event that several TDA8752 ICs are used in a system, using the I2C-bus interface (for example, two ICs used in an odd/even configuration). • Programmable phase clock adjustment cells • Internal voltage regulators • TTL compatible digital inputs and outputs • Chip enable high-impedance ADC output • Power-down mode • Possibility to use up to four ICs in the same system, using the I2C-bus interface, or more, using the 3-wire serial interface • 1 W power dissipation. APPLICATIONS • R, G and B high speed digitizing • LCD panels drive • LCD projection systems • VGA and higher resolutions • Using two ICs in parallel, higher display resolution can be obtained; 200 MHz pixel frequency. ORDERING INFORMATION TYPE NUMBER TDA8752H/6 TDA8752H/8 1999 Mar 09 PACKAGE NAME DESCRIPTION plastic quad flat package; 100 leads (lead length 1.95 mm); QFP100 body 14 × 20 × 2.8 mm 2 VERSION SOT317-2 SAMPLING FREQUENCY (MHz) 60 100 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage for R, G and B channels 4.75 5.0 5.25 V VDDD logic supply voltage for I2C-bus and 3-wire 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage 4.75 5.0 5.25 V VCCA(PLL) analog PLL supply voltage 4.75 5.0 5.25 V VCCO(PLL) output PLL supply voltage 4.75 5.0 5.25 V ICCA analog supply current − 120 − mA − 1.0 − mA − 40 − mA − 6 − mA for R, G and B channels I2C-bus IDDD logic supply current ICCD digital supply current ICCO output stages supply current ICCA(PLL) analog PLL supply current − 28 − mA ICCO(PLL) output PLL supply current − 5 − mA fCLK maximum clock frequency TDA8752/6 60 − − MHz TDA8752/8 100 − − MHz fref(PLL) PLL reference clock frequency 15 − 280 kHz fVCO VCO output clock frequency 12 − 100 MHz INL DC integral non linearity from analog input to digital output; full-scale; ramp input; fCLK = 100 MHz − ±0.5 ±1.5 LSB DNL DC differential non linearity from analog input to digital output; full-scale; ramp input; fCLK = 100 MHz − ±0.5 ±1.0 LSB ∆Gamp/T amplifier gain stability as a function of temperature Vref = 2.5 V with 100 ppm/°C maximum − − 200 ppm/°C B amplifier bandwidth −3 dB; Tamb = 25 °C 250 − − MHz tset settling time of the ADC block plus AGC input signal settling − time < 1 ns; Tamb = 25 °C − 6 ns DRPLL PLL divider ratio 100 − 4095 Ptot total power consumption fCLK = 100 MHz; ramp input − 1.0 − W jPLL(rms) maximum PLL phase jitter (RMS value) fref = 66.67 kHz; fCLK = 100 MHz − 0.3 − ns 1999 Mar 09 for and 3-wire fCLK = 100 MHz; ramp input 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... RAGC RGAINC RIN RDEC Vref GAGC GGAINC GIN GDEC BAGC 4 BGAINC BIN BDEC TDO TCK ADD2 ADD1 SEN SCL SDA DIS 27 40 79 69 VCCD 59 VCCO(PLL) AGNDR 95 99 85 89 13 VSSD AGNDB 21 29 OGNDG AGNDPLL OGNDR 41 DGND OGNDB OGNDPLL 70 60 48 96 82 86 6 9 8 7 12 RBOT 71 to 78 CLAMP 10 RCLP R0 to R7 MUX OUTPUTS 45 ADC 3 ROR RED CHANNEL 14 17 16 15 20 61 to 68 46 22 87 25 24 23 28 49, 52 to 58 BLUE CHANNEL 26 GBOT G0 to G7 GREEN CHANNEL 18 GCLP 47 GOR OE BCLP BBOT B0 to B7 BOR 36 84 35 HSYNCI 34 33 TDA8752 81 SERIAL INTERFACE I2C-BUS OR 3-WIRE 38 42 39 83 80 REGULATOR 92 PLL 37 I2C-bus; 1-bit 91 32 (H level) 93 94 90 4 2 88 97 98 MGG363 n.c. HSYNC DEC1 DEC2 PWDWN Fig.1 Block diagram. CP CZ CKBO CKAO CKREFO CKEXT INV COAST CKREF TDA8752 1, 5, 30, 31, 43 , 44 50, 51, 100 CKADCO Product specification I2C/3W 19 VCCOG AGNDG CLP Philips Semiconductors 11 VDDD VCCOB VCCA(PLL) Triple high speed Analog-to-Digital Converter (ADC) VCCAG VCCOR BLOCK DIAGRAM VCCAB book, full pagewidth 1999 Mar 09 VCCAR Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) CLP TDA8752 RAGC CLKADC handbook, full pagewidth RCLP CLAMP CONTROL VP RIN DAC 150 kΩ 8 MUX Vref ADC AGC 3 kΩ REGISTER ROR I2C-bus; 8 bits (Or) VCCAR OUTPUTS 45 kΩ 8 R0 to R7 8 DAC D≥R 1 5 D OE R 8 RBOT 7 REGISTER FINE GAIN ADJUST 1 I2C-bus; 5 bits (Fr) REGISTER COARSE GAIN ADJUST I2C-bus; 7 bits (Cr) SERIAL I2C-BUS MGG364 HSYNCI RGAINC Fig.2 Red channel diagram. 1999 Mar 09 5 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) Cp Cz handbook, full pagewidth TDA8752 COAST CZ CKEXT INV MUX 0°/180° CP I2C-bus; 1 bit (V level) CKREF PHASE FREQUENCY edge selector DETECTOR I2C-bus; 1 bit I2C-bus; 5 bits (edge) (Ip, Up, Do) 12 to 100 MHz loop filter I2C-bus; 3 bits (Z) VCO I2C-bus; phase selector A 2 bits (VCO) I2C-bus; I2C-bus; 5 bits (Pa) 1 bit (Cka) CKADCO CLK ADC CKBO DIV N (100 to 4095) I2C-bus; 12 bits (Di) I2C-bus; 1 bit (Ckb) phase selector B I2C-bus; 5 bits (Pb) CKAO SYNCHRO CKREFO MGG370 Fig.3 PLL diagram. 1999 Mar 09 6 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 PINNING SYMBOL PIN DESCRIPTION n.c. 1 not connected DEC2 2 main regulator decoupling input Vref 3 gain stabilizer voltage reference input DEC1 4 main regulator decoupling input n.c. 5 not connected RAGC 6 red channel AGC output RBOT 7 red channel ladder decoupling input (BOT) RGAINC 8 red channel gain capacitor input RCLP 9 red channel gain clamp capacitor input RDEC 10 red channel gain regulator decoupling input VCCAR 11 red channel gain analog power supply RIN 12 red channel gain analog input AGNDR 13 red channel gain analog ground GAGC 14 green channel AGC output GBOT 15 green channel ladder decoupling input (BOT) GGAINC 16 green channel gain capacitor input GCLP 17 green channel gain clamp capacitor input GDEC 18 green channel gain regulator decoupling input VCCAG 19 green channel gain analog power supply GIN 20 green channel gain analog input AGNDG 21 green channel gain analog ground BAGC 22 blue channel AGC output BBOT 23 blue channel ladder decoupling input (BOT) BGAINC 24 blue channel gain capacitor input BCLP 25 blue channel gain clamp capacitor input BDEC 26 blue channel gain regulator decoupling input VCCAB 27 blue channel gain analog power supply BIN 28 blue channel gain analog input AGNDB 29 blue channel gain analog ground n.c. 30 not connected n.c. 31 not connected I2C/3W 32 selection input between I2C-bus (active HIGH) and 3-wire serial bus (active LOW) ADD1 33 I2C-bus address control input 1 ADD2 34 I2C-bus address control input 2 TCK 35 scan test mode (active HIGH) 1999 Mar 09 7 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 SYMBOL PIN TDO 36 scan test output DIS 37 I2C and 3W disable control input (disable at HIGH level) SEN 38 select enable for 3-wire serial bus input (see Fig.10) SDA 39 I2C/3W serial data input VDDD 40 logic I2C/3W digital power supply VSSD 41 logic I2C/3W digital ground SCL 42 I2C/3W serial clock input n.c. 43 not connected n.c. 44 not connected ROR 45 red channel ADC output bit out of range GOR 46 green channel ADC output bit out of range BOR 47 blue channel ADC output bit out of range OGNDB 48 blue channel ADC output ground B0 49 blue channel ADC output bit 0 (LSB) n.c. 50 not connected n.c. 51 not connected B1 52 blue channel ADC output bit 1 B2 53 blue channel ADC output bit 2 B3 54 blue channel ADC output bit 3 B4 55 blue channel ADC output bit 4 B5 56 blue channel ADC output bit 5 B6 57 blue channel ADC output bit 6 B7 58 blue channel ADC output bit 7 (MSB) VCCOB 59 blue channel ADC output power supply OGNDG 60 green channel ADC output ground G0 61 green channel ADC output bit 0 (LSB) G1 62 green channel ADC output bit 1 G2 63 green channel ADC output bit 2 G3 64 green channel ADC output bit 3 G4 65 green channel ADC output bit 4 G5 66 green channel ADC output bit 5 G6 67 green channel ADC output bit 6 G7 68 green channel ADC output bit 7 (MSB) VCCOG 69 green channel ADC output power supply OGNDR 70 red channel ADC output ground R0 71 red channel ADC output bit 0 (LSB) 1999 Mar 09 DESCRIPTION 8 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 SYMBOL PIN R1 72 red channel ADC output bit 1 R2 73 red channel ADC output bit 2 R3 74 red channel ADC output bit 3 R4 75 red channel ADC output bit 4 R5 76 red channel ADC output bit 5 R6 77 red channel ADC output bit 6 R7 78 red channel ADC output bit 7 (MSB) VCCOR 79 red channel ADC output power supply CKREFO 80 reference output clock resynchronized horizontal pulse CKAO 81 PLL clock output 3 (in phase with reference output clock) OGNDPLL 82 PLL digital ground CKBO 83 PLL clock output 2 CKADCO 84 PLL clock output 1 (in phase with internal ADC clock) VCCO(PLL) 85 PLL output power supply DGND 86 digital ground OE 87 output enable not (when OE is HIGH, the outputs are in high-impedance) PWDWN 88 power-down control input (IC is in power-down mode when this pin is HIGH) CLP 89 clamp pulse input (clamp active HIGH) HSYNC 90 horizontal synchronization input pulse INV 91 PLL clock output inverter command input (invert when HIGH) CKEXT 92 external clock input COAST 93 PLL coast command input CKREF 94 PLL reference clock input VCCD 95 digital power supply AGNDPLL 96 PLL analog ground CP 97 PLL filter input CZ 98 PLL filter input VCCAPLL 99 PLL analog power supply n.c. 100 not connected 1999 Mar 09 DESCRIPTION 9 Philips Semiconductors Product specification 81 CKAO 82 OGNDPLL 83 CKBO 84 CKADCO 85 VCCO(PLL) n.c. 1 80 CKREFO DEC2 2 79 VCCOR Vref 3 78 R7 DEC1 4 77 R6 n.c. 5 76 R5 RAGC 6 75 R4 RBOT 7 74 R3 RGAINC 8 73 R2 RCLP 9 72 R1 RDEC 10 71 R0 VCCAR 11 70 OGNDR RIN 12 69 VCCOG AGNDR 13 68 G7 GAGC 14 67 G6 GBOT 15 66 G5 65 G4 GCLP 17 64 G3 GDEC 18 63 G2 VCCAG 19 62 G1 GIN 20 61 G0 AGNDG 21 60 OGNDG BAGC 22 59 VCCOB TDA8752 GGAINC 16 10 n.c. 50 B0 49 OGNDB 48 BOR 47 GOR 46 n.c. n.c. 44 B1 51 ROR 45 52 n.c. 30 n.c. 43 AGNDB 29 SCL 42 B2 VSSD 41 53 VDDD 40 B3 BIN 28 SDA 39 54 DIS 37 B4 VCCAB 27 SEN 38 55 TDO 36 B5 BDEC 26 TCK 35 56 ADD2 34 B6 BCLP 25 ADD1 33 B7 57 n.c. 31 58 I2C/3W 32 BBOT 23 BGAINC 24 Fig.4 Pin configuration. 1999 Mar 09 86 DGND 87 OE 88 PWDWN 89 CLP 90 HSYNC 91 INV TDA8752 92 CKEXT 93 COAST 94 CKREF 95 VCCD 96 AGNDPLL 97 CP 98 CZ 100 n.c. handbook, full pagewidth 99 VCCA(PLL) Triple high speed Analog-to-Digital Converter (ADC) MGG362 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 The output of the multiplexer is either the normal video signal or the 0.156 V reference signal (during HSYNC). FUNCTIONAL DESCRIPTION This triple high-speed 8-bit ADC is designed to convert RGB signals, from a PC or work station, into data used by a LCD driver (pixel clock up to 200 MHz, using 2 ICs). The corresponding ADC outputs are then compared to a pre-set value loaded in a register. Depending on the result of the comparison, the gain of the variable gain amplifiers is adjusted (coarse gain control; see Figs 2 and 8). The three 7-bit registers receive data via a serial interface to enable the gain to be programmed. IC analog video inputs The video inputs are internally DC polarized. These inputs are AC coupled externally. The pre-set value loaded in the 7-bit register is chosen between approximately 67 codes to ensure the full-scale input range (see Fig.8). A contrast control can be achieved using these registers. In this case care should be taken to stay within the allowed code range (32 to 99). Clamps Three independent parallel clamping circuits are used to clamp the video input signals on the black level and to control the brightness level. The clamping code is programmable between code −63.5 and +64 in steps of 1⁄ LSB. The programming of the clamp value is achieved 2 via an 8-bit DAC. Each clamp must be able to correct an offset from ±0.1 V to ±10 mV within 300 ns, and correct the total offset in 10 lines. A fine correction using three 5-bit DACs, also controlled via the serial interface, is used to finely tune the gain of the three channels (fine gain control; see Figs 2 and 9) and to compensate the channel-to-channel gain mismatch. With a full scale ADC input, the resolution of the fine register corresponds to 1⁄2LSB peak-to-peak variation. The clamps are controlled by an external TTL positive going pulse (pin CLP). The drop of the video signal is <1 LSB. Normally, the circuit operates with a 0 code clamp, corresponding to the 0 ADC code. This clamp code can be changed from −63.5 to +64 as represented in Fig.7, in steps of 1⁄2LSB. The digitized video signal is always between code 0 and code 255 of the ADC. To use these gain controls correctly, it is recommended to fix the coarse gain (to have a full-scale ADC input signal) to within 4LSB and then adjust it with the fine gain. The gain is adjusted during HSYNC. During this time the output signal is not related to the amplified input signal. The outputs, when the coarse gain system is stable, is related to the programmed coarse code (see Fig.8). Variable gain amplifier ADCs Three independent variable gain amplifiers are used to provide, to each channel, a full-scale input range signal to the 8-bit ADC. The gain adjustment range is designed so that, for an input range varying from 0.4 to 1.2 V (p-p), the output signal corresponds to the ADC full-scale input of 1 V (p-p). The ADCs are 8-bit with a maximum clock frequency of 100 Msps. The ADCs input range is 1 V (p-p) full-scale. One out of range bit exists per channel (ROR, GOR and BOR). It will be at logic 1 when the signal is out of range of the full scale of the ADCs. Pipeline delay in the ADCs is 1 clock cycle from sampling to data output. To ensure that the gain does not vary over the whole operating temperature range, an external reference of +2.5 V DC, (Vref with a 100 ppm/°C maximum variation) supplied externally, is used to calibrate the gain at the beginning of each video line before the clamp pulse using the following principle. The ADCs reference ladders regulators are integrated. ADC outputs ADC outputs are straight binary. An output enable pin (OE; active LOW) enables the output status between active and high-impedance (OE = HIGH) to be switched; it is recommended to load the outputs with a 10 pF capacitive load. The timing must be checked very carefully if the capacitive load is more than 10 pF. A differential of 0.156 V (p-p) (1⁄16Vref) reference signal is generated internally from the reference voltage (Vref). During the synchronization part of the video line, the multiplexer, controlled by the TTL synchronization signal (HSYNCI, coming from HSYNC; see Fig.1) with a width equal to one of the video synchronization signals (e.g. signal coming from a synchronization separator), is switched between the two amplifiers. 1999 Mar 09 11 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 1 fn 1 f z = ------------------------------ and ξ = --- × ---- 2 fz 2π × R × C z Phase-locked loop The ADCs are clocked either by an internal PLL locked to the CKREF clock, (all of the PLL is on-chip except the loop filter capacitance) or an external clock, CKEXT. Selection is performed via the serial interface bus. Where: fz = loop filter zero frequency R = the chosen resistance for the filter The reference clock (CKREF) range is between 15 and 280 kHz. Consequently, the VCO minimum frequency is 12 MHz and the maximum frequency 100 MHz for the TDA8752/8 and 60 MHz for the TDA8752/6. The gain of the VCO part can be controlled via the serial interface, depending on the frequency range to which the PLL is locked. ξ = the damping factor. Different resistances for the filter can be programmed via the serial interface. To have better performances, the PLL parameters should be chosen so that: fn/fref ≅ 0.05 ξ ≅ 1.5. To increase the bandwidth of the PLL, the charge pump current, controlled by the serial interface, must also be increased. The relationship between the frequency and the current is given by the following equation: It is possible to control (independently) the phase of the ADC clock and the phase of an additional clock output (which could be used to drive a second TDA8752). For this, two serial interface-controlled digital phase-shift controllers are included (controlled by 5-bit registers, phase shift controller steps are 11.25° each on the whole PLL frequency range). KO IP 1 f n = ------- ----------------------------------2π ( C z + C P ) N Where: CKREF is resynchronized, by the synchro block, on the CKAO clock. The output is CKREFO (LOW during 8 clock periods). CKAO is the clock at the output of the phase selector A. This clock can be used as the clocks for CKBO and CKADCO. The timing is given in Fig.5. fn = the natural PLL frequency KO = the VCO gain N = the division number Cz and CP = capacitors of the PLL filter. The other PLL equation is as follows: andbook, full pagewidth CKREF CKAO tCKAO CKREFO tCKREFO t phase selector tCKAO = tCLK(buffer) + tphase selector (tCLK(buffer) = 10 ns and tphase selector = ------------------------------- × TCLK(pixel)). 2π tCKREFO = either tCKAO if phase A ≥01000 or tCKAO + TCLK(pixel) if phase A <01000. Fig.5 Timing. 1999 Mar 09 12 MBK773 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 The COAST pin is used to disconnect the PLL phase frequency detector during the frame flyback or the unavailability of the CKREF signal. This signal can normally be derived from the VSYNC signal. b) Using two TDA8752s the PLL of the master TDA8752 is used to drive both ADC clocks. The PLL of the slave TDA8752 is disconnected and the CKBO of the master TDA8752 is connected to pin CKEXT of both TDA8752. The clock output is able to drive an external 10 pF load (for the on-chip ADCs). 2. When an RGB signal is at a pixel frequency exceeding 100 to 200 MHz, it is possible to follow one of the two possibilities given below; The master TDA8752 is used to sample the even pixels and the slave TDA8752 for odd pixels, using a 180° phase shift between the clocks (CKADCO pins). The master chip has its INV pin LOW while the slave chip has its INV pin HIGH, which guarantees the 180° shift ADC clock drive. It is then necessary to adjust phase B of the master chip. Special care should be taken with the quality of the input signal (input setting time). a) Using one TDA8752; the sampling rate can be reduced by a factor of two, by sampling the even pixels in the even frame and the odd pixels in the odd frame. The INV pin is used to toggle between frames. If CKREFO output signal at the master chip is needed, it is possible to use one of the two phase A values in order to avoid set-up and hold problems in the SYNCHRO function; e.g. PHASEA = 100000 and PHASEA = 111111. The PLL can be used in three different methods: 1. The IC can be used as stand-alone with a sampling frequency of up to 100 MHz for the TDA8752/8 and up to 60 MHz for the TDA8752/6. 1999 Mar 09 13 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 handbook, full pagewidth COAST CKEXT INV 12 to 100 MHz MUX phase selector A I2C-bus; I2C-bus; 5 bits (Pa) 1 bit (Cka) (Cka = 1) CKREF PLL CKADCO 0°/180° CLK ADC CKBO phase selector B I2C-bus; 5 bits (Pb) I2C-bus; 1 bit (Ckb) (Ckb = 1) Master TDA8752 (even pixels) CKAO SYNCHRO COAST CKREFO 5V INV CKEXT 12 to 100 MHz CKADCO MUX 0°/180° phase selector A I2C-bus; I2C-bus; 5 bits (Pa) 1 bit (Cka) (Cka = 1) CLK ADC CKBO CKREF PLL phase selector B I2C-bus; 5 bits (Pb) I2C-bus; 1 bit (Ckb) (Ckb = 0) Slave TDA8752 (odd pixels) CKAO SYNCHRO CKREFO MBK772 Slave at 180° phase shift with respect to pin CKADCO of the master TDA8752. Fig.6 Dual TDA8752 solution for pixel clock rate with a single phase adjustment (100 to 200 MHz). 1999 Mar 09 14 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 I2C-bus and 3-wire serial bus interface The I2C-bus and 3-wire serial buses control the status of the different control DACs and registers. Control pin DIS enables or disables the full serial interface function (disable at HIGH level). Four ICs can be used in the same system and programmed by the same bus. Therefore, two pins (ADD1 and ADD2) are available to set each address respectively, for use with the I2C-bus interface. All programming is described in Chapter “I2C-bus and 3-wire interfaces”. 255 handbook, full pagewidth digitized video signal code 64 clamp programming code 0 code −63.5 video signal CLP MGG368 Fig.7 Clamp definition. handbook, full pagewidth Ncoarse ADC output code code 127 coarse register value (67 codes) G(max) 255 G(min) 99 227 32 160 0 128 V 0.2 0.156 = ref 16 0.6 Vi (p-p) 2 MGG366 Fig.8 Coarse gain control. 1999 Mar 09 15 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 ADC output code handbook, full pagewidth GNCOARSE 255 G(max) G(min) 227 coarse register value (67 codes) NCOARSE 160 128 NFINE = 0 NFINE = 31 Vref MGG367 Fig.9 Fine gain correction for a coarse gain GNCOARSE. 1999 Mar 09 16 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... The configuration of the different registers is as follows: Table 1 I2C-bus and 3-wire registers FUNCTION NAME SUB-ADDRESS A7 A6 A5 A4 A3 BIT DEFINITION A2 A1 A0 MSB LSB DEFAULT VALUE SUBADDR − − − − − − − − X X X Mode Sa3 Sa2 Sa1 Sa0 xxx1 0000 OFFSETR X X X X 0 0 0 0 Or7 Or6 Or5 Or4 Or3 Or2 Or1 Or0 0111 1111 COARSER X X X X 0 0 0 1 X Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 x010 0000 FINER X X X X 0 0 1 0 X X X Fr4 Fr3 Fr2 Fr1 Fr0 xxx0 0000 OFFSETG X X X X 0 0 1 1 Og7 Og6 Og5 Og4 Og3 Og2 Og1 Og0 0111 1111 COARSEG X X X X 0 1 0 0 X Cg6 Cg5 Cg4 Cg3 Cg2 Cg1 Cg0 x010 0000 FINEG X X X X 0 1 0 1 X X X Fg4 Fg3 Fg2 Fg1 Fg0 xxx0 0000 OFFSETB X X X X 0 1 1 0 Ob7 Ob6 Ob5 Ob4 Ob3 Ob2 Ob1 Ob0 0111 1111 COARSEB X X X X 0 1 1 1 X Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 x010 0000 17 FINEB X X X X 1 0 0 0 X X X Fb4 Fb3 Fb2 Fb1 Fb0 xxx0 0000 CONTROL X X X X 1 0 0 1 V level H level edge Up Do Ip2 Ip1 Ip0 0000 0100 VCO X X X X 1 0 1 0 Z2 Z1 Z0 Vco1 Vco0 Di11 Di10 Di9 0110 0001 DIVIDER (LSB) X X X X 1 0 1 1 Di8 Di7 Di6 Di5 Di4 Di3 Di2 Di1 1001 0000 PHASEA X X X X 1 1 0 0 X Di0 Cka Pa4 Pa3 Pa2 Pa1 Pa0 x000 0000 PHASEB X X X X 1 1 0 1 X X Ckb Pb4 Pb3 Pb2 Pb1 Pb0 xx00 0000 Philips Semiconductors Register definitions Triple high speed Analog-to-Digital Converter (ADC) 1999 Mar 09 I2C-BUS AND 3-WIRE INTERFACES All the registers are defined by a sub-address of 8 bits; bit A4 refers to the mode which is used with the I2C-bus interface; bits Sa3 to Sa0 are the subaddresses of each register. The bit mode, used only with the I2C-bus, enables two modes to be programmed: TDA8752 • If Mode = 1, all the registers are programmed one after the other by giving this initial condition (xxx1 1111) as the sub-address state; thus, the registers are charged following the predefined sequence of 16 bytes (from sub-address 0000 to 1101). Product specification • If Mode = 0, each register is programmed independently by giving its sub-address and its content Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 Table 3 OFFSET REGISTER This register controls the clamp level for the RGB channels. The relationship between the programming code and the level of the clamp code is given in Table 2. Table 2 NCOARSE GAIN Vi TO BE FULL-SCALE 32 0.825 1.212 99 2.5 0.4 Coding PROGRAMMED CODE CLAMP CODE ADC OUTPUT 0 −63.5 underflow 1 −63 2 −62.5 ↓ ↓ Gain correspondence (COARSE) The default programmed value is as follows: • NCOARSE = 32 • Gain = 0.825 • Vi to be full-scale = 1.212. 127 0 0 ↓ ↓ ↓ 254 63.5 63 or 64 255 64 64 To modulate this gain, the fine register is programmed using the above equation. With a full-scale ADC input, the fine register resolution is a 1⁄2LSB peak-to-peak (see Table 4 for NCOARSE = 32). Table 4 Gain correspondence (FINE) NFINE The default programmed value is: GAIN Vi TO BE FULL-SCALE • Programmed code = 127 0 0.825 1.212 • Clamp code = 0 31 0.878 1.139 • ADC output = 0. The default programmed value is: NFINE = 0. COARSE AND FINE REGISTERS CONTROL REGISTER These two registers enable the gain control, the AGC gain with the coarse register and the reference voltage with the fine register. The coarse register programming equation is as follows: COAST and HSYNC signals can be inverted by setting the I2C-bus control bits V level and H level respectively. When V level and H level are set to zero respectively, COAST and HSYNC are active HIGH. N COARSE + 1 1 GAIN = ---------------------------------------------- × ------ = N FINE 16 V ref 1 – ------------------- 32 × 16 The bit ‘edge’ defines the rising or falling edge of CKREF to synchronise the PLL. It will be on the rising edge if the bit is at logic 0 and on the falling edge if the bit is at logic 1. N COARSE + 1 ------------------------------------------------- × 32 V ref ( 512 – N FINE ) Where: Vref = 2.5 V. The bits Up and Do are used for the test, to force the charge pump current. These bits have to be logic 0 during normal use. The gain correspondence is given in Table 3. The gain is linear with reference to the programming code (NFINE = 0). The bits Ip0, Ip1 and Ip2 control the charge pump current, to increase the bandwidth of the PLL, as shown in Table 5. 1999 Mar 09 18 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) Table 5 TDA8752 Charge-pump current control Table 7 Ip2 Ip1 Ip0 CURRENT (µA) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 6.25 12.5 25 50 100 200 400 700 VCO gain control VCO1 VCO0 VCO gain (MHz/V) PIXEL CLOCK FREQUENCY RANGE (MHz) 1 0 60 10 to 17 0 1 30 17 to 35 1 0 60 35 to 60 1 1 100 60 to 100 The bits VCO1 and VCO0 control the VCO gain. The default programmed value is as follows: • Internal resistance = 16 kΩ The default programmed value is as follows: • VCO gain = 15 MHz/V. • Charge pump current = 100 µA • Test bits: no test mode; bits Up and Do at logic 0 DIVIDER REGISTER • Rising edge of CKREF: bit edge at logic 0 This register controls the PLL frequency. The bits are the LSB bits. • COAST and HSYNC inputs are active HIGH: V level and H level at logic 0. The default programmed value is 0011 0010 0000 = 800. VCO REGISTER The MSB bits (Di11, Di10, Di9) and the LSB bit (Di0) have to be programmed before the bits Di8 to Di1 to have the required divider ratio. The bit Di0 is used for the parity divider number = Di0 = 0 = even number Di0 = 1 = odd number. It should be noted that if the I2C-bus programming is done in mode = 1 and the bit Di0 has to be toggled, then the registers have to be loaded twice to have the update divider ratio. The bits Z2, Z1 and Z0 enable the internal resistance for the VCO filter to be selected. Table 6 VCO register bits Z2 Z1 Z0 RESISTANCE (kΩ) 0 0 0 high impedance 0 0 1 128 0 1 0 32 0 1 1 16 1 0 0 8 1 0 1 4 1 1 0 2 1 1 1 1 POWER-DOWN MODE • When the supply is completely switched off, the registers are set to their default values; in that event they have to be reprogrammed if the required settings are different (e.g. through an EEPROM) • When the device is in power-down mode, the previously programmed register values remain unaffected. PHASEA AND PHASEB REGISTERS The bit Cka is logic 0 when the used clock is the PLL clock, and logic 1 when the used clock is the external clock. The bit Ckb is logic 0 when the second clock is not used. The bits Pa4 to Pa0 and Pb4 to Pb0 are used to program the phase shift for the clock, CKADCO, CKAO and CKBO (see Table 8). 1999 Mar 09 19 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) Table 8 TDA8752 Phase registers bits Pa4, Pb4 Pa3, Pb3 Pa2, Pb2 Pa1, Pb1 Pa0, Pb0 PHASE SHIFT (°) 0 0 ↓ ↓ 1 1 0 0 ↓ ↓ 1 1 0 0 ↓ ↓ 1 1 0 0 ↓ ↓ 1 1 0 1 ↓ ↓ 0 1 0 11.25 ↓ ↓ 337.5 348.75 The default programmed value is as follows: • No external clock: CKA at logic 0 • No use of the second clock: CKB at logic 0 • Phase shift for CKAO and CKADCO = 0° • Phase shift for CKBO = 0°. I2C-bus protocol I2C-bus address Table 9 A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 1 1 ADD2 ADD1 0 The I2C-bus address of the circuit is 10011 xx0. Bits A2 and A1 are fixed by the potential on pins ADD1 and ADD2. Thus, four TDA8752s can be used on the same system, using the addresses for ADD1 and ADD2 with the I2C-bus. The A0 bit must always be equal to logic 0 because it is not possible to read the data in the register. The timing and protocol for the I2C-bus are standard. Two sequences are available, see Tables 10 and 11. Table 10 Address sequence for mode 0 S IC ADDRESS ACK SUBADDRESS REGISTER1 ACK DATA REGISTER1 (see Table 1) ACK SUBADDRESS REGISTER2 ACK .... P DATA REGISTER2 ACK .... P Where: S = START condition, ACK = acknowledge and P = STOP condition. Table 11 Address sequence for mode 1 S IC ADDRESS ACK SUBADDRESS xxx1 1111 ACK DATA REGISTER1 (see Table 1) ACK Where: S = START condition, ACK = acknowledge and P = STOP condition. 1999 Mar 09 20 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Using the 3-wire interface, an indefinite number of ICs can operate on the same system. Pin SEN is used to validate the circuits. SEN tr3W = 600 ns 100 ns 1 9 1 9 SCL ts3W = 100 ns SDA X X X th3W = 100 ns X A3 A2 A1 A0 X D7 D6 D5 D4 D3 D2 D1 D0 X Philips Semiconductors For the 3-wire serial bus the first byte refers to the register address which is programmed. The second byte refers to the data to be sent to the chosen register (see Table 1). The acquisition is achieved via SEN. Triple high speed Analog-to-Digital Converter (ADC) 1999 Mar 09 3-wire protocol MGG365 21 Fig.10 3-wire serial bus protocol. Product specification TDA8752 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage −0.3 +7.0 V VCCD digital supply voltage −0.3 +7.0 V VDDD logic input voltage −0.3 +7.0 V VCCO output stages supply voltage −0.3 +7.0 V ∆VCC supply voltage differences VCCA − VCCD −1.0 +1.0 V VCCO − VCCD, VCCO − VDDD −1.0 +1.0 V VCCA − VDDD, VCCD − VDDD −1.0 +1.0 V VCCA − VCCO −1.0 +1.0 V −0.3 +7.0 V Vi(RGB) RGB input voltage range Io output current − 10 mA Tstg storage temperature −55 +150 °C Tamb operating ambient temperature 0 70 °C Tj junction temperature − 150 °C referenced to AGND HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1999 Mar 09 PARAMETER CONDITIONS thermal resistance from junction to ambient 22 in free air VALUE UNIT 52 K/W Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 CHARACTERISTICS VCCA = V11 (or V19, V27 or V99) referenced to AGND (V13, V21, V29 or V96 = 4.75 to 5.25 V; VCCD = V95 referenced to DGND (V86) = 4.75 to 5.25 V; VDDD = V40 referenced to VSSD (V41) = 4.75 to 5.25 V; VCCO = V59 (or V69, V79 or V85) referenced to OGND (V48, V60, V70 or V82) = 4.75 to 5.25 V; AGND, DGND, OGND and VSSD short circuited together. Tamb = 0 to 70 °C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VDDD logic supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage 4.75 5.0 5.25 V ICCA analog supply current − 120 − mA IDDD logic supply current for I2C-bus and 3-wire − 1.0 − mA ICCD digital supply current − 40 − mA ICCO output stages supply current − 6 − mA ICCO(PLL) output PLL supply current − 5 − mA ICCA(PLL) analog PLL supply current − 28 − mA ∆VCC supply voltage differences VCCA − VCCD −0.25 − +0.25 V VCCO − VCCD, VCCO − VDDD −0.25 − +0.25 V VCCA − VDDD, VCCD − VDDD −0.25 − +0.25 V VCCA − VCCO −0.25 − +0.25 V − 1.0 − W − 87 − mW Ptot total power consumption Ppd power consumption in power-down mode ramp input; fCLK = 100 MHz ramp input; fCLK = 100 MHz R, G and B amplifiers B bandwidth −3 dB; Tamb = 25 °C 250 − − MHz tset settling time of the block ADC plus AGC full-scale (black-to-white) transition; input signal settling time < 1 ns; 1 to 99%; Tamb = 25 °C − 4.5 6 ns GNCOARSE coarse gain range Vref = 2.5 V; minimum coarse gain register; code = 32; (see Fig.8) − −1.67 − dB maximum coarse gain register; code = 99; (see Fig.8) − 8 − dB 1999 Mar 09 23 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) SYMBOL GFINE PARAMETER fine gain correction range TDA8752 CONDITIONS MIN. TYP. MAX. UNIT fine register input code = 0; (see Fig.9) − 0 − dB fine register input code = 31; (see Fig.9) − −0.5 − dB Vref = 2.5 V with 100 ppm/°C maximum variation − − 200 ppm/°C − ±20 − µA ∆Gamp/T amplifier gain stability as a function of temperature IGC gain current tstab amplifier gain adjustment speed HSYNC active; capacitors − on pins 8, 16 and 24 = 22 nF 25 − mdB/µs Vi(p-p) input voltage range (peak-to-peak value) corresponding to full-scale output 0.4 − 1.2 V tr(Vi) input voltage rise time fi = 100 MHz; square wave − − 2.5 ns tf(Vi) input voltage fall time fi = 100 MHz; square wave − − 2.5 ns GE(rms) channel-to-channel gain matching (RMS value) maximum coarse gain; Tamb = 25 °C − 1 − % minimum coarse gain; Tamb = 25 °C − 2 − % black level noise on RGB channels = 10 mV (max.) (RMS value); Tamb = 25 °C −1 − +1 LSB Clamps PCLP precision tCOR1 clamp correction time to within ±100 mV black level input ±10 mV variation; clamp capacitor = 4.7 nF − − 300 ns tCOR2 clamp correction time to less than 1 LSB ±100 mV black level input variation; clamp capacitor = 4.7 nF − − 10 lines tW(CLP) clamp pulse width 500 − 2000 ns CLPE channel-to-channel clamp matching −1 − +1 LSB Aoff code clamp reference clamp register input code = 0 − −63.5 − LSB clamp register input code = 255 − 64 − LSB fCLK = 60 MHz; see Table 13 − 450 − ps − 360 − ps Phase-locked loop jPLL(rms) long term PLL jitter (RMS value) fCLK = 100 MHz; see Table 13 DR divider ratio 100 − 4095 fref reference clock frequency range 15 − 280 kHz fPLL output clock frequency range 12 − 100 MHz 1999 Mar 09 24 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) SYMBOL PARAMETER TDA8752 CONDITIONS MIN. TYP. MAX. UNIT − − 40 lines PLL recapture time when coast mode is aborted − 3 − lines tcap PLL capture time in start-up conditions − − 5 ms Φstep phase shift step Tamb = 25 °C − 11.25 − deg 60 − − MHz TDA8752/8 100 − − MHz tCOASTmax maximum coast mode time trecap ADCs fs maximum sampling frequency TDA8752/6 INL DC integral non linearity from IC analog input to digital output; ramp input; fCLK = 100 MHz − ±0.5 ±1.5 LSB DNL DC differential non linearity from IC analog input to digital output; ramp input; fCLK = 100 MHz − ±0.5 ±1.0 LSB ENOB effective number of bits from IC analog input to digital output; 10 kHz sine wave input; ramp input; fCLK = 100 MHz; note 1 − 7.4 − bits maximum gain; fCLK = 100 MHz − 45 − dB minimum gain; fCLK = 100 MHz − 44 − dB maximum gain; fCLK = 100 MHz − 60 − dB minimum gain; fCLK = 100 MHz − 60 − dB 45 50 55 % 100 − − MHz Signal-to-noise ratio S/N signal-to-noise ratio Spurious free dynamic range SFDR spurious free dynamic range Clock timing output (CKADCO, CKBO and CKAO) ηext ADC clock duty cycle fCLK(max) maximum clock frequency 100 MHz output Clock timing input (CKEXT) fCLK(max) maximum clock frequency 100 − − MHz tCPH clock pulse width HIGH 3.6 − − ns tCPL clock pulse width LOW 4.5 − − ns td(CLKO) delay from CKEXT to CKADCO INV set to LOW 13.6 14.7 15.2 ns INV set to HIGH − t CLK ---------2 − ns time difference between samples operating in the same supply − and temperature condition 0.1 0.3 ns ∆tsample 1999 Mar 09 25 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) SYMBOL PARAMETER TDA8752 CONDITIONS MIN. TYP. MAX. UNIT Data timing (see Fig.11); fCLK = 100 MHz; CL = 10 pF; note 2 − − − ns output delay time − −3.3 −2.6 ns output hold time 4.6 5.5 − ns td(s) sampling delay time td(o) th(o) referenced to CKADCO 3-state output delay time; (see Fig.12) tdZH output enable HIGH − 12 − ns tdZL output enable LOW − 10 − ns tdHZ output disable HIGH − 50 − ns tdLZ output disable LOW − 65 − ns PLL clock output VOL LOW-level output voltage Io = 1 mA − 0.3 0.8 V VOH HIGH-level output voltage Io = − 1 mA 2.4 3.5 − V IOL LOW-level output current VOL = 0.4 V − 2 − mA IOH HIGH-level output current VOH = 2.7 V − −0.4 − mA ADC data outputs VOL LOW-level output voltage Io = 1 mA − 0 0.8 V VOH HIGH-level output voltage Io = − 1 mA 2.4 VCCD − V IOL LOW-level output current VOL = 0.4 V − 2 − mA IOH HIGH-level output current VOH = 2.7 V − −0.5 − mA TTL digital inputs (CKREF, COAST, CKEXT, INV, HSYNC and CLP) VIL LOW level input voltage − − 0.8 V VIH HIGH level input voltage 2.0 − − V IIL LOW level input current VIL = 0.4 V 400 − − µA IIH HIGH level input current VIH = 2.7 V − − 100 µA Zi input impedance − 4 − kΩ Ci input capacitance − 4.5 − pF 3-wire serial bus treset reset time of the chip before 3-wire communication − 600 − ns tsu data set-up time − 100 − ns th data hold time − 100 − ns I2C-bus; see note 3 fSCL clock frequency 0 − 100 kHz tBUF time the bus must be free before new transmission can start 4.7 − − µs 1999 Mar 09 26 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) SYMBOL PARAMETER TDA8752 CONDITIONS MIN. TYP. MAX. UNIT 4.0 − − µs 4.7 − − µs LOW level clock period 4.7 − − µs tCKH HIGH level clock period 4.0 − − µs tSU;DAT data set-up time 250 − − ns tHD;DAT data hold time 0 − − ns tr SDA and SCL rise time for fSCL = 100 kHz − − 1.0 µs tf SDA and SCL fall time for fSCL = 100 kHz − − 300 ns tSU;STOP stop condition set-up time 4.0 − − µs CL(bus) capacitive load for each bus line − − 400 pF tHD;STA start condition hold time tSU;STA start condition set-up time tCKL repeated start Notes to the characteristics 1. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST frequency). Conversion-to-noise ratio: S/N = EB × 6.02 + 1.76 dB. 2. Output data acquisition is available after the maximum delay time td(o), which is the time during which the data is available. All the timings are given for a 10 pF capacitive load. A higher load can be used but the timing must then be rechecked. 3. The I2C-bus timings are given for a frequency of 100 kbit/s (100 kHz). This bus can be used at a frequency of 400 kbit/s (400 kHz). tCPH handbook, full pagewidth tCPL n 50 % = 1.4 V CKADCO td(o) DATA R0 to R7, ROR G0 to G7, GOR B0 to B7, BOR 2.4 V In − 1 In In + 1 In + 2 1.4 V 0.4 V th(o) td(s) VlN sample N + 1 sample N + 2 sample N Fig.11 Timing diagram. 1999 Mar 09 27 MGL103 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 VCCD handbook, full pagewidth 50% OE tdHZ tdZH HIGH 90% output data 50% tdLZ LOW tdZL HIGH VCCD output data 50% LOW 3.3 kΩ 10% S1 TDA8752 10 pF OE tOE = 100 kHz. Fig.12 Timing diagram and test conditions of 3-state output delay time. Table 12 Test conditions for Fig.12 TEST SWITCH S1 tdLZ VCCD tdZl VCCD tdHZ GND tdZH GND 1999 Mar 09 28 MGD695 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... fCLK (MHz) N 15.75 14.3 VGA: 640 × 480 31.5 VESA: 800 × 600 48.08 VESA: 1024 × 768 SUN: 1152 × 900 CGA: 640 × 200 LONG TIME JITTER(2) KO (MHz/V) CZ (nF) CP (nF) IP (µA) Z (kΩ) ps (RMS) ns (p-p) PLL PHASE DRIFT(3) (ns) 912 15 150 1 200 4 − − 1.2 25.2 800 30 150 1 400 2 610 3.6 0.7 50 1040 60 150 1 700 1 480 2.9 0.55 60.02 78.8 1312 100 150 1 700 1 380 2.3 0.3 66.67 100 1500 100 150 1 700 1 360 2.2 0.3 Notes 1. Values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25°C. 2. PLL long-term time jitter is measured at the end of the video line, where it is at its maximum. 3. Measured between 0 and 70 °C. Philips Semiconductors fref (kHz) Triple high speed Analog-to-Digital Converter (ADC) VIDEO STANDARDS APPLICATION INFORMATION 1999 Mar 09 Table 13 Examples of PLL settings and performances; note 1 29 Product specification TDA8752 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) handbook, full pagewidth 33 nF CZ VCCA(PLL) n.c. n.c. 10 nF 2.5 V RIN GIN BIN 1 TDA8752 PWDWN CKBO 150 pF COAST CKADCO OE CLP CP VCCO(PLL) CKEXT AGNDPLL OGNDPLL HSYNC CKREF DGND VCCD CKAO INV 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 DEC2 2 79 Vref 3 78 1.5 nF DEC1 4 77 n.c. 5 76 RAGC 6 75 10 nF RBOT 7 74 22 nF RGAINC 8 73 4.7 nF RCLP 9 72 10 nF RDEC 10 71 VCCAR 11 70 100 nF RIN 12 69 AGNDR 13 68 75 Ω or 50 Ω GAGC 14 67 10 nF GBOT 15 66 22 nF GGAINC TDA8752 16 65 4.7 nF GCLP 17 64 10 nF GDEC 18 63 VCCAG 19 62 100 nF GIN 20 61 AGNDG 21 60 75 Ω or 50 Ω BAGC 22 59 10 nF BBOT 23 58 22 nF BGAINC 24 57 4.7 nF BCLP 25 56 10 nF BCDEC 26 55 VCCAB 27 54 100 nF BIN 28 53 AGNDB 29 52 75 Ω or 50 Ω n.c. 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 n.c. ADD1 TCK DIS I2C/3W ADD2 TDO SEN VDDD VSSD n.c. ROR BOR n.c. GOR 4.7 4.7 kΩ kΩ SDA SCL VDDD VDDD All supply pins have to be decoupled, with two capacitors: one for high frequencies (approximately 1 nF) and one for the low frequencies (approximately 100 nF or higher). Fig.13 Application diagram. 1999 Mar 09 30 CKREFO VCCOR R7 R6 R5 R4 R3 R2 R1 R0 OGNDR VCCOG G7 G6 G5 G4 G3 G2 G1 G0 OGNDG VCCOB B7 B6 B5 B4 B3 B2 B1 n.c. B0 n.c. OGNDB MGG371 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 PACKAGE OUTLINE QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT317-2 c y X 80 A 51 81 50 ZE e E HE A A2 (A 3) A1 θ wM pin 1 index Lp bp L 31 100 detail X 30 1 wM bp e ZD v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 3.20 0.25 0.05 2.90 2.65 0.25 0.40 0.25 0.25 0.14 20.1 19.9 14.1 13.9 0.65 24.2 23.6 18.2 17.6 1.95 1.0 0.6 0.2 0.15 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT317-2 1999 Mar 09 EUROPEAN PROJECTION 31 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. SOLDERING Introduction to soldering surface mount packages • For packages with leads on two sides and a pitch (e): This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 1999 Mar 09 32 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable suitable(2) suitable suitable suitable LQFP, QFP, TQFP not recommended(3)(4) suitable SSOP, TSSOP, VSO not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 1999 Mar 09 33 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1999 Mar 09 34 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 NOTES 1999 Mar 09 35 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/750/05/pp36 Date of release: 1999 Mar 09 Document order number: 9397 750 05306