MC74VHC1G03 D

MC74VHC1G03
Single 2−Input NOR Gate
with Open Drain Output
Features
•
•
•
•
•
•
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MARKING
DIAGRAMS
5
SC−88A / SOT−353 / SC−70
DF SUFFIX
CASE 419A
M
The MC74VHC1G03 is an advanced high speed CMOS 2−input
NOR gate with an open drain output fabricated with silicon gate
CMOS technology.
The internal circuit is composed of multiple stages, including an
open drain output which provides the capability to set output
switching level. This allows the MC74VHC1G03 to be used to
interface 5 V circuits to circuits of any voltage between VCC and 7 V
using an external resistor and power supply.
The MC74VHC1G03 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage.
VP M G
G
1
High Speed: tPD = 3.6 ns (Typ) at VCC = 5 V
Low Internal Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
CASE 483
Power Down Protection Provided on Inputs
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 62
Pb−Free Packages are Available
IN B
VP
= Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
1
5
VCC
PIN ASSIGNMENT
OVT
IN A
GND
VP M G
G
2
3
4
OUT Y
1
IN B
2
IN A
3
GND
4
OUT Y
5
VCC
FUNCTION TABLE
Figure 1. Pinout (Top View)
Inputs
IN A
IN B
≥1
OUT Y
Figure 2. Logic Symbol
Output
A
B
Y
L
L
H
H
L
H
L
H
Z
L
L
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
January, 2007 − Rev. 14
1
Publication Order Number:
MC74VHC1G03/D
MC74VHC1G03
MAXIMUM RATINGS
Symbol
Characteristics
VCC
DC Supply Voltage
VIN
DC Input Voltage
VOUT
DC Output Voltage
IIK
Input Diode Current
VCC = 0
High or Low State
IOK
Output Diode Current
IOUT
DC Output Current, per Pin
ICC
DC Supply Current, VCC and GND
PD
Power Dissipation in Still Air at 85°C
qJA
Thermal Resistance
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
TSTG
Storage Temperature Range
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
Unit
V
−0.5 to +7.0
V
−0.5 to 7.0
−0.5 to VCC + 0.5
V
−20
mA
+20
mA
+25
mA
VOUT < GND; VOUT > VCC
+50
mA
SC70−5/SC−88A
TSOP−5
150
200
mW
SC70−5/SC−88A (Note 1)
TSOP−5
350
230
°C/W
260
°C
)150
°C
*65 to )150
°C
Level 1
Oxygen Index: 28 to 34
ESD Withstand Voltage
ILATCHUP
Value
−0.5 to +7.0
Latchup Performance
UL 94 V−0 @ 0.125 in
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 2000
> 200
N/A
V
Above VCC and Below GND at 125°C (Note 5)
$500
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
Max
Unit
VCC
DC Supply Voltage
2.0
5.5
V
VIN
DC Input Voltage
0.0
5.5
V
DC Output Voltage
0.0
7.0
V
−55
+125
°C
0
0
100
20
ns/V
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
Time, Years
80
1,032,200
117.8
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 110°C
Time, Hours
TJ = 120°C
Junction
Temperature °C
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
TJ = 80°C
Input Rise and Fall Time
TJ = 90°C
Operating Temperature Range
TJ = 100°C
TA
tr, tf
TJ = 130°C
VOUT
1
1
10
100
1000
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
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2
MC74VHC1G03
DC ELECTRICAL CHARACTERISTICS
VCC
Symbol
Parameter
Test Conditions
VIH
Minimum High−Level
Input Voltage
VIL
Maximum Low−Level
Input Voltage
VOL
Maximum Low−Level
Output Voltage
VIN = VIH or VIL
TA ≤ 85°C
TA = 25°C
(V)
Min
2.0
3.0
4.5
5.5
1.5
2.1
3.15
3.85
Typ
Max
Min
−55 ≤ TA ≤ 125°C
Max
Min
1.5
2.1
3.15
3.85
2.0
3.0
4.5
5.5
0.0
0.0
0.0
Max
1.5
2.1
3.15
3.85
Unit
V
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN = VIH or VIL
IOL = 50 mA
2.0
3.0
4.5
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
ILKG
Z−State Output
Leakage Current
VIN = VIL
VOUT = VCC or GND
5.5
$5
$10
$10
mA
IIN
Maximum Input
Leakage Current
VIN = 5.5 V or GND
0 to
5.5
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
1.0
20
40
mA
IOFF
Power Off−Output
Leakage Current
VOUT = 5.5 V
VIN = 5.5 V
0
0.25
2.5
5
mA
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AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns
TA ≤ 85°C
TA = 25°C
Typ
Max
Unit
9.5
13.0
11.0
15.5
ns
5.5
7.5
6.5
8.5
8.0
10.0
8.1
11.4
13.0
15.5
5.1
7.5
8.5
10.0
4
10
10
10
Parameter
tPZL
Maximum Output
Enable Time,
Input A or B to Y
VCC = 3.3 ± 0.3 V
RL = RI = 500 W
CL = 15 pF
CL = 50 pF
5.6
8.1
7.9
11.4
VCC = 5.0 ± 0.5 V
RL = RI = 500 W
CL = 15 pF
CL = 50 pF
3.6
5.1
Maximum Output
Disable Time
VCC = 3.3 ± 0.3 V
RL = RI = 500 W
CL = 50 pF
VCC = 5.0 ± 0.5 V
RL = RI = 500 W
CL = 50 pF
CIN
Maximum Input
Capacitance
Min
Max
−55 ≤ TA ≤ 125°C
Max
Symbol
tPLZ
Test Conditions
Min
Min
ns
pF
Typical @ 25°C, VCC = 5.0V
CPD
18
Power Dissipation Capacitance (Note 6)
pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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3
MC74VHC1G03
VCC
VCC − 7 V
OVT
A
VCC
A or B
RL
50%
GND
B
tPLZ
tPZL
Y
HIGH
IMPEDANCE
50% VCC
Figure 4. Output Voltage Mismatch Application
VOL +0.3 V
Figure 5. Switching Waveforms
VCC
R1
PULSE
GENERATOR
VCC x 2
DUT
RT
CL
RL
CL = 50 pF equivalent (Includes jig and probe capacitance)
RL = R1 = 500 W or equivalent
RT = ZOUT of pulse generator (typically 50 W)
Figure 6. Test Circuit
VCC
VCC
MC74VHC1G01
A
B
1
VCC
A
MC74VHC1G03
5
2.2 kW
B
RLED
2
3.3 V
1.5 V
MC74VHC1G03
3
C
6
E = (A • B) + (C+D)
D
Figure 7. Complex Boolean Functions
220 W
A
GTL
B
Figure 8. LED Driver
Figure 9. GTL Driver
ORDERING INFORMATION
Device
Package
MC74VHC1G03DFT1
SC70−5 / SC−88A / SOT−353
MC74VHC1G03DFT1G
SC70−5 / SC−88A / SOT−353
(Pb−Free)
MC74VHC1G03DFT2
SC70−5 / SC−88A / SOT−353
MC74VHC1G03DFT2G
SC70−5 / SC−88A / SOT−353
(Pb−Free)
MC74VHC1G03DTT1
SOT23−5 / TSSOP−5 / SC59−5
MC74VHC1G03DTT1G
SOT23−5 / TSSOP−5 / SC59−5
(Pb−Free)
Shipping †
3000/Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHC1G03
PACKAGE DIMENSIONS
SC−88A, SOT−353, SC−70
CASE 419A−02
ISSUE J
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
M
B
M
N
J
C
K
H
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
−−−
0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
−−−
0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
MC74VHC1G03
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE F
NOTE 5
2X
0.10 T
2X
0.20 T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
D 5X
0.20 C A B
5
1
4
2
3
M
B
S
K
L
DETAIL Z
G
A
DIM
A
B
C
D
G
H
J
K
L
M
S
DETAIL Z
J
C
0.05
SEATING
PLANE
H
T
MILLIMETERS
MIN
MAX
3.00 BSC
1.50 BSC
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
1.25
1.55
0_
10 _
2.50
3.00
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74VHC1G03/D