MC74VHC1G07 Single Non-Inverting Buffer with Open Drain Output The MC74VHC1G07 is an advanced high speed CMOS buffer with open drain output fabricated with silicon gate CMOS technology. The internal circuit is composed of multiple stages, including a buffer and an open drain output which provides the capability to set the output switching level. This allows the MC74VHC1G07 to be used to interface any 2 V to 5.5 V circuit to circuits of any voltage between 1.5 V and 7 V using an external resistor and power supply. The MC74VHC1G07 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. • • • • • • High Speed: tPD = 3.8 ns (Typ) at VCC = 5 V Low Internal Power Dissipation: ICC = 1 mA (Max) at TA = 25°C Power Down Protection Provided on Inputs Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 105 These Devices are Pb−Free and are RoHS Compliant NC 5 1 5 SC−88A / SOT−353 / SC−70 DF SUFFIX CASE 419A VCC V7 M G G 1 V7 M G G TSOP−5 / SOT−23 / SC−59 DT SUFFIX CASE 483 V7 M G = Device Code = Date Code* = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. OVT IN A MARKING DIAGRAMS M Features http://onsemi.com 2 PIN ASSIGNMENT GND 4 3 OUT Y Figure 1. Pinout 1 IN A 1 NC 2 IN A 3 GND 4 OUT Y 5 VCC FUNCTION TABLE OUT Y Figure 2. Logic Symbol A Input Y Output L H L Z ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2011 May, 2011 − Rev. 17 1 Publication Order Number: MC74VHC1G07/D MC74VHC1G07 MAXIMUM RATINGS Symbol Parameter VCC DC Supply Voltage VIN DC Input Voltage VOUT DC Output Voltage Value Unit 0.5 to 7.0 V −0.5 to +7.0 V 0.5 to 7.0 V 20 mA 20 mA IIK DC Input Diode Current IOK DC Output Diode Current IOUT DC Output Sink Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pin +50 mA 65 to 150 °C 260 °C TSTG VOUT GND; VOUT VCC Storage Temperature Range TL Lead Temperature, 1 mm from Case for 10 Seconds TJ Junction Temperature Under Bias qJA Thermal Resistance PD Power Dissipation in Still Air at 85°C MSL Moisture Sensitivity FR Flammability Rating VESD Latchup Performance °C 350 230 °C/W SC70−5/SC−88A/SOT−353 SOT23−5/TSOP−5/SC59−5 150 200 mW Level 1 Oxygen Index: 28 to 34 ESD Withstand Voltage ILATCHUP 150 SC70−5/SC−88A/SOT−353 (Note 1) SOT23−5/TSOP−5/SC59−5 UL 94 V−0 @ 0.125 in Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) 2000 200 N/A V Above VCC and Below GND at 125°C (Note 5) 500 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage 2.0 5.5 V VIN DC Input Voltage 0.0 5.5 V DC Output Voltage 0.0 7.0 V 55 125 °C 0 0 100 20 ns/V VOUT TA Operating Temperature Range tr , tf Input Rise and Fall Time VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 TJ = 80°C 117.8 TJ = 90°C 1,032,200 TJ = 100°C 80 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 110°C Time, Years TJ = 120°C Time, Hours TJ = 130°C Junction Temperature °C NORMALIZED FAILURE RATE DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES 1 1 10 100 1000 TIME, YEARS Figure 3. Failure Rate vs. Time Junction Temperature http://onsemi.com 2 MC74VHC1G07 DC ELECTRICAL CHARACTERISTICS TA = 255C VCC Symbol Parameter Test Conditions (V) Min 1.5 2.1 3.15 3.85 VIH Minimum High−Level Input Voltage 2.0 3.0 4.5 5.5 VIL Maximum Low−Level Input Voltage 2.0 3.0 4.5 5.5 VOL Maximum Low−Level Output Voltage VIN = VIH or VIL Typ TA 855C Max Min Max 1.5 2.1 3.15 3.85 0.0 0.0 0.0 *555C TA 1255C Min Max 1.5 2.1 3.15 3.85 Unit V 0.5 0.9 1.35 1.65 0.5 0.9 1.35 1.65 0.5 0.9 1.35 1.65 V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V VIN = VIL IOL = 50 mA 2.0 3.0 4.5 VIN = VIL IOL = 4 mA IOL = 8 mA 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 ILKG Z−State Output Leakage Current VIN = VIH VOUT = VCC or GND 5.5 0.25 2.5 5.0 mA IIN Maximum Input Leakage Current VIN = 5.5 V or GND 0 to 5.5 0.1 1.0 1.0 mA ICC Maximum Quiescent Supply Current VIN = VCC or GND 5.5 1.0 20 40 mA IOFF Power Off−Output Leakage Current VOUT = 5.5 V VIN = 5.5 V 0 0.25 2.5 5 mA AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns TA = 255C TA 855C *555C TA 1255C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol Parameter tPZL Maximum Output Enable Time, Input A to Y tPLZ CIN Maximum Output Disable Time Test Conditions Min Typ Max Min Max Min Max Unit ns VCC = 3.3 0.3 V RL = RI = 500 W CL = 15 pF CL = 50 pF 5.0 7.5 7.1 10.6 8.5 12.0 10.0 14.5 VCC = 5.0 0.5 V RL = RI = 500 W CL = 15 pF CL = 50 pF 3.8 5.3 5.5 7.5 6.5 8.5 8.0 10.0 VCC = 3.3 0.3 V RL = RI = 500 W CL = 50 pF 7.5 10.6 12.0 14.5 VCC = 5.0 0.5 V RL = RI = 500 W CL = 50 pF 5.3 7.5 8.5 10.0 4 10 10 10 Maximum Input Capacitance ns pF Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Note 6) 18 pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. http://onsemi.com 3 MC74VHC1G07 VCC 2 R1 VCC A 50% tPZL tPLZ HIGH IMPEDANCE 50% VCC Y A GND CL * RL VOL 0.3 V *Includes jig and probe capacitance. RL = R1 = 500 W Figure 4. Switching Waveforms VCC MC74VHC1G01 1.5 V to 7 V A VCC 2.2 kW B RL OVT A Figure 5. Test Circuit MC74VHC1G03 C F = (A • B) (CD) E D MC74VHC1G07 E Figure 6. Output Voltage Mismatch Application VCC 1 A VCC MC74VHC1G07 3.3 V 5 1.5 V 220 W RLED 2 3 Figure 7. Complex Boolean Functions A 4 Figure 8. LED Driver GTL Figure 9. GTL Driver ORDERING INFORMATION Device Package MC74VHC1G07DFT1G SC70−5/SC−88A/SOT−353 (Pb−Free) MC74VHC1G07DFT2G SC70−5/SC−88A/SOT−353 (Pb−Free) MC74VHC1G07DTT1G SOT23−5/TSOP−5/SC59−5 (Pb−Free) Shipping† 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 MC74VHC1G07 PACKAGE DIMENSIONS SC−88A (SC−70−5/SOT−353) CASE 419A−02 ISSUE K A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A−01 OBSOLETE. NEW STANDARD 419A−02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. G 5 4 −B− S 1 2 DIM A B C D G H J K N S 3 D 5 PL 0.2 (0.008) M B M N J C H K http://onsemi.com 5 INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC --0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC --0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 MC74VHC1G07 PACKAGE DIMENSIONS TSOP−5 CASE 483−02 ISSUE H D 5X NOTE 5 2X 0.10 T 2X 0.20 T NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. 0.20 C A B M 5 1 4 2 L 3 B S K DETAIL Z G A DIM A B C D G H J K L M S DETAIL Z J C 0.05 SEATING PLANE H T MILLIMETERS MIN MAX 3.00 BSC 1.50 BSC 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 SOLDERING FOOTPRINT* 0.95 0.037 1.9 0.074 2.4 0.094 1.0 0.039 0.7 0.028 SCALE 10:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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