INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT153 Dual 4-input multiplexer Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Dual 4-input multiplexer FEATURES • Non-inverting output • Separate enable for each output • Common select inputs • See ‘253” for 3-state version • Permits multiplexing from n lines to 1 line • Enable line provided for cascading (n lines to 1 line) • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT153 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. 74HC/HCT153 The 74HC/HCT153 have two identical 4-input multiplexers which select two bits of data from up to four sources selected by common data select inputs (S0, S1). The two 4-input multiplexer circuits have individual active LOW output enable inputs (1E, 2E) which can be used to strobe the outputs independently. The outputs (1Y, 2Y) are forced LOW when the corresponding output enable inputs are HIGH. The “153” is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels applied to S0 and S1. The logic equations for the outputs are: 1Y = 1E.(1I0.S1.S0+1I1.S1.S0+ +1I2.S1.S0+1I3.S1.S0) 2Y = 2E.(2I0.S1.S0+2I1.S1.S0+ +2I2.S1.S0+2I3.S1.S0) The “153” can be used to move data to a common output bus from a group of registers. The state of the select inputs would determine the particular register from which the data came. An alternative application is a function generator. The device can generate two functions or three variables. This is useful for implementing highly irregular random logic. The “153” is similar to the “253” but has standard outputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay HCT CL = 15 pF; VCC = 5 V 1In, 2In to nY 14 16 ns Sn to nY 15 17 ns nE to nY 10 11 ns CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per multiplexer notes 1 and 2 30 30 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: See “74HC/HCT/HCU/HCMOS Logic Package Information”. fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V ∑ (CL × VCC2 × fo) = sum of outputs 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V December 1990 ORDERING INFORMATION 2 Philips Semiconductors Product specification Dual 4-input multiplexer 74HC/HCT153 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 15 1E, 2E output enable inputs (active LOW) 14, 2 S0, S1 common data select inputs 6, 5, 4, 3 1I0 to 1I3 data inputs from source 1 7 1Y multiplexer output from source 1 8 GND ground (0 V) 9 2Y multiplexer output from source 2 10, 11, 12, 13 2I0 to 2I3 data inputs from source 2 16 VCC positive supply voltage December 1990 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. Fig.4 Functional diagram. 3 Philips Semiconductors Product specification Dual 4-input multiplexer 74HC/HCT153 FUNCTION TABLE SELECT INPUTS DATA INPUTS OUTPUT ENABLE OUTPUT S0 S1 nI0 nI1 nI2 nI3 nE nY X X X X X X H L L L H H L L L L L H X X X X L H X X X X X X X X L L L L L H L H L L H H H H H H X X X X X X X X L H X X X X L H L L L L L H L H Note 1. H = HIGH voltage level L = LOW voltage level X = don’t care Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification Dual 4-input multiplexer 74HC/HCT153 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER −40 to+85 +25 min. typ. max. min. max. −40 to+125 min. UNIT VCC WAVEFORMS (V) max. tPHL/ tPLH propagation delay 1In to nY; 2In to nY 47 17 14 145 29 25 180 36 31 220 44 38 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay Sn to nY 50 18 14 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.7 tPHL/ tPLH propagation delay nE to nY 33 12 10 100 20 17 125 25 21 150 30 26 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Figs 6 and 7 December 1990 5 Philips Semiconductors Product specification Dual 4-input multiplexer 74HC/HCT153 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT 1In, 2In nE Sn 0.45 0.60 1.35 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER −40 to+85 +25 min. typ. max. min. max. −40 to+125 min. UNIT VCC (V) WAVEFORMS max. tPHL propagation delay 1In to nY; 2In to nY 19 34 43 51 ns 4.5 Fig.6 tPLH propagation delay 1In to nY; 2In to nY 13 24 30 36 ns 4.5 Fig.6 tPHL/ tPLH propagation delay Sn to nY 20 34 43 51 ns 4.5 Fig.7 tPHL/ tPLH propagation delay nE to nY 14 27 34 41 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 December 1990 6 Figs 6 and 7 Philips Semiconductors Product specification Dual 4-input multiplexer 74HC/HCT153 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the input (1In, 2In) to output (1Y, 2Y) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the select input (S0, S1) and the output enable input (E) to output (1Y, 2Y) propagation delays and the output transition times. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 7