INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT157 Quad 2-input multiplexer Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Quad 2-input multiplexer 74HC/HCT157 Moving the data from two groups of registers to four common output buses is a common use of the “157”. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator. FEATURES • Non-inverting data path • Output capability: standard • ICC category: MSI The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common. GENERAL DESCRIPTION The 74HC/HCT157 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The “157” is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The logic equations are: The 74HC/HCT157 are quad 2-input multiplexers which select 4 bits of data from two sources under the control of a common data select input (S). The four outputs present the selected data in the true (non-inverted) form. The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions. 1Y = E.(1l1.S + 1l0.S) 2Y = E.(2l1.S + 2l0.S) 3Y = E.(3l1.S + 3l0.S) 4Y = E.(4l1.S + 4l0.S) The “157” is identical to the “158” but has non-inverting (true) outputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay HCT CL = 15 pF; VCC = 5 V nI0, nI1 to nY 11 13 ns E to nY 11 12 ns S to nY 12 19 ns CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per multiplexer notes 1 and 2 70 70 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 Philips Semiconductors Product specification Quad 2-input multiplexer 74HC/HCT157 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 S common data select input 2, 5, 11, 14 1I0 to 4I0 data inputs from source 0 3, 6, 10, 13 1I1 to 4I1 data inputs from source 1 4, 7, 9, 12 1Y to 4Y multiplexer outputs 8 GND ground (0 V) 15 E enable input (active LOW) 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Quad 2-input multiplexer 74HC/HCT157 FUNCTION TABLE INPUTS E S nI0 nI1 nY H X X X L L L L L L L H H L H X X X X L H L H L H Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care Fig.4 Functional diagram. Fig.5 Logic diagram. December 1990 4 OUTPUT Philips Semiconductors Product specification Quad 2-input multiplexer 74HC/HCT157 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER −40 to +85 +25 min. typ. max. min. max. −40 to +125 min. UNIT VCC WAVEFORMS (V) max. tPHL/ tPLH propagation delay nI0 to nY; nI1 to nY 36 13 10 125 25 21 155 31 26 190 38 32 ns 2.0 4.5 6.0 Fig.7 tPHL/ tPLH propagation delay E to nY 39 14 11 115 23 20 145 29 25 175 35 30 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay S to nY 41 15 12 125 25 21 155 31 26 190 38 32 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.6 and Fig.7 December 1990 5 Philips Semiconductors Product specification Quad 2-input multiplexer 74HC/HCT157 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT nI0 nI1 E S 1.00 1.00 0.60 1.00 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER −40 to +85 +25 min. typ. max. min. max. −40 to +125 min. UNIT VCC WAVEFORMS (V) max. tPHL/ tPLH propagation delay nI0 to nY; nI1 to nY 16 27 34 41 ns 4.5 Fig.7 tPHL/ tPLH propagation delay E to nY 15 26 33 39 ns 4.5 Fig.6 tPHL/ tPLH propagation delay S to nY 22 37 46 56 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 and Fig.7 December 1990 6 Philips Semiconductors Product specification Quad 2-input multiplexer 74HC/HCT157 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the enable input (E) to output (nY) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the data inputs (nIn) and common data select input (S) to output (nY) propagation delays. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 7