74HC257; 74HCT257 Quad 2-input multiplexer; 3-state Rev. 05 — 13 January 2010 Product data sheet 1. General description The 74HC257; 74HCT257 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC257 and 74HCT257 have four identical 2-input multiplexers with 3-state outputs, which select 4 bits of data from two sources and are controlled by a common data select input (S). The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and the data inputs from source 1 (1I1 to 4I1) are selected when S is HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs. The 74HC257 and 74HCT257 are the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The outputs are forced to a high-impedance OFF-state when OE is HIGH. The logic equations for the outputs are: 1Y = OE • ( 1I1 • S • 1I0 • S ) 2Y = OE • ( 2I1 • S • 2I0 • S ) 3Y = OE • ( 3I1 • S • 3I0 • S ) 4Y = OE • ( 4I1 • S • 4I0 • S ) Except for their non-inverting (true) outputs the 74HC257; 74HCT257 are identical to the 74HC258. 2. Features Non-inverting data path 3-state outputs interface directly with system bus Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114E exceeds 2 000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from −40 °C to +85 °C and from −40 °C to +125 °C 74HC257; 74HCT257 NXP Semiconductors Quad 2-input multiplexer; 3-state 3. Ordering information Table 1. Ordering information Type number 74HC257N Package Temperature range Name Description Version −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HCT257N 74HC257D 74HCT257D 74HC257DB 74HCT257DB 74HC257PW 74HCT257PW 4. Functional diagram 1 15 1 2 1I0 3 1I1 5 2I0 6 2I1 11 3I0 10 3I1 14 4I0 13 4I1 15 OE S 2 1Y 2Y 4 3 G1 EN 1 MUX 4 1 5 7 7 6 3Y 9 11 9 10 4Y 12 14 12 13 001aad467 mga835 Fig 1. Logic symbol Fig 2. IEC logic symbol 74HC_HCT257_5 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 05 — 13 January 2010 2 of 17 74HC257; 74HCT257 NXP Semiconductors Quad 2-input multiplexer; 3-state 2 3 1I0 1I1 1 S 15 OE Fig 3. 5 6 2I0 2I1 11 10 3I0 3I1 14 13 4I0 4I1 SELECTOR 3-STATE MULTIPLEXER OUTPUTS 1Y 2Y 3Y 4Y 4 7 9 12 mgr280 Functional diagram 1I0 1Y 1I1 2I0 2Y 2I1 3I0 3Y 3I1 4I0 4Y 4I1 OE S Fig 4. 001aad468 Logic diagram 74HC_HCT257_5 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 05 — 13 January 2010 3 of 17 74HC257; 74HCT257 NXP Semiconductors Quad 2-input multiplexer; 3-state 5. Pinning information 5.1 Pinning 74HC257 74HCT257 S 1 16 VCC 1I0 2 15 OE 1I1 3 14 4I0 1Y 4 13 4I1 2I0 5 12 4Y 2I1 6 11 3I0 2Y 7 10 3I1 GND 8 9 3Y 001aad499 Fig 5. Pin configuration DIP16, SO16, SSOP16 and TSSOP16 5.2 Pin description Table 2. Pin description Symbol Pin Description S 1 common data select input 1I0 to 4I0 2, 5, 11, 14 data input from source 0 1I1 to 4I1 3, 6, 10, 13 data input from source 1 1Y to 4Y 4, 7, 9, 12 3-state multiplexer output GND 8 ground (0 V) OE 15 3-state output enable input (active LOW) VCC 16 supply voltage 6. Functional description 6.1 Function table Table 3. Function table[1] Control Input Output OE S nl0 nl1 nY H X X X Z L H X L L L H X H H L L L X L L L H X H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 74HC_HCT257_5 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 05 — 13 January 2010 4 of 17 74HC257; 74HCT257 NXP Semiconductors Quad 2-input multiplexer; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V −0.5 +7 V - ±20 mA IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V - ±20 mA IO output current VO = −0.5 V to VCC + 0.5 V - ±35 mA ICC supply current - +70 mA IGND ground current - −70 mA Tstg storage temperature −65 +150 °C Ptot total power dissipation DIP16 package [1] - 750 mW SO16 package [2] - 500 mW SSOP16 package [3] - 500 mW TSSOP16 package [3] - 500 mW [1] For DIP16 packages: above 70 °C, Ptot derates linearly with 12 mW/K. [2] For SO16 packages: above 70 °C, Ptot derates linearly with 8 mW/K. [3] For SSOP16 and TSSOP16 packages: above 60 °C, Ptot derates linearly with 5.5 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit Type 74HC257 VCC supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Δt/ΔV input transition rise and fall rates VCC = 2.0 V - - 625 ns VCC = 4.5 V - 1.67 139 ns VCC = 6.0 V - - 83 ns −40 - +125 °C Tamb ambient temperature Type 74HCT257 VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Δt/ΔV input transition rise and fall rates - 1.67 139 ns Tamb ambient temperature −40 - +125 °C VCC = 4.5 V 74HC_HCT257_5 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 05 — 13 January 2010 5 of 17 74HC257; 74HCT257 NXP Semiconductors Quad 2-input multiplexer; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = −20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V 74HC257 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL IO = −20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = −6.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = −7.8 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 7.8 mA; VCC = 6.0 V 0.4 V VI = VIH or VIL - 0.16 0.26 - 0.33 - II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1.0 ±1.0 IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND; VCC = 6.0 V - - ±0.5 - ±5.0 ±10.0 ±10.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - Ci input capacitance - 3.5 - 80 160 ±1.0 μA 160 μA pF 74HCT257 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = −20 μA 4.4 4.5 - 4.4 - 4.4 - V IO = −6 mA 3.98 4.32 - 3.84 - 3.7 - V - 0.1 - 0.1 IO = 20 μA - 0 0.1 - 0.33 - 0.4 IO = 6.0 mA - 0.15 0.26 - ±1.0 - ±1.0 V - - ±0.1 - ±5.0 - ±10 VOL II LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V input leakage current VI = VCC or GND; VCC = 5.5 V 74HC_HCT257_5 Product data sheet V μA © NXP B.V. 2010. All rights reserved. Rev. 05 — 13 January 2010 6 of 17 74HC257; 74HCT257 NXP Semiconductors Quad 2-input multiplexer; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). 25 °C −40 °C to +85 °C −40 °C to +125 °C Symbol Parameter Conditions Min Typ Max Min Max Min Max IOZ OFF-state output current VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A - - ±0.5 - 80 - 160 ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 ΔICC additional supply current VI = VCC − 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A per input pin; nI0, nI1 inputs - 40 144 - 180 - 196 μA per input pin; OE input - 135 486 - 608 - 662 μA per input pin; S input - 70 252 - 315 - 343 μA - 3.5 - CI input capacitance Unit μA μA pF 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); For test circuit see Figure 8. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to Unit +125 °C Typ Max Max Max VCC = 2.0 V 36 110 140 165 ns VCC = 4.5 V 13 22 28 33 ns VCC = 5.0 V; CL = 15 pF 11 - - - ns VCC = 6.0 V 10 19 24 28 ns VCC = 2.0 V 47 150 190 225 ns VCC = 4.5 V 17 30 38 45 ns VCC = 5.0 V; CL = 15 pF 14 - - - ns 14 26 33 38 ns VCC = 2.0 V 33 150 190 225 ns VCC = 4.5 V 12 30 38 45 ns 10 26 33 38 ns VCC = 2.0 V 41 150 190 225 ns VCC = 4.5 V 15 30 38 45 ns VCC = 6.0 V 12 26 33 38 ns 74HC257 tpd propagation delay nl0 to nY or nl1 to nY; see Figure 6 [1] S to nY; see Figure 6 VCC = 6.0 V ten enable time OE to nY; see Figure 7 [2] VCC = 6.0 V tdis disable time OE to nY; see Figure 7 [3] 74HC_HCT257_5 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 05 — 13 January 2010 7 of 17 74HC257; 74HCT257 NXP Semiconductors Quad 2-input multiplexer; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); For test circuit see Figure 8. Symbol Parameter Conditions tt see Figure 6 transition time 25 °C power dissipation capacitance −40 °C to Unit +125 °C Typ Max Max Max VCC = 2.0 V 14 60 75 90 ns VCC = 4.5 V 5 12 15 18 ns 13 15 ns [4] VCC = 6.0 V CPD −40 °C to +85 °C 4 10 45 - VCC = 4.5 V 16 30 38 VCC = 5.0 V; CL = 15 pF 13 - - 20 35 44 per multiplexer; VI = GND to VCC [5] nl0 to nY or nl1 to nY; see Figure 6 [1] pF 74HCT257 tpd propagation delay 45 ns ns S to nY; see Figure 6 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF 53 ns 17 - ns 15 30 38 45 ns ten enable time OE to nY; VCC = 4.5 V; see Figure 7 [2] tdis disable time OE to nY; VCC = 4.5 V; see Figure 7 [3] 16 30 38 45 ns tt transition time VCC = 4.5 V; see Figure 6 [4] 5 12 15 18 ns per multiplexer; VI = GND to VCC [5] 45 - CPD power dissipation capacitance [1] tpd is the same as tPHL, tPLH. [2] ten is the same as tPZH, tPZL. [3] tdis is the same as tPHZ, tPLZ. [4] tt is the same as tTHL, tTLH. [5] pF CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74HC_HCT257_5 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 05 — 13 January 2010 8 of 17 74HC257; 74HCT257 NXP Semiconductors Quad 2-input multiplexer; 3-state 11. Waveforms VI input S, nI0, nI1 VM VM GND t PHL t PLH VOH 90 % output nY VM VM 10 % VOL t THL t TLH 001aad477 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Propagation delays input (S, nI0, nI1) to output (nY) and output (nY) transition times tr VI tf 90 % OE input VM GND 10 % tPLZ output tPZL VCC LOW-to-OFF OFF-to-LOW VM 10 % VOL tPHZ output VOH tPZH 90 % HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled 001aac479 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. 3-state output enable and disable times Table 8. Measurement points Type Input Output VM VM 74HC257 0.5VCC 0.5VCC 74HCT257 1.3 V 1.3 V 74HC_HCT257_5 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 05 — 13 January 2010 9 of 17 74HC257; 74HCT257 NXP Semiconductors Quad 2-input multiplexer; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC G VCC VI VO RL S1 open DUT RT CL 001aad983 Measurement points are given in Table 8 and test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistor. Fig 8. Test circuit for switching times Table 9. Type Test data Input Load Switch position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC257 VCC 6 ns 50 pF 1 kΩ open GND VCC 74HCT257 3V 6 ns 50 pF 1 kΩ open GND VCC 74HC_HCT257_5 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 05 — 13 January 2010 10 of 17 74HC257; 74HCT257 NXP Semiconductors Quad 2-input multiplexer; 3-state 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 9. EUROPEAN PROJECTION Package outline SOT38-4 (DIP16) 74HC_HCT257_5 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 05 — 13 January 2010 11 of 17 74HC257; 74HCT257 NXP Semiconductors Quad 2-input multiplexer; 3-state SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT109-1 (SO16) 74HC_HCT257_5 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 05 — 13 January 2010 12 of 17 74HC257; 74HCT257 NXP Semiconductors Quad 2-input multiplexer; 3-state SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 11. Package outline SOT338-1 (SSOP16) 74HC_HCT257_5 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 05 — 13 January 2010 13 of 17 74HC257; 74HCT257 NXP Semiconductors Quad 2-input multiplexer; 3-state TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 12. Package outline SOT403-1 (TSSOP16) 74HC_HCT257_5 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 05 — 13 January 2010 14 of 17 74HC257; 74HCT257 NXP Semiconductors Quad 2-input multiplexer; 3-state 13. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT257_5 20100113 Product data sheet - Modifications: • 74HC_HCT257_4 Table 7 “Dynamic characteristics”: changed 3OE to OE 74HC_HCT257_4 20090608 Product data sheet - 74HC_HCT257_3 74HC_HCT257_3 20050920 Product data sheet - 74HC_HCT257_CNV_2 74HC_HCT257_CNV_2 19980930 Product specification - - 74HC_HCT257_5 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 05 — 13 January 2010 15 of 17 74HC257; 74HCT257 NXP Semiconductors Quad 2-input multiplexer; 3-state 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 14.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC_HCT257_5 Product data sheet © NXP B.V. 2010. All rights reserved. Rev. 05 — 13 January 2010 16 of 17 NXP Semiconductors 74HC257; 74HCT257 Quad 2-input multiplexer; 3-state 16. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 13 January 2010 Document identifier: 74HC_HCT257_5