LTC5800-WHM
SmartMesh WirelessHART Node
Wireless Mote
Network Features
Description
Complete Radio Transceiver, Embedded Processor,
and Networking Software for Forming a Self-Healing
Mesh Network
nn Compliant to WirelessHART (IEC62591) Standard
nn SmartMesh® Networks Incorporate:
nn Time Synchronized Network-Wide Scheduling
nn Per Transmission Frequency Hopping
nn Redundant Spatially Diverse Topologies
nn Network-Wide Reliability and Power Optimization
nn NIST Certified Security
nn SmartMesh Networks Deliver:
nn >99.999% Network Reliability Achieved in the
Most Challenging Dynamic RF Environments Often
Found in Industrial Applications
nn Sub 50µA Routing Nodes
SmartMesh WirelessHART wireless sensor networks
are self managing, low power networks built from
wireless nodes called motes. The LTC®5800-WHM is the
WirelessHART Mote-on-Chip™ integrated circuit in the
Eterna®* family of IEEE 802.15.4 System-on-Chip (SoC)
solutions, featuring a highly integrated, low power radio
design by Dust Networks® as well as an ARM Cortex-M3 32bit microprocessor running Dust’s embedded SmartMesh
WirelessHART networking software.
nn
LTC5800-WHM Features
Industry-Leading Low Power Radio Technology with:
4.5mA to Receive a Packet
nn 5.4mA to Transmit at 0dBm
nn 9.7mA to Transmit at 8dBm
nn PCB Module Versions Available (LTP™5901/LTP5902WHM) with RF Modular Certifications
nn 2.4GHz, IEEE 802.15.4 System-on-Chip
nn 72-Pin 10mm × 10mm QFN Package
nn
nn
The LTC5800-WHM SoC features an on-chip power amplifier (PA) and transceiver, requiring only power supply
decoupling, crystals, and antenna with matching circuitry
to create a complete wireless node.
With Dust’s time-synchronized WirelessHART networks all
motes in the network may route, source or terminate data
while providing many years of battery powered operation.
The SmartMesh WirelessHART software provided with
the LTC5800-WHM is fully tested and validated, and is
readily configured via a software Application Programming Interface.
SmartMesh WirelessHART motes deliver a highly flexible
network with proven reliability and low power performance
in an easy-to-integrate platform.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Dust, Dust Networks, SmartMesh and
Eterna are registered trademarks and LTP, the Dust Networks logo and Mote-on-Chip are
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents, including 7375594, 7420980, 7529217, 7791419,
7881239, 7898322, 8222965.
* Eterna is Dust Networks’ low power radio SoC architecture.
Typical Application
20MHz
EXPANDED VIEW
MANAGER
LTC5800-WHM
ANTENNA
LTP5903-WHR
ANTENNA
IN+
LTC2379-18 SPI
SENSOR
µCONTROLLER
UART
ETHERNET
UART
IN–
HOST
APPLICATION
MOTE
32kHz
5800WHM TA01
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LTC5800-WHM
Table of Contents
Network Features........................................... 1
LTC5800-WHM Features................................... 1
Typical Application ......................................... 1
Description.................................................. 1
SmartMesh Network Overview............................ 3
Absolute Maximum Ratings............................... 4
Order Information........................................... 4
Pin Configuration........................................... 4
Recommended Operating Conditions.................... 5
DC Characteristics.......................................... 5
Radio Specifications....................................... 5
Radio Receiver Characteristics........................... 6
Radio Transmitter Characteristics........................ 6
Digital I/O Characteristics................................. 7
Temperature Sensor Characteristics..................... 7
Analog Input Chain Characteristics...................... 7
System Characteristics.................................... 8
UART AC Characteristics................................... 8
TIMEn AC Characteristics................................. 10
Radio_Inhibit AC Characteristics........................ 10
Flash AC Characteristics.................................. 11
Flash SPI Slave AC Characteristics..................... 11
Electrical Characteristics................................. 12
Typical Performance Characteristics................... 13
Pin Functions............................................... 17
2
Operation................................................... 22
Power Supply...........................................................22
Supply Monitoring and Reset..................................23
Precision Timing......................................................23
Application Time Synchronization...........................23
Time References......................................................23
Radio....................................................................... 24
UARTs...................................................................... 24
Autonomous MAC....................................................25
Security...................................................................25
Temperature Sensor................................................26
Radio Inhibit............................................................26
Flash Programming.................................................26
FLASH Data Retention.............................................26
State Diagram.......................................................... 28
Applications Information................................. 29
Regulatory and Standards Compliance....................29
Soldering Information..............................................29
Related Documentation................................... 30
Package Description...................................... 31
Typical Application........................................ 32
Related Parts............................................... 32
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LTC5800-WHM
SmartMesh Network Overview
A SmartMesh network consists of a self-forming multi-hop
mesh of nodes, known as motes, which collect and relay
data, and a network manager that monitors and manages
network performance and security, and exchanges data
with a host application.
SmartMesh networks communicate using a time slotted
channel hopping (TSCH) link layer, pioneered by Dust
Networks. In a TSCH network, all motes in the network
are synchronized to within less than a millisecond. Time
in the network is organized into time slots, which enables
collision-free packet exchange and per-transmission
channel-hopping. In a SmartMesh network, every device
has one or more parents (e.g. mote 3 has motes 1 and
2 as parents) that provide redundant paths to overcome
communications interruption due to interference, physical
obstruction or multi-path fading. If a packet transmission
fails on one path, the next retransmission may try on a
different path and different RF channel.
The Network Manager uses health reports to continually
optimize the network to maintain >99.999% data reliability
even in the most challenging RF environments.
The use of TSCH allows SmartMesh devices to sleep in
between scheduled communications and draw very little
power in this state. Motes are only active in time slots
where they are scheduled to transmit or receive, typically
resulting in a duty cycle of < 1%. The optimization software in the Network Manager coordinates this schedule
automatically. When combined with the Eterna low power
radio, every mote in a SmartMesh network—even busy
routing ones—can run on batteries for years. By default,
all motes in a network are capable of routing traffic from
other motes, which simplifies installation by avoiding the
complexity of having distinct routers vs non-routing end
nodes. Motes may be configured as non-routing to further
reduce that particular mote’s power consumption and to
support a wide variety of network topologies.
A network begins to form when the network manager
instructs its on-board Access Point (AP) radio to begin
sending advertisements—packets that contain information
that enables a device to synchronize to the network and
request to join. This message exchange is part of the security handshake that establishes encrypted communications
between the manager or application, and mote. Once motes
have joined the network, they maintain synchronization
through time corrections when a packet is acknowledged.
ALL NODES ARE ROUTERS.
THEY CAN TRANSMIT AND RECEIVE.
THIS NEW NODE CAN JOIN
ANYWHERE BECAUSE ALL
NODES CAN ROUTE.
HOST
APPLICATION
SNO 02
NETWORK MANAGER
AP
Mote
1
Mote
2
Mote
3
SNO 01
An ongoing discovery process ensures that the network
continually discovers new paths as the RF conditions
change. In addition, each mote in the network tracks performance statistics (e.g. quality of used paths, and lists of
potential paths) and periodically sends that information
to the network manager in packets called health reports.
At the heart of SmartMesh motes and network managers is the Eterna IEEE 802.15.4e System-on-Chip (SoC),
featuring Dust Networks’ highly integrated, low power
radio design, plus an ARM Cortex-M3 32-bit microprocessor running SmartMesh networking software. The
SmartMesh networking software comes fully compiled
yet is configurable via a rich set of Application Programming Interfaces (APIs) which allows a host application
to interact with the network, e.g. to transfer information
to a device, to configure data publishing rates on one or
more motes, or to monitor network state or performance
metrics. Data publishing can be uniform or different for
each device, with motes being able to publish infrequently
or faster than once per second as needed.
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LTC5800-WHM
Absolute Maximum Ratings
Pin Configuration
(Note 1)
Pin functions shown in italics are currently not supported in software.
RADIO_INHIBIT 1
CAP_PA_1P 2
CAP_PA_1M 3
CAP_PA_2M 4
CAP_PA_2P 5
CAP_PA_3P 6
CAP_PA_3M 7
CAP_PA_4M 8
CAP_PA_4P 9
VDDPA 10
LNA_EN / GPIO17 11
RADIO_TX / GPIO18 12
RADIO_TXn / GPIO19 13
ANTENNA 14
AI_0 15
AI_1 16
AI_3 17
AI_2 18
54 VPP
53 SPIS_SSn / SDA
52 SPIS_SCK / SCL
51 SPIS_MOSI / GPIO26 / UARTC1_RX
50 SPIS_MISO / 1_WIRE / UARTC1_TX
49 PWM0 / GPIO16
48 DP1 (GPIO20) / TIMER16_IN
47 SPIM_SS_0n / GPIO12
46 SPIM_SS_1n / GPIO13
45 IPCS_SSn / GPIO3
44 IPCS_SCK / GPIO4
43 SPIM_SCK / GPIO9
42 IPCS_MOSI / GPIO5
41 SPIM_MOSI / GPIO10
40 IPCS_MISO / GPIO6
39 SPIM_MISO / GPIO11
38 UARTCO_RX
37 UARTCO_TX
EXPOSED PAD
(GND)
OSC_32K_XOUT 19
OSC_32K_XIN 20
VBGAP 21
RESETn 22
TDI 23
TDO 24
TMS 25
TCK 26
DP4 (GPIO23) 27
OSC_20M_XIN 28
OSC_20M_XOUT 29
VDDA 30
VCORE 31
VOSC 32
DP3 (GPIO22) / TIMER8_IN 33
DP2 (GPIO21) / LPTIMER_IN 34
SLEEPn / GPIO14 35
DP0 (GPIO0) / SPIM_SS_2n 36
CAUTION: This part is sensitive to electrostatic discharge
(ESD). It is very important that proper ESD precautions be
observed when handling the LTC5800-WHM.
TOP VIEW
72 TIMEn
71 UART_TX
70 UART_TX_CTSn
69 UART_TX-RTSn
68 UART_RX
67 UART_RX_CTSn
66 UART_RX_RTSn
65 VSUPPLY
64 CAP_PRIME_1P
63 CAP_PRIME_1M
62 CAP_PRIME_2M
61 CAP_PRIME_2P
60 CAP_PRIME_3P
59 CAP_PRIME_3M
58 CAP_PRIME_4M
57 CAP_PRIME_4P
56 VPRIME
55 FLASH_P_ENn
Supply Voltage on VSUPPLY...................................4.20V
Input Voltage on AI_0/AI_1/AI_2/AI_3 Inputs.........1.80V
Voltage on Any Digital I/O Pin.–0.3V to VSUPPLY + 0.3V
Input RF Level.......................................................10dBm
Storage Temperature Range (Note 3)...... –55°C to 125°C
Junction Temperature (Note 3).............................. 125°C
Operating Temperature Range
LTC5800I..............................................–40°C to 85°C
LTC5800H........................................... –55°C to 105°C
WR PACKAGE
72-LEAD PLASTIC QFN
TJMAX = 125°C, ΨJCtop = 0.2°C/W, ΨJCbottom = 0.6°C/W
EXPOSED PAD IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC5800IWR-WHMA#PBF
LTC5800WR-WHMA
72-Lead (10mm × 10mm × 0.85mm) Plastic QFN
–40°C to 85°C
LTC5800HWR-WHMA#PBF
LTC5800WR-WHMA
72-Lead (10mm × 10mm × 0.85mm) Plastic QFN
–55°C to 105°C
*The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
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LTC5800-WHM
Recommended Operating Conditions
The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VSUPPLY
Supply Voltage
Including Noise and Load Regulation
l
MIN
TYP
Supply Noise
Requires Recommended RLC Filter, 50Hz to 2MHz
l
Operating Relative Humidity
Non-condensing
l
10
90
% RH
Temperature Ramp Rate
While Operating in Network
l
–8
+8
°C/min
2.1
MAX
UNITS
3.76
V
250
mV
DC Characteristics
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
OPERATION/STATE
CONDITIONS
MIN
TYP
MAX
UNITS
Reset
After Power-on Reset
1.2
µA
Power-on Reset
During Power-on Reset, Maximum 750µs + VSUPPLY Rise Time
from 1V to 1.9V
12
mA
Doze
RAM On, ARM Cortex-M3, Flash, Radio, and Peripherals Off,
All Data and State Retained, 32.768kHz Reference Active
1.2
µA
Deep Sleep
RAM On, ARM Cortex-M3, Flash, Radio, and Peripherals Off,
All Data and State Retained, 32.768kHz Reference Inactive
0.8
µA
In-Circuit Programming
RESETn and FLASH_P_ENn Asserted, IPCS_SCK at 8MHz
20
mA
Peak Operating Current
+8dBm
+0dBm
System Operating at 14.7MHz, Radio Transmitting, During Flash
Write. Maximum duration 4.33 ms.
30
26
mA
mA
Active
ARM Cortex M3, RAM and Flash Operating, Radio and All Other
Peripherals Off. Clock Frequency of CPU and Peripherals Set to
7.3728MHz, VCORE = 1.2V
1.3
mA
Flash Write
Single Bank Flash Write
3.7
mA
Flash Erase
Single Bank Page or Mass Erase
2.5
mA
Radio Tx
+0dBm (LTC5800I)
+0dBm (LTC5800H)
+8dBm (LTC5800I)
+8dBm (LTC5800H)
Current With Autonomous MAC Managing Radio Operation,
CPU Inactive. Clock Frequency of CPU and Peripherals Set to
7.3728MHz.
5.4
5.6
9.7
9.9
mA
mA
mA
mA
Radio Rx
LTC5800I
LTC5800H
Current With Autonomous MAC Managing Radio Operation,
CPU Inactive. Clock Frequency of CPU and Peripherals Set to
7.3728MHz.
4.5
4.7
mA
mA
Radio Specifications
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
2.4000
MAX
2.4835
UNITS
GHz
Frequency Band
l
Number of Channels
l
15
Channel Separation
l
5
l
2405 + 5•(k-11)
MHz
l
250
kbps
Channel Center Frequency
Where k = 11 to 25, as Defined by IEEE.802.15.4
Raw Data Rate
Antenna Pin ESD Protection
HBM Per JEDEC JESD22-A114F
Range (Note 4)
Indoor
Outdoor
Free Space
25°C, 50% RH, +2dBi Omni-Directional Antenna, Antenna 2m
Above Ground
MHz
±1000
V
100
300
1200
m
m
m
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LTC5800-WHM
Radio Receiver Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
Receiver Sensitivity
Packet Error Rate (PER) = 1% (Note 5)
–93
dBm
Receiver Sensitivity
PER = 50%
–95
dBm
Saturation
Maximum Input Level the Receiver Will
Properly Receive Packets
0
dBm
Adjacent Channel Rejection (High Side) Desired Signal at -82dBm, Adjacent Modulated Channel 5MHz
Above the Desired Signal, PER = 1% (Note 5)
22
dBc
Adjacent Channel Rejection (Low Side) Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz
Below the Desired Signal, PER = 1% (Note 5)
19
dBc
Alternate Channel Rejection
(High Side)
Desired Signal at –82dBm, Alternate Modulated Channel 10MHz
Above the Desired Signal, PER = 1% (Note 5)
40
dBc
Alternate Channel Rejection (Low Side) Desired Signal at –82dBm, Alternate Modulated Channel 10MHz
Below the Desired Signal, PER = 1% (Note 5)
36
dBc
Second Alternate Channel Rejection
Desired Signal at –82dBm, Second Alternate Modulated Channel
Either 15MHz Above or Below, PER = 1% (Note 5)
42
dBc
Co-Channel Rejection
Desired Signal at –82dBm, Undesired Signal is an 802.15.4
Modulated Signal at the Same Frequency, PER = 1%
–6
dBc
–55
dBm
Frequency Error Tolerance (Note 6)
±50
ppm
Symbol Error Tolerance
±50
ppm
–90 to –10
dBm
LO Feed Through
Received Signal Strength Indicator
(RSSI) Input Range
TYP
MAX
UNITS
RSSI Accuracy
±6
dB
RSSI Resolution
1
dB
Radio Transmitter Characteristics
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER
CONDITIONS
Output Power
High Calibrated Setting
Low Calibrated Setting
Delivered to a 50Ω Load
Spurious Emissions
Conducted Measurement with a 50Ω Single-Ended Load,
+8dBm Output Power. All Measurements Made with Max
Hold. RF Implementation Per Eterna Reference Design
30MHz to 1000MHz
1GHz to 12.75GHz
2.4GHz ISM Upper Band Edge (Peak)
2.4GHz ISM Upper Band Edge (Average)
2.4GHz ISM Lower Band Edge
Harmonic Emissions
2nd Harmonic
3rd Harmonic
6
MIN
TYP
MAX
UNITS
8
0
dBm
dBm
RBW = 120kHz, VBW = 100Hz
RBW = 1MHz, VBW = 3MHz
RBW = 1MHz, VBW = 3MHz
RBW = 1MHz, VBW = 10Hz
RBW = 100kHz, VBW = 100kHz
<–70
–45
–37
–49
–45
dBm
dBm
dBm
dBm
dBc
Conducted Measurement Delivered to a 50Ω Load,
Resolution Bandwidth = 1MHz, Video Bandwidth = 1MHz,
RF Implementation Per Eterna Reference Design
–50
–45
dBm
dBm
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Digital I/O Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL
PARAMETER
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
VOL
Low Level Output Voltage
VOH
CONDITIONS (Note 7)
MIN
TYP
MAX
UNITS
l
–0.3
0.6
V
(Note 8)
l
VSUPPLY – 0.3
VSUPPLY + 0.3
V
Type 1, IOL(MAX) = 1.2mA
l
0.4
V
Low Level Output Voltage
Type 2, Low Drive, IOL(MAX) = 2.2mA
l
0.4
V
Low Level Output Voltage
Type 2, High Drive, IOL(MAX) = 4.5mA
l
0.4
V
High Level Output Voltage
Type 1, IOH(MAX) = –0.8mA
l
VSUPPLY – 0.3
VSUPPLY + 0.3
V
High Level Output Voltage
Type 2, Low Drive, IOH(MAX) = –1.6mA
l
VSUPPLY – 0.3
VSUPPLY + 0.3
V
High Level Output Voltage
Type 2, High Drive, IOH(MAX) = –3.2mA
l
VSUPPLY – 0.3
VSUPPLY + 0.3
V
Input Leakage Current
Input Driven to VSUPPLY or GND
Pull-Up/Pull-Down Resistance
50
nA
50
kΩ
Temperature Sensor Characteristics
The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
Offset
Temperature Offset Error at 25°C
Slope Error
TYP
MAX
UNITS
±0.25
°C
±0.033
°C/°C
Analog Input Chain Characteristics
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
Variable Gain Amplifier
Gain
Gain Error
DNL
DNL
INL
TYP
1
Offset-Digital to Analog Converter (DAC)
Full-Scale
Resolution
Differential Non-Linearity
Analog to Digital Converter (ADC)
Full-Scale, Signal
Resolution
Offset
Differential Non-Linearity
Integral Non-Linearity
Settling Time
Conversion Time
Current Consumption
MIN
8
2
1.80
4
Mid-Scale
1.80
1.8
1.4
10kΩ Source Impedance
40
Analog Inputs (Note 9)
Load
Series Input Resistance
MAX
20
1
2.7
12
1
1
10
20
UNITS
%
V
Bits
mV
V
mV
LSB
LSB
LSB
µs
µs
µA
pF
kΩ
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LTC5800-WHM
System Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
Doze to Active State Transition
Doze to Radio Tx or Rx
QCCA
Charge to Sample RF Channel RSSI
Charge Consumed Starting from Doze State
and Completing an RSSI Measurement
QMAX
Largest Atomic Charge Operation
Flash Erase, 21ms Max Duration
RESETn Pulse Width
UNITS
µs
1.2
ms
4
µC
200
l
l
MAX
5
125
µC
µs
UART AC Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
CONDITIONS
Permitted RX Baud Rate Error
Both Application Programming
Interface (API) and Command Line
Interface (CLI) UARTs
l
MIN
–2
Generated TX Baud Rate Error
Both API and CLI UARTs
TYP
MAX
2
UNITS
%
l
–1
1
%
tRX_RTS to RX_CTS
Assertion of UART_RX_RTSn to Assertion of
UART_RX_CTSn, or Negation of UART_RX_
RTSn to Negation of UART_RX_CTSn
l
0
2
ms
tCTS_R to RX
Assertion of UART_RX_CTSn to Start of Byte
l
0
20
ms
tEOP to RX_RTS
End of Packet (End of the Last Stop Bit) to
Negation of UART_RX_RTSn
l
0
22
ms
tBEG_TX_RTS to TX_CTS
Assertion of UART_TX_RTSn to Assertion of
UART_TX_CTSn
l
0
22
ms
tEND_TX_RTS to TX_CTS
Negation of UART_TX_RTSn to Negation of
UART_TX_CTSn
Mode 2 Only
22
ms
tEND_TX_CTS to TX_RTS
Negation of UART_TX_CTSn to Negation of
UART_TX_RTSn
Mode 4 Only
tTX_CTS to TX
Assertion of UART_TX_CTSn to Start of Byte
l
0
2
Bit Period
tEOP to TX_RTS
End of Packet (End of the Last Stop Bit) to
Negation of UART_TX_RTSn
l
0
1
Bit Period
2
Bit Period
tRX_INTERBYTE
Receive Inter-Byte Delay
l
tRX_INTERPACKET
Receive Inter-Packet Delay
l
20
ms
tTX_INTERPACKET
Transmit Inter-Packet Delay
l
1
Bit Period
tTX to TX_CTS
Start of Byte to Negation of UART_TX_CTSn
l
0
ns
8
100
ms
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UART AC Characteristics
tEOP to RX_RTS
tRX_INTERPACKET
UART_RX_RTSn
tRX_RTS to RX_CTS
tRX_RTS to RX_CTS
UART_RX_CTSn
tRX_CTS to RX
UART_RX
BYTE 0
tRX_INTERBYTE
BYTE 1
tEOP to TX_RTS
tTX_INTERPACKET
UART_TX_RTSn
UART_TX_CTSn
tTX_RTS to TX_CTS
tEND_TX_CTS to TX_RTS
tEND_TX_RTS to TX_CTS
tTX to TX_CTS
tTX_CTS to TX
UART_TX
BYTE 0
BYTE 1
5800IPM F01
Figure 1. API UART Timing
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LTC5800-WHM
TIMEn AC Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
tSTROBE
TIMEn Signal Strobe Width
CONDITIONS
l
MIN
125
tRESPONSE
Delay from Rising Edge of TIMEn to the Start
of Time Packet on API UART
l
0
tTIME_HOLD
Delay from End of Time Packet on API UART
to Falling Edge of Subsequent TIMEn
l
0
Timestamp Resolution (Note 10)
l
1
µs
Network-Wide Time Accuracy (Note 11)
l
±5
µs
tSTROBE
TYP
MAX
UNITS
µs
100
ms
ns
tTIME_HOLD
TIMEn
tRESPONSE
UART_TX
TIME INDICATION PAYLOAD
5800WHM F02
Figure 2. Timestamp Timing
Radio_Inhibit AC Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
tRADIO_OFF
Delay from Rising Edge of
RADIO_INHIBIT to Radio Disabled
CONDITIONS
l
MIN
TYP
MAX
20
UNITS
ms
tRADIO_INHIBIT_STROBE
Maximum RADIO_INHIBIT Strobe Width
l
2
s
tRADIO_INHIBIT_STROBE
RADIO_INHIBIT
tRADIO_OFF
RADIO STATE
ACTIVE/OFF
OFF
ACTIVE/OFF
5800WHM F03
Figure 3. RADIO_INHIBIT Timing
10
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Flash AC Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
tWRITE
Time to Write a 32-Bit Word (Note 12)
CONDITIONS
l
21
µs
tPAGE_ERASE
Time to Erase a 2kB Page (Note 12)
l
21
ms
tMASS_ERASE
Time to Erase 256kB Flash Bank (Note 12)
l
21
ms
Data Retention
MIN
25°C
85°C
105°C
TYP
MAX
100
20
8
UNITS
Years
Years
Years
Flash SPI Slave AC Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tFP_EN_to_RESET
Setup from Assertion of FLASH_P_ENn to
Assertion of RESETn
l
0
ns
tFP_ENTER
Delay from the Assertion RESETn to the
First Falling Edge of IPCS_SSn
l
125
µs
tFP_EXIT
Delay from the Completion of the Last
Flash SPI Slave Transaction to the
Negation of RESETn and FLASH_P_ENn
(Note 13)
l
10
µs
tSSS
IPCS_SSn Setup to the Leading Edge of
IPCS_SCK
l
15
ns
tSSH
IPCS_SSn Hold from Trailing Edge of
IPCS_SCK
l
15
ns
tCK
IPCS_SCK Period
l
300
ns
tDIS
IPCS_MOSI Data Setup
l
15
ns
tDIH
IPCS_MOSI Data Hold
l
5
tDOV
IPCS_MISO Data Valid
l
–5
30
ns
tOFF
IPCS_MISO Data Tri-State
l
0
30
ns
FLASH_P_ENn
RESETn
ns
tFP_EN_TO_RESET
tFP_EXIT
tFP_ENTER
tSSS
tSSH
IPCS_SSn
tCK
IPCS_SCK
tDIS
tDIH
IPCS_MOSI
IPCS_MISO
tDOV
tOFF
5800IPM F04
Figure 4. Flash Programming Interface Timing
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LTC5800-WHM
Electrical Characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: ESD (electrostatic discharge) sensitive device. ESD protection
devices are used extensively internal to Eterna. However, high electrostatic
discharge can damage or degrade the device. Use proper ESD handling
precautions.
Note 3: Extended storage at high temperature is discouraged, as this
negatively affects the data retention of Eterna’s calibration data. See the
FLASH Data Retention section for details.
Note 4: Actual RF range is subject to a number of installation-specific
variables including, but not restricted to ambient temperature, relative
humidity, presence of active interference sources, line-of-sight obstacles,
and near-presence of objects (for example, trees, walls, signage, and so
on) that may induce multipath fading. As a result, range varies.
Note 5: As Specified by IEEE Std. 802.15.4-2006: Wireless Medium
Access Control (MAC) and Physical Layer (PHY) Specifications for
Low-Rate Wireless Personal Area Networks (LR-WPANs)
http://standards.ieee.org/findstds/standard/802.15.4-2011.html
12
Note 6: IEEE Std. 802.15.4-2006 requires transmitters to maintain a
frequency tolerance of better than ±40ppm.
Note 7: Per-pin IO types are provided in the Pin Functions section.
Note 8: VIH maximum voltage input must respect the VSUPPLY maximum
voltage specification.
Note 9: The analog inputs to the ADC can be modeled as a series resistor
to a capacitor. At a minimum the entire circuit, including the source
impedance for the signal driving the analog input should be designed
to settle to within ¼ LSB within the sampling window to match the
performance of the ADC.
Note 10: See the SmartMesh WirelessHART API Guide for the
timeIndication notification definition.
Note 11: Network time accuracy is a statistical measure and varies over
the temperature range, reporting rate and the location of the device
relative to the manager in the network. See the Typical Performance
Characteristics section for a more detailed description.
Note 12: Code execution from flash banks being written or erased is
suspended until completion of the flash operation.
Note 13: Guaranteed by design. Not production tested.
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Typical Performance Characteristics
Network motes typically route through at least two parents
the traffic destined for the manager. The supply current
graphs shown in Figure 5 include a parameter called descendants. In these graphs the term descendants is short
for traffic-weighted descendants and refers to an amount
of activity equivalent to the number of descendants if all
of the network traffic directed to the mote in question.
Generally the number of descendants of a parent is more,
typically 2x or more, than the number of traffic-weighted
descendants. For example, with reference to Figure 6 mote
P1 has 0.75 traffic-weighted descendants. To obtain this
value notice that mote D1 routes half its packets through
mote P1 adding 0.5 to the traffic-weighted descendant
value; the other half of D1’s traffic is routed through its
other parent, P2. Mote D2 routes half its packets through
mote D1 (the other half going through parent P3), which
we know routes half its packets to mote P1, adding another
0.25 to the traffic-weighted descendant value for a total
traffic-weighted descendant value of 0.75.
was performed with the 1-hop mote inside a temperature
chamber. Timing errors due to temperature changes and
temperature differences both between the manager and
this mote and between this mote and its descendents
therefore propagated down through the network. The synchronization of the 3-hop and 5-hop motes to the manager
was then affected by the temperature ramps even though
they were at room temperature. For 2°C/minute testing
the temperature chamber was cycled between –40°C and
85°C at this rate for 24 hours. For 8°C/minute testing, the
temperature chamber was rapidly cycled between 85°C and
45°C for 8 hours, followed by rapid cycling between –5°C
and 45°C for 8 hours, and lastly, rapid cycling between
–40°C and 15°C for 8 hours.
MANAGER
P1
As described in the Application Time Synchronization
section, Eterna provides two mechanisms for applications
to maintain a time base across a network. The synchronization performance plots that follow were generated
using the more precise TIMEn input. Publishing rate is
the rate a mote application sends upstream data. Synchronization improves as the publishing rate increases.
Baseline synchronization performance is provided for a
network operating with a publishing rate of zero. Actual
performance for applications in network will improve
as publishing rates increase. All synchronization testing
10
80
60
8
2 DESCENDANTS 5sec REPORTING
5 DESCENDANTS 30sec REPORTING
2 DESCENDANTS 30sec REPORTING
0 DESCENDANTS 5sec REPORTING
0 DESCENDANTS 30sec REPORTING
40
D2
7
3 HOP
5800WHM F06
Figure 6. Example Network Graph
250
5 DESCENDANTS
2 DESCENDANTS
1 DESCENDANTS
0 DESCENDANTS
200
6
5
4
3
2
20
0
–60 –40 –20
MEDIAN LATENCY (sec)
SUPPLY CURRENT (µA)
100
2 HOP
D1
5 HOPS
4 HOPS
3 HOPS
2 HOPS
1 HOP
9
1 HOP
P3
SUPPLY CURRENT (µA)
120
P2
150
100
50
1
0 20 40 60
TEMPERATURE (°C)
80 100
0
0
5
10
15
20
25
REPORTING INTERVAL (sec)
5800WHM F05a
30
5800WHM F05b
0
0
5
25
10
15
20
REPORTING INTERVAL (sec)
30
5800WHM F05c
Figure 5
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LTC5800-WHM
Typical Performance Characteristics
20
15
10
5
0
–500
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
500
16
14
µ = –0.7
σ = 63.0
N = 281492
12
10
8
6
4
2
0
–500
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
35
µ = 10.1
σ = 35.7
N = 92717
30
25
20
15
10
5
0
–500
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
500
14
12
µ = 7.2
σ = 75.9
N = 92718
8
6
4
2
0
–500
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
5800WHM G04
35
30
25
20
15
10
5
0
–500
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
500
5800WHM G07
14
6
4
2
0
–500
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
14
12
500
9
8
7
µ=6
σ = 125.7
N = 92719
6
5
4
3
2
1
0
–500
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
10
8
6
4
2
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
500
5800WHM G06
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
5 Hops, 8°C/Min
µ = 10.9
σ = 81.5
N = 95165
0
–500
500
5800WHM G03
5800WHM G05
NORMALIZED FREQUENCY OF OCCURENCE (%)
NORMALIZED FREQUENCY OF OCCURENCE (%)
40
8
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
3 Hops, 8°C/Min
µ = 15.3
σ = 39.4
N = 91114
µ = –0.8
σ = 110.7
N = 281493
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
5 Hops, 2°C/Min
10
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
1 Hop, 8°C/Min
45
10
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
3 Hops, 2°C/Min
NORMALIZED FREQUENCY OF OCCURENCE (%)
NORMALIZED FREQUENCY OF OCCURENCE (%)
40
500
12
5800WHM G02
5800WHM G01
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
1 Hop, 2°C/Min
45
NORMALIZED FREQUENCY OF OCCURENCE (%)
25
18
NORMALIZED FREQUENCY OF OCCURENCE (%)
30
µ = 0.1
σ = 35.0
N = 281490
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
5 Hops, Room Temperature
NORMALIZED FREQUENCY OF OCCURENCE (%)
35
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
3 Hops, Room Temperature
NORMALIZED FREQUENCY OF OCCURENCE (%)
NORMALIZED FREQUENCY OF OCCURENCE (%)
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
1 Hop, Room Temperature
500
5800WHM G08
8
7
µ = 10.7
σ = 136.8
N = 95167
6
5
4
3
2
1
0
–500
300
–300
–100 0 100
SYNCHRONIZATION ERROR (µs)
500
5800WHM G09
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LTC5800-WHM
Typical Performance Characteristics
As described in the SmartMesh Network Overview section, devices in network spend the vast majority of their
time inactive in their lowest power state (doze). On a
synchronous schedule a mote will wake to communicate
with another mote. Regularly occurring sequences which
wake, perform a significant function and return to sleep
are considered atomic. These operations are considered
atomic as the sequence of events can not be separated
into smaller events while performing a useful function.
For example, transmission of a packet over the radio is
an atomic operation. Atomic operations are characterized
in either charge or energy. In a time slot where a mote
successfully sends a packet, an atomic transmit includes
setup prior to sending the message, sending the message,
receiving the acknowledgment and the post processing
needed as a result of the message being sent. Similarly in
a time slot when a mote successfully receives a packet, an
atomic receive includes setup prior to listening, listening
until the start of the packet transition, receiving the packet,
sending the acknowledgement and post processing required due to the arrival of the packet.
To ensure reliability each mote in the network is provided
multiple time slots for each packet it nominally will send
and forward. The time slots are assigned to communicate
upstream, toward the manager, with at least two different
motes. When combined with frequency hopping this provides temporal, spatial and spectral redundancy. Given this
approach a mote will often listen for a message that it will
never receive, since the time slot is not being used by the
transmitting mote. It has already successfully transmitted
the packet. Since typically 3 time slots are scheduled for
every 1 packet to be sent or forwarded, motes will perform
more of these atomic “idle listens” than atomic transmit or
atomic receive sequences. Examples of transmit, receive
and idle listen atomic operations are shown in Figure 7.
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LTC5800-WHM
Typical Performance Characteristics
Atomic Operation – Idle Listen, 10ms Time Slot (15.1µC Total Charge at 3.6V), 25°C, LTC5800I
25
DOZE
POWER UP
10
IDLE RECEIVE
70
DOZE
60
50
40
30
5
CURRENT
CHARGE (µC)
CURRENT (mA)
15
RADIO Rx SHUT DOWN
20
RADIO Rx TURN ON
80
20
0
10
CHARGE
–5
–2000
0
2000
4000
6000
8000
0
12000
10000
TIME (µs)
5800WHM F07a
Atomic Operation – Maximum Length Transmit with Acknowlege, 10ms Time Slot (39.2µC Total Charge at 3.6V), 25°C, LTC5800I
25
70
RECEIVE WITH AES
Tx ACKNOWLEDGE
POST
MESSAGE
PROCESSING
60
DOZE
50
10
40
30
5
CURRENT
CHARGE (µC)
CURRENT (mA)
POWER UP
RADIO RECEIVE
DOZE
15
GUARD TIME
20
RADIO Rx TURN ON
80
20
0
10
CHARGE
–5
–2000
0
2000
4000
6000
8000
10000
TIME (µs)
0
12000
5800WHM F07b
Atomic Operation – Maximum Length Transmit with Acknowlege, 10ms Time Slot (55.9µC Total Charge at 3.6V), 25°C, LTC5800I
25
80
70
DOZE
POWER UP
Rx ACKNOWLEDGE
PACKET TRANSMISSION
POST MESSAGE
PROCESSING
DOZE
50
10
40
30
5
CURRENT
20
0
–5
–2000
60
CHARGE (µC)
CURRENT (mA)
15
Tx PREP
20
10
CHARGE
0
2000
4000
6000
TIME (µs)
8000
10000
0
12000
5800WHM F07c
Figure 7
16
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LTC5800-WHM
Pin Functions
Pin functions shown in italics are currently not supported in software.
The following table organizes the pins by functional
groups. For those I/O with multiple functions the alternate
functions are shown on the second and third line in their
respective row. The No column provides the pin number.
The second column lists the function. The Type column
NO POWER SUPPLY
TYPE
I/O
lists the I/O type. The I/O column lists the direction of the
signal relative to Eterna. The Pull column shows which
signals have a fixed passive pull-up or pull-down. The
Description column provides a brief signal description.
PULL DESCRIPTION
P
GND
Power
-
-
Ground Connection, P = QFN Paddle
2
CAP_PA_1P
Power
-
-
PA DC/DC Converter Capacitor 1 Plus Terminal
3
CAP_PA_1M
Power
-
-
PA DC/DC Converter Capacitor 1 Minus Terminal
4
CAP_PA_2M
Power
-
-
PA DC/DC Converter Capacitor 2 Minus Terminal
5
CAP_PA_2P
Power
-
-
PA DC/DC Converter Capacitor 2 Plus Terminal
6
CAP_PA_3P
Power
-
-
PA DC/DC Converter Capacitor 3 Plus Terminal
7
CAP_PA_3M
Power
-
-
PA DC/DC Converter Capacitor 3 Minus Terminal
8
CAP_PA_4M
Power
-
-
PA DC/DC Converter Capacitor 4 Minus Terminal
9
CAP_PA_4P
Power
-
-
PA DC/DC Converter Capacitor 4 Plus Terminal
10 VDDPA
Power
-
-
Internal Power Amplifier Power Supply, Bypass
30 VDDA
Power
-
-
Regulated Analog Supply, Bypass
31 VCORE
Power
-
-
Regulated Core Supply, Bypass
32 VOSC
Power
-
-
Regulated Oscillator Supply, Bypass
54 VPP
Test
-
-
Internal Regulator Test Port
56 VPRIME
Power
-
-
Internal Primary Power Supply, Bypass
57 CAP_PRIME_4P
Power
-
-
Primary DC/DC Converter Capacitor 4 Plus Terminal
58 CAP_PRIME_4M
Power
-
-
Primary DC/DC Converter Capacitor 4 Minus Terminal
59 CAP_PRIME_3M
Power
-
-
Primary DC/DC Converter Capacitor 3 Minus Terminal
60 CAP_PRIME_3P
Power
-
-
Primary DC/DC Converter Capacitor 3 Plus Terminal
61 CAP_PRIME_2P
Power
-
-
Primary DC/DC Converter Capacitor 2 Plus Terminal
62 CAP_PRIME_2M
Power
-
-
Primary DC/DC Converter Capacitor 2 Minus Terminal
63 CAP_PRIME_1M
Power
-
-
Primary DC/DC Converter Capacitor 1 Minus Terminal
64 CAP_PRIME_1P
Power
-
-
Primary DC/DC Converter Capacitor 1 Plus Terminal
65 VSUPPLY
Power
-
-
Power Supply Input to Eterna
NO RADIO
1
RADIO_INHIBIT
GPIO15
TYPE
I/O
1 (Note 14)
I
I/O
PULL DESCRIPTION
-
Radio Inhibit
General Purpose Digital I/O
11
LNA_EN
GPIO17
1
O
I/O
-
External LNA Enable
General Purpose Digital I/O
12
RADIO_TX
GPIO18
1
O
I/O
-
Radio TX Active (External PA Enable/Switch Control)
General Purpose Digital I/O
13
RADIO_TXn
GPIO19
1
O
I/O
-
Radio TX Active (External PA Enable/Switch Control), Active Low
General Purpose Digital I/O
-
-
-
Single-Ended Antenna Port, 50Ω
14 ANTENNA
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LTC5800-WHM
Pin Functions
NO ANALOG
Pin functions shown in italics are currently not supported in software.
TYPE
I/O
15 AI_0
Analog
I
-
Analog Input 0
16 AI_1
Analog
I
-
Analog Input 1
17 AI_3
Analog
I
-
Analog Input 3
18 AI_2
Analog
I
-
Analog Input 2
NO CRYSTALS
PULL DESCRIPTION
TYPE
I/O
19 OSC_32K_XOUT
Crystal
O
-
32 kHz Crystal Xout
20 OSC_32K_XIN
Crystal
I
-
32 kHz Crystal Xin
28 OSC_20M_XIN
Crystal
I
-
20 MHz Crystal Xin
29 OSC_20M_XOUT
Crystal
O
-
20 MHz Crystal Xout
NO RESET
TYPE
I/O
22 RESETn
1
I
NO JTAG
TYPE
I/O
23 TDI
1
I
UP
JTAG Test Data In
24 TDO
1
O
-
JTAG Test Data Out
25 TMS
1
I
26 TCK
1
I
DOWN JTAG Test Clock
TYPE
I/O
PULL DESCRIPTION
27 DP4 (GPIO23)
1
I/O
-
General Purpose Digital I/O
33 DP3 (GPIO22)
TIMER8_EXT
1
I/O
I
-
General Purpose Digital I/O
External Input to 8-Bit Timer/Counter
34 DP2 (GPIO21)
LPTIMER_EXT
1
I/O
I
-
General Purpose Digital I/O
External Input to Low Power Timer/Counter
36 DP0 (GPIO0)
SPIM_SS_2n
1
I/O
O
-
General Purpose Digital I/O
SPI Master Slave Select 2, Active Low
48 DP1 (GPIO20)
TIMER16_EXT
1
I/O
I
-
General purpose digital I/O
External Input to 16-Bit Timer/Counter
NO GPIOS (NOTE 15)
NO SPECIAL PURPOSE
35 SLEEPn
GPIO14
49 PWM0
TIMER16_OUT
GPIO16
72 TIMEn
NO CLI
PULL DESCRIPTION
PULL DESCRIPTION
UP
Reset Input, Active Low
PULL DESCRIPTION
UP
JTAG Test Mode Select
TYPE
I/O
1 (Note 14)
I
I/O
PULL DESCRIPTION
-
Deep Sleep, Active Low
General Purpose Digital I/O
2
O
O
I/O
-
Pulse Width Modulator 0
16-Bit Timer/Counter Match Output/PWM Output
General Purpose Digital I/O
1 (Note 14)
I
-
Time Capture Request, Active Low
TYPE
I/O
37 UARTC0_TX
2
O
-
CLI UART 0 Transmit
38 UARTC0_RX
1
I
UP
CLI UART 0 Receive
18
PULL DESCRIPTION
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Pin Functions
Pin functions shown in italics are currently not supported in software.
NO SPI MASTER
TYPE
I/O
PULL DESCRIPTION
39 SPIM_MISO
GPIO11
1
I
I/O
-
SPI Master (MISO) Master In Slave Out Port
General Purpose Digital I/O
41 SPIM_MOSI
GPIO10
2
O
I/O
-
SPI Master (MOSI) Master Out Slave In Port
General Purpose Digital I/O
43 SPIM_SCK
GPIO9
2
O
I/O
-
SPI Master (SCK) Serial Clock Port
General Purpose Digital I/O
46 SPIM_SS_1n
GPIO13
1
O
I/O
-
SPI Master Slave Select 1, Active Low
General Purpose Digital I/O
47 SPIM_SS_0n
GPIO12
1
O
I/O
-
SPI Master Slave Select 0, Active Low
General Purpose Digital I/O
NO IPCS SPI/FLASH PROGRAMMING (NOTE 16)
TYPE
I/O
40 IPCS_MISO
TIMER16_OUT
GPIO6
2
O
O
I/O
-
SPI Flash Emulation (MISO) Master In Slave Out Port
16-Bit Timer/Counter Match Output/PWM Output
General Purpose Digital I/O
42 IPCS_MOSI
TIMER16_EXT
GPIO5
1
I
I
I/O
-
SPI Flash Emulation (MOSI) Master Out Slave In Port
External Input to 16-bit Timer/Counter
General Purpose Digital I/O
44 IPCS_SCK
TIMER8_EXT
GPIO4
1
I
I
I/O
-
SPI Flash Emulation (SCK) Serial Clock Port
External Input to 8-Bit Timer/Counter
General Purpose Digital I/O
45 IPCS_SSn
LPTIMER_EXT
GPIO3
1
I
I
I/O
-
SPI Flash Emulation Slave Select, Active Low
External Input to Low Power Timer/Counter
General Purpose Digital I/O
55 FLASH_P_ENn
1
I
UP
NO I2C/1-WIRE/SPI SLAVE
PULL DESCRIPTION
Flash Program Enable, Active Low
TYPE
I/O
50 SPIS_MISO
UARTC1_TX
1_WIRE
2
O
O
I/O
PULL DESCRIPTION
-
SPI Slave (MISO) Master In Slave Out Port
CLI UART 1 Transmit
1 Wire Master
51 SPIS_MOSI
UARTC1_RX
GPIO26
1
I
I
I/O
-
SPI Slave (MOSI) Master Out Slave In Port
CLI UART 1 Receive
General Purpose Digital I/O
52 SPIS_SCK
SCL
2
I
I/O
-
SPI Slave (SCK) Serial Clock Port
I2C Serial Clock
53 SPIS_SSn
SDA
2
I
I/O
-
SPI Slave Select, Active Low
I2C Serial Data
NO API UART
TYPE
I/O
PULL DESCRIPTION
66 UART_RX_RTSn
1 (Note 14)
I
-
UART Receive (RTS) Request to Send, Active Low
67 UART_RX_CTSn
1
O
-
UART Receive (CTS) Clear to Send, Active Low
1 (Note 14)
I
-
UART Receive
69 UART_TX_RTSn
1
O
-
UART Transmit (RTS) Request to Send, Active Low
70 UART_TX_CTSn
1 (Note 14)
I
-
UART Transmit (CTS) Clear to Send, Active Low
2
O
-
UART Transmit
68 UART_RX
71 UART_TX
Note 14: These inputs are always enabled and must be driven or pulled to
a valid state to avoid leakage.
Note 15: See also pins 40, 42, 44, and 45 for additional GPIO ports.
Note 16: Embedded programming over the IPCS SPI bus is only avaliable
when RESETn is asserted.
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LTC5800-WHM
Pin Functions
VSUPPLY: System and I/O Power Supply. Provides power
to the chip including the on-chip DC/DC converters. The
digital-interface I/O voltages are also set by this voltage.
Bypass with 2.2µF and 0.1µF to ensure the DC/DC converters operate properly.
VDDPA: PA-Converter Bypass Pin. A 0.47µF cap should be
connected from VDDPA to ground with as short a trace as
feasible. Do not connect anything else to this pin.
VDDA: Analog-Regulator Bypass Pin. A 0.1µF cap should
be connected from VDDA to ground with as short a trace
as feasible. Do not connect anything else to this pin.
VCORE: Core-Regulator Bypass Pin. A 56nF cap should be
connected from VCORE to ground with as short a trace as
feasible. Do not connect anything else to this pin.
VOSC: Oscillator-Regulator Bypass Pin. A 56nF cap should
be connected from VOSC to ground with as short a trace
as feasible. Do not connect anything else to this pin.
VPP: Manufacturing Test port for internal regulator. Do
not connect anything to this pin.
VPRIME: Primary-Converter Bypass Pin. A 0.22µF cap
should be connected from VPRIME to ground with as short
a trace as feasible. Do not connect anything else to this pin.
VBGAP: Bandgap Reference Output. Used for testing and
calibration. Do not connect anything to this pin.
CAP_PA_1P, CAP_PA_1M through CAP_PA_4P, CAP_
PA_4M: Dedicated Power-Amplifier DC/DC Converter
Capacitor Pins. These pins are used when the radio is
transmitting to efficiently convert VSUPPLY to the proper
voltage for the power amplifier. A 56nF cap should be connected between each P and M pair. Trace length should
be as short as feasible.
CAP_PRIME_1P, CAP_PRIME_1M through CAP_
PRIME_4P, CAP_PRIME_4M: Primary DC/DC Converter
Capacitor Pins. These pins are used when the device is
awake to efficiently convert VSUPPLY to the proper voltage
for the three on-chip low-dropout regulators. A 56nF cap
should be connected between each P and M pair. Trace
length should be as short as feasible.
20
ANTENNA: Multiplexed Receiver Input and Transmitter
Output Pin. The impedance presented to the antenna
pin should be 50Ω, single-ended with respect to paddle
ground. To ensure regulatory compliance of the final
product please see the Eterna Integration Guide for filtering
requirements. The antenna pin must not have a DC path to
ground; AC blocking must be included if a DC-grounded
antenna is used.
LNA_ENABLE, RADIO_TX, RADIO_TXn: Control signals
generated by the autonomous MAC supporting the integration of an external LNA/PA. See the Eterna Extended Range
Reference Design for implementation details.
AI_0, AI_1, AI_2, AI_3: Analog Inputs. These pins are
multiplexed to the analog input chain. The analog input
chain, as shown in Figure 8, is software-configurable
and includes a variable-gain amplifier, an offset-DAC for
adjusting input range, and a 10b ADC. Valid input range
is between 0 to 1.8V.
ANALOG INPUT
+
3-BIT
VGA
10-BIT ADC
4-BIT DAC
5800WHM F08
Figure 8. Analog Input Chain
OSC_32K_XOUT: Output Pin for the 32kHz Oscillator.
Connect to 32kHz quartz crystal. The OSC_32K_XOUT
and OSC_32K_XIN traces must be well-shielded from
other signals, both on the same PCB layer and lower PCB
layers, as shown in Figure 9.
OSC_32K_XIN: Input for the 32kHz Oscillator. Connect to 32kHz quartz crystal.The OSC_32K_XOUT and
OSC_32K_XIN traces must be well-shielded from other
signals, both on the same PCB layer and lower PCB layers,
as shown in Figure 9.
OSC_20M_XOUT: Output for the 20MHz Oscillator.
Connect only to a supported 20MHz quartz crystal. The
OSC_20M_XOUT and OSC_20M_XIN traces must be
well-shielded from other signals, both on the same PCB
layer and lower PCB layers, as shown in Figure 9. See the
Eterna Integration Guide for supported crystals.
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Pin Functions
OSC_20M_XIN: Input for the 20MHz Oscillator. Connect
only to a supported 20MHz quartz crystal. The OSC_20M_
XOUT and OSC_20M_XIN traces must be well-shielded
from other signals, both on the same PCB layer and lower
PCB layers, as shown in Figure 9.
RESETn: The asynchronous reset signal is internally pulled
up. Resetting Eterna will result in the ARM Cortex M3
rebooting and loss of network connectivity. Use of this
signal for resetting Eterna is not recommended except
during power-on and in-circuit programming.
RADIO_INHIBIT: RADIO_INHIBIT provide a mechanism
for an external device to temporarily disable radio operation. Failure to observe the timing requirements defined
in the Radio_Inhibit AC Characteristics table, may result
in unreliable network operation. In designs where the
RADIO_INHIBIT function is not needed the input must
either be tied, pulled or actively driven low to avoid excess
leakage.
TMS, TCK, TDI, TDO: JTAG Port Supporting Software
Debug and Boundary Scan. An IEEE Std 1149.1b-1994
compliant Boundary Scan Definition Language (BDSL) file
for the WR QFN72 package can be found here.
SLEEPn: The SLEEPn function is not currently supported
in software. The SLEEPn input must either be tied, pulled
or actively driven high to avoid excess leakage.
UART_RX, UART_RX_RTSn, UART_RX_CTSn, UART_TX,
UART_TX_RTSn, UART_TX_CTSn: The API UART interface
includes bi-directional wake up and flow control. Unused
input signals must be driven or pulled to their inactive state.
TIMEn: Strobing the TIMEn input is the most accurate
method to acquire the network time maintained by Eterna.
Eterna latches the network timestamp with sub-microsecond resolution on the rising edge of the TIMEn signal and
produces a packet on the API serial port containing the
timing information.
UARTC0_RX, UARTC0_TX: The CLI UART provides a
mechanism for monitoring, configuration and control of
Eterna during operation. For a complete description of the
supported commands see the SmartMesh WirelessHART
Mote CLI Guide.
Figure 9. PCB Top Metal Layer Shielding of Crystal Signals
FLASH_P_ENn, IPCS_SSn, IPCS_SCK, IPCS_MISO,
IPCS_SSn: The In-circuit Programming Control System
(IPCS) bus enables in-circuit programming of Eterna’s flash
memory. IPCS_SCK is a clock and should be terminated
appropriately for the driving source to prevent overshoot
and ringing.
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LTC5800-WHM
Operation
The LTC5800 is the world’s most energy-efficient IEEE
802.15.4 compliant platform, enabling battery and energy harvested applications. With a powerful 32-bit ARM
Cortex™-M3, best-in-class radio, flash, RAM and purposebuilt peripherals, Eterna provides a flexible, scalable and
robust networking solution for applications demanding
minimal energy consumption and data reliability in even
the most challenging RF environments.
Shown in Figure 10, Eterna integrates purpose-built
peripherals that excel in both low operating-energy consumption and the ability to rapidly and precisely cycle
between operating and low-power states. Items in the
gray shaded region labeled "Analog Core” correspond to
the analog/RF components.
Power Supply
Eterna is powered from a single pin, VSUPPLY, which
powers the I/O cells and is also used to generate internal
supplies. Eterna’s two on-chip DC/DC converters minimize
energy consumption while the device is awake. To conserve
power the DC/DC converters are disabled when the device
is in low-power state. Power supply conditioning, including
the two integrated DC/DC converters and three integrated
low-dropout regulators, provides excellent rejection of
supply noise. Eterna’s operating supply voltage range is
high enough to support direct connection to lithium-thionyl
chloride (Li-SOCl2) sources and wide enough to support
battery operation over a broad temperature range.
32kHz
DIGITAL CORE
ANALOG CORE
32kHz, 20MHz
TIMERS
SCHED
VOLTAGE REFERENCE
PRIMARY
DC/DC
CONVERTER
SRAM
72kB
CORE REGULATOR
CLOCK REGULATOR
PMU/
CLOCK
CONTROL
FLASH
512kB
RELAXATION
OSCILLATOR
ANALOG REGULATOR
PA
DC/DC
CONVERTER
PoR
FLASH
CONTROLLER
802.15.4
MOD
AES
LPF
DAC
PA
CODE
AUTO
MAC
802.15.4
FRAMING
DMA
802.15.4
DEMOD
SYSTEM
20MHz
PLL
ADC
LIMITER
BPF
PPF
LNA
AGC
RSSI
IPCS
SPI
SLAVE
CLI
UART
(2 PIN)
API
UART
(6 PIN)
ADC
CTRL
10-BIT
ADC
BAT
LOAD
VGA
PTAT
4-BIT
DAC
5800WHM F10
Figure 10. Eterna Block Diagram
22
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Operation
Supply Monitoring and Reset
Eterna integrates a Power-on reset (PoR) circuit. As the
RESETn input pin is nominally configured with an internal
pull-up resistor, no connection is required. For a graceful
shutdown, the software and the networking layers should
be cleanly halted via API commands prior to assertion
of the RESETn pin. See the SmartMesh WirelessHART
Mote API Guide for details on the disconnect and reset
commands. Eterna includes a soft brown-out monitor that
fully protects the flash from corruption in the event that
power is removed while writing to flash. Integrated flash
supervisory functionality, in conjunction with a fault tolerant
file system, yields a robust nonvolatile storage solution.
The use of TIMEn has the advantage of being more accurate. The value of the timestamp is captured in hardware
relative to the rising edge of TIMEn. If an API request is
used, due to packet processing, the value of the timestamp
may be captured several milliseconds after receipt of the
packet. See the TIMEn AC Characteristics section for the
TIMEn function’s definition and specifications.
Time References
Eterna includes three clock sources: an internal relaxation
oscillator, a low power oscillator designed for a 32.768kHz
crystal, and the radio reference oscillator designed for a
20MHz crystal.
Precision Timing
Relaxation Oscillator
Eterna’s unique low power dedicated timing hardware and
timing algorithms provides a significant improvement over
competing 802.15.4 product offerings. This functionality
provides timing precision two to three orders of magnitude
better than any other low-power solution available at the
time of publication. Improved timing accuracy allows motes
to minimize the amount of radio listening time required
to ensure packet reception thereby lowering even further
the power consumed by SmartMesh networks. Eterna’s
patented timing hardware and timing algorithms provide
superior performance over rapid temperature changes,
further differentiating Eterna’s reliability when compared
with other wireless products. In addition, precise timing
enables networks to reduce spectral dead time, increasing
total network throughput.
The relaxation oscillator is the primary clock source for
Eterna, providing the clock for the CPU, memory subsystems, and all peripherals. The internal relaxation oscillator
is dynamically calibrated to 7.3728MHz. The internal relaxation oscillator typically starts up in a few μs, providing
an expedient, low-energy method for duty cycling between
active and low power states. Quick start-up from the doze
state, defined in the State Diagram section, allows Eterna to
wake up and receive data over the UART and SPI interfaces
by simply detecting activity on the appropriate signals.
Application Time Synchronization
In addition to coordinating time slots across the network,
which is transparent to the user, Eterna’s timing management is used to support two mechanisms to share network
time. Having an accurate, shared, network-wide time base
enables events to be accurately time stamped or tasks to
be performed in a synchronized fashion across a network.
Eterna will send a time packet through its serial interface
when one of the following occurs:
32.768kHz Crystal
Once Eterna is powered up and the 32.768kHz crystal
source has begun oscillating, the 32.768kHz crystal remains operational while in the Active state, and is used as
the timing basis when in Doze state. See the State Diagram
section, for a description of Eterna’s operational states.
20MHz Crystal
The 20MHz crystal source provides a frequency reference
for the radio, and is automatically enabled and disabled by
Eterna as needed. Eterna requires specific characterized
20MHz crystal references. See the the Eterna Integration
Guide for a complete list of the currently supported 20MHz
crystals.
Eterna receives an API request to read time
n
The TIMEn signal is asserted
n
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LTC5800-WHM
Operation
Radio
Eterna includes the lowest-power commercially available
2.4GHz IEEE 802.15.4 radio by a substantial margin.
(Please refer to the Radio Specifications section for
power consumption numbers.). Eterna’s integrated power
amplifier is calibrated and temperature-compensated to
consistently provide power at a limit suitable for worldwide
radio certifications. Additionally, Eterna uniquely includes
a hardware-based autonomous MAC that handles precise
sequencing of peripherals, including the transmitter, the
receiver, and advanced encryption standard (AES) peripherals. The hardware-based autonomous media access
controller (MAC) minimizes CPU activity, thereby further
decreasing power consumption.
UARTs
The principal network interface is through the application
programming interface (API) UART. A command-line
interface (CLI) is also provided for support of test and
debug functions. Both UARTs sense activity continuously,
consuming virtually no power until data is transferred and
automatically returning to their lowest power state after
the conclusion of a transfer. The definition for packet
encoding on the API UART interface can be found in the
SmartMesh WirelessHART Mote API Guide and the CLI
command definitions can be found in the SmartMesh
WirelessHART Mote CLI Guide.
API UART Protocols
The API UART supports multiple modes with the goal of
supporting a wide range of companion multipoint control
units (MCUs) while reducing power consumption of the
system. As a general rule, higher serial data rates translate
into lower energy consumption for both endpoints. The API
UART receive protocol includes two additional signals in addition to UART_RX: UART_RX_RTSn and UART_RX_CTSn.
The transmit half of the API UART protocol includes two
additional signals in addition to UART_TX: UART_TX_RTSn
and UART_TX_CTSn. The two supported protocols are
referred to as UART Mode 2 and UART Mode 4. Mode
setting is controlled via the Fuse Table.
24
In the Figures accompanying the protocol descriptions,
signals driven by the companion processor are drawn
in black and signals driven by Eterna are drawn in blue.
UART Mode 2
UART Mode 2 provides the most energy-efficient method
for operating Eterna’s API UART. UART Mode 2 requires
the use of all six UART signals, but does not require
adherence to the minimum inter-packet delay as defined
in the UART AC Characteristics section. UART Mode 2
incorporates edge-sensitive flow control, at either 9600
or 115200 baud. Packets are HDLC encoded with one
stop bit and no parity bit. The flow control signals for
Eterna’s API receive path are shown in Figure 11. Transfers are initiated by the companion processor asserting
UART_RX_RTSn. Eterna then responds by enabling the
UART and asserting UART_RX_CTSn. After detecting the
assertion of UART_RX_CTSn the companion processor
sends the entire packet. Following the transmission of
the final byte in the packet, the companion processor
negates UART_RX_RTSn and waits until the negation of
UART_RX_CTSn before asserting UART_RX_RTSn again.
The flow control signals for Eterna’s API transmit path
are shown in Figure 12. Transfers are initiated by Eterna
asserting UART_TX_RTSn. The companion processor
responds by asserting UART_TX_CTSn when ready to
receive data. After detecting the falling edge of UART_
TX_CTSn Eterna sends the entire packet. Following
the transmission of the final byte in the packet Eterna
negates UART_TX_RTSn and waits until the negation of
UART_TX_CTSn before asserting UART_TX_RTSn again.
The companion processor may negate UART_TX_CTSn
any time after the first byte is transferred provided the
timeout from UART_TX_RTSn to UART_TX_CTSn,
tEND_TX_RTS to TX_CTS is met.
UART_RX_RTSn
UART_RX_CTSn
UART_RX
BYTE 0
BYTE 1
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Figure 11. UART Mode 2 Receive Flow Control
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UART_TX_RTSn
UART_TX_CTSn
UART_TX
BYTE 0
BYTE 1
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Figure 12. UART Mode 2 Transmit Flow Control
packet. After detecting a logic ‘0’ on UART_TX_CTSn Eterna
sends the entire packet. Following the transmission of the
final byte in the packet Eterna negates UART_TX_RTSn
and waits for a minimum period defined in the UART AC
Characteristics section before asserting UART_TX_RTSn
again.
UART_TX_RTSn
For details on the timing of the UART protocol, see the
UART AC Characteristics section.
UART_TX_CTSn
CLI UART
UART_TX
BYTE 0
BYTE 1
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Figure 13. UART Mode 4 Transmit Flow Control
UART Mode 4
UART Mode 4 incorporates level-sensitive flow control
on the TX channel and requires no flow control on the
RX channel, supporting both 9600 and 115200 baud.
The use of level-sensitive flow control signals enables
data rates above 9600 baud with the option of using a
reduced set of the flow control signals; however, Mode
4 has specific limitations. First, The use of the RX flow
control signals (UART_RX_RTSn and UART_RX_CTSn)
for Mode 4 are optional provided the use is limited to the
industrial temperature range (–40°C to 85°C); otherwise,
the flow control is mandatory. If RX flow control signals
are not used, UART_RX_RTSn should be tied to VSUPPLY
(inactive) and UART_RX_CTSn should be left unconnected.
Second, unless the companion processor is always ready
to receive a packet, the companion processor must negate
UART_TX_CTSn prior to the end of the current packet.
Failure to negate UART_TX_CTSn prior to the end of a
packet may result in back to back packets. Third , the
companion processor must wait at least tRX_RTS to RX_CTS
between transmitting packets on UART_RX. See the UART
AC Characteristics section for complete timing specifications. Packets are HDLC encoded with one stop bit and
no parity bit. The flow control signals for the TX channel
are shown in Figure 13. Transfers are initiated by Eterna
asserting UART_TX_RTSn. The UART_TX_CTSn signal
may be actively driven by the companion processor when
ready to receive a packet or UART_TX_CTSn may be tied
low if the companion processor is always ready to receive a
The command line interface (CLI) UART port is a two
wire protocol (TX and RX) that operates at a fixed 9600
baud rate with one stop bit and no parity. The CLI UART
interface is intended to support command line instructions
and response activity.
Autonomous MAC
Eterna was designed as a system solution to provide a
reliable, ultralow power, and secure network. A reliable
network capable of dynamically optimizing operation
over changing environments requires solutions that are
far too complex to completely support through hardware
acceleration alone. As described in the Precision Timing
section, proper time management is essential for optimizing
a solution that is both low power and reliable. To address
these requirements Eterna includes the Autonomous MAC,
which incorporates a co-processor for controlling all of
the time-critical radio operations. The Autonomous MAC
provides two benefits: first, preventing variable software
latency from affecting network timing and second, greatly
reducing system power consumption by allowing the CPU
to remain inactive during the majority of the radio activity.
The Autonomous MAC, provides software-independent
timing control of the radio and radio-related functions,
resulting in superior reliability and exceptionally low power.
Security
Network security is an often overlooked component of
a complete network solution. Proper implementation
of security protocols is significant in terms of both engineering effort and market value in an OEM product.
Eterna system solutions provide a FIPS-140 compliant
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LTC5800-WHM
Operation
encryption scheme that includes authentication and encryption at the MAC and network layers with separate keys
for each mote. This not only yields end-to-end security,
but if a mote is somehow compromised, communication
from other motes is still secure. A mechanism for secure
key exchange allows keys to be kept fresh. To prevent
physical attacks, Eterna includes hardware support for
electronically locking devices, thereby preventing access
to Eterna’s flash and RAM memory and thus the keys and
code stored therein. This lock-out feature also provides
a means to securely unlock a device should support of a
product require access. For details see the Board Specific
Configuration Guide.
Temperature Sensor
Eterna includes a calibrated temperature sensor on chip.
The temperature readings are available locally through
Eterna’s serial API, in addition to being available via the
network manager. The performance characteristics of the
temperature sensor can be found in the Typical Performance
Characteristics section.
Radio Inhibit
The RADIO_INHIBIT input enables an external controller to temporarily disable the radio software drivers (for
example, to take a sensor reading that is susceptible to
radio interference). When RADIO_INHIBIT is asserted
the software radio drivers will disallow radio operations
including clear channel assessment, packet transmissions,
or packet receptions. If the current timeslot is active when
RADIO_INHIBIT is asserted the radio will be disabled after
the present operation completes. The Radio Inhibit function is not enabled by default and must be enabled by the
Fuse Table. See the Board Specific Configuration Guide for
details on creating a Fuse Table. For details on the timing
associated with RADIO_INHIBIT see the Radio_Inhibit AC
Characteristics section.
FLASH Data Retention
Eterna contains internal flash (non-volatile memory) to
store calibration results, unique ID, configuration settings
and software images. Flash retention over the operating
temperature range. See the Electrical Characteristics and
Absolute Maximum Ratings sections.
Non destructive storage above the operating temperature
range of –55°C to 105°C is possible; however, this may
result in a degradation of retention characteristics.
The degradation in flash retention for temperatures >105°C
can be approximated by calculating the dimensionless
acceleration factor using the following equation.
⎡⎛ Ea ⎞ ⎛
⎞⎤
1
1
−
⎢⎜ ⎟•⎜
⎟⎥
⎣⎝ k ⎠ ⎝ TUSE +273 TSTRESS +273 ⎠⎦
AF = e
where:
AF = acceleration factor
Ea = activation energy = 0.6eV
k = 8.625 • 10–5eV/°K
TUSE = is the specified temperature retention in °C
TSTRESS = actual storage temperature in °C
Example: Calculate the effect on retention when storing
at a temperature of 125°C.
TSTRESS = 125°C
Flash Programming
This product is provided without software programmed into
the device. OEMs will need to program software images
during development and manufacturing. Eterna’s software
26
images are loaded via the In-Circuit Programming Control
System (IPCS) SPI interface. Sequencing of RESETn and
FLASH_P_ENn, as described in the Flash SPI Slave AC
Characteristics section, places Eterna in a state emulating
a serial flash to support in-circuit programming. Hardware
and software for supporting development and production
programming of devices is described in the Eterna Serial
Programmer Guide. The serial protocol, SPI, and timing parameters are described in the Flash SPI Slave AC
Characteristics section.
TUSE = 85°C
AF = 7.1
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Operation
POWER-ON
RESET
VSUPPLY > PoR
RESETn LOW AND
FLASH_P_ENn LOW
LOAD FUSE
SETTINGS
RESETn LOW AND
FLASH_P_ENn HIGH
SET RESETn HIGH AND
FLASH_P_ENn HIGH
FOR 125µs, THEN
SET RESETn LOW
SERIAL FLASH
EMULATION
RESETn HIGH
AND
FLASH_P_ENn
HIGH
RESET
DEASSERT
RESETn
BOOT
START-UP
ASSERT RESETn
DOZE
ASSERT RESETn
CPU AND
PERIPHERALS
INACTIVE
HW OR PMU EVENT
OPERATION
ASSERT RESETn
CPU
ACTIVE
ACTIVE
CPU
INACTIVE
DEEP SLEEP
LOW POWER SLEEP
COMMAND
INACTIVE
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Figure 14. Eterna State Diagram
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LTC5800-WHM
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So the overall retention of the flash would be degraded
by a factor of 7.1, reducing data retention from 20 years
at 85°C to 2.8 years at 125°C.
State Diagram
In order to provide capabilities and flexibility in addition
to ultra low power, Eterna operates in various states, as
shown in Figure 14. State transitions shown in red are
not recommended.
Fuse Table
FLASH_P_ENn pin is not asserted but RESETn is asserted,
Eterna automatically reduces its energy consumption to
a minimum until RESETn is released. Once RESETn is
de-asserted, Eterna goes through a boot sequence, and
then enters the active state.
Serial Flash Emulation
When both RESETn and FLASH_P_ENn are asserted,
Eterna disables normal operation and enters a mode to
emulate the operation of a serial flash. In this mode, its
flash can be programmed.
Eterna’s Fuse Table is a 2kB page in flash that contains
two data structures. One structure supports hardware
configuration immediately following power-on reset or
the assertion of RESETn. The second structure supports
configuration of software board support parameters.
Fuse Tables are generated via the Fuse Table application
described in the Board Specific Configuration Guide.
Hardware configuration of I/O immediately following poweron reset provides a method to minimize leakage due to
floating nets prior to software configuration. I/O leakage
can contribute hundreds of microamperes of leakage
per input, potentially stressing current limited supplies.
Examples of software board support parameters include
setting of UART modes, clock sources and trim values.
Fuse Tables are loaded into flash using the same software
and in-circuit programmer used to load software images
as described in the Eterna Serial Programmer Guide.
Operation
Start-Up
Doze State
Start-up occurs as a result of either crossing the power-on
reset threshold or asserting RESETn. After the completion of power-on reset or the falling edge of an internally
synchronized RESETn, Eterna loads its Fuse Table which,
as described in the previous section, includes configuring
I/O direction. In this state, Eterna checks the state of the
FLASH_P_ENn and RESETn pins and enters the serial
flash emulation mode if both signals are asserted. If the
28
Once Eterna has completed start-up, Eterna transitions to
the operational group of states (active/CPU active, active/
CPU inactive, and doze). There, Eterna cycles between the
various states, automatically selecting the lowest possible power state while fulfilling the demands of network
operation.
Active State
In the active state, Eterna’s relaxation oscillator is running
and peripherals are enabled as needed. The ARM CortexM3 cycles between CPU-active and CPU-inactive (referred
to in the ARM Cortex-M3 literature as sleep now mode).
Eterna’s extensive use of DMA and intelligent peripherals
that independently move Eterna between active state and
doze state minimizes the time the CPU is active, significantly reducing Eterna’s energy consumption.
The doze state consumes orders of magnitude less current than the active state and is entered when all of the
peripherals and the CPU are inactive. In the doze state
Eterna’s full state is retained, timing is maintained, and
Eterna is configured to detect, wake, and rapidly respond
to activity on I/Os (such as UART signals and the TIMEn
pin). In the doze state the 32.768kHz oscillator and associated timers are active.
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Applications Information
Regulatory and Standards Compliance
Radio Certification
Eterna is suitable for systems targeting compliance with
worldwide radio frequency regulations: ETSI EN 300 328
and EN 300 440 class 2 (Europe), FCC CFR47 Part 15
(US), and ARIB STD-T66 (Japan). Application Programming Interfaces (APIs) supporting regulatory testing are
provided on both the API and CLI UART interfaces. The
Eterna Certification User Guide provides:
This product has been specifically designed to utilize
RoHS-compliant materials and to eliminate or reduce the
use of restricted materials to comply with 2002/95/EC.
The RoHS-compliant design features include:
RoHS-compliant solder for solder joints
n
RoHS-compliant base metal alloys
n
RoHS-compliant precious metal plating
n
RoHS-compliant cable assemblies and connector
choices
n
Reference information required for certification
n
Lead-free QFN package
Test plans for common regulatory test cases
n
Example CLI calls
n
Sample manual language and example label
n
n
Halogen-free mold compound
n
RoHS-compliant and 245°C re-flow compatible
n
Compliance to Restriction of Hazardous Substances
(RoHS)
Restriction of Hazardous Substances (RoHS) is a directive
that places maximum concentration limits on the use of
cadmium (Cd), lead (Pb), hexavalent chromium (Cr +6),
mercury (Hg), Polybrominated Biphenyl (PBB), and Polybrominated Diphenyl Ethers (PBDE). Linear Technology is
committed to meeting the requirements of the European
Community directive 2002/95/EC.
Note: Customers may elect to use certain types of leadfree solder alloys in accordance with the European Community directive 2002/95/EC. Depending on the type of
solder paste chosen, a corresponding process change to
optimize reflow temperatures may be required.
Soldering Information
Eterna is suitable for both eutectic PbSn and RoHS-6 reflow.
The maximum reflow soldering temperature is 260°C. A
more detailed description of layout recommendations, assembly procedures and design considerations is included
in the Eterna Integration Guide.
Related Documentation
TITLE
LOCATION
DESCRIPTION
SmartMesh WirelessHART User’s Guide
http://www.linear.com/docs/41887
The user’s guide provides theory of operation, and details of the
services supported.
SmartMesh WirelessHART Mote API Guide
http://www.linear.com/docs/41893
Definitions of the command line interface commands available
over the API UART
SmartMesh WirelessHART Mote CLI Guide
http://www.linear.com/docs/41892
Definitions of the command line interface commands available
over the CLI UART
Eterna Integration Guide
http://www.linear.com/docs/41874
Recommended practices for designing with the LTC5800
Eterna Serial Programmer Guide
http://www.linear.com/docs/41876
User’s guide for the Eterna Serial programmer used for in circuit
programming of the LTC5800
Board Specific Configuration Guide
http://www.linear.com/docs/41875
User’s guide for the Eterna Board Specific Configuration
application, used to configure the board specific parameters
Eterna Certification User Guide
http://www.linear.com/docs/42918
The essential documentation necessary to complete radio
certifications, including examples for common test cases
5800whmfa
For more information www.linear.com/LTC5800-WHM
29
LTC5800-WHM
Package Description
Please refer to http://www.linear.com/product/LTC5800-WHM#packaging/ for the most recent package drawings.
WR Package
72-Lead QFN (10mm × 10mm)
Package
(Reference LTC DWGWR
# 05-08-1930
Rev A)
72-Lead QFN (10mm × 10mm)
(Reference LTC DWG # 05-08-1930 Rev A)
0°–14° (×4)
0.65 REF
10.50 ±0.05
6.00 ±0.15
MAX
1.0mm
0.02
8.90 ±0.05
8.50 REF
(4 SIDES)
0.20
REF
6.00 ±0.15
0.50
DETAIL A
0.25 ±0.05
0.50 BSC
0.8 ±0.05
0.60 MAX
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.10 M C A B
0.0.5 M C
0.15 C
10.00 BSC
B
9.75 BSC
B
0.60
MAX
b
0.25 ±0.05
DETAIL B
0.5 ±0.1
6.00 ±0.15
55
72
54
1
PIN 1
10.00 9.75
BSC BSC
6.00 ±0.15
37
0.15 C
18
36
R0.300
TYP
C
0.50 BSC
19
DETAIL B
WR72 0213 REV A
DETAIL A
0.10 C
0.10 C
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220
2. DIMENSION “b” APPLIES TO METALIZED TERMINAL AND IS MEASURED BETWEEN
0.15mm AND 0.30mm FROM THE TERMINAL TIP. IF THE TERMINAL HAS OPTIONAL
RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION B SHOULD NOT BE
MEASURED IN THAT RADIUS AREA
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. DRAWING NOT TO SCALE
COMPONENT
LTCXXXXXX
SEATING PLANE
PIN “A1”
TRAY PIN 1
BEVEL
30
PACKAGE IN TRAY LOADING ORIENTATION
5800whmfa
For more information www.linear.com/LTC5800-WHM
LTC5800-WHM
Revision History
REV
DATE
DESCRIPTION
A
12/15
Added H-grade ordering information and product specifications.
PAGE NUMBER
4, 5, 25
5800whmfa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
its circuits as described
herein will not infringe on existing patent rights.
For moreofinformation
www.linear.com/LTC5800-WHM
31
LTC5800-WHM
Typical Application
Mesh Network Thermistor
TADIRAN TL-5903
Li-SOCI2
100pF
LTC5800-WHM
3.3nH
ANTENNA
1pF
56nF
56nF
56nF
56nF
56nF
0.22µF
0.1µF
56nF
56nF
LT6654-2.048
0.1µF
VIN
PA08 (GP08)
47µF
CAP_PA_2M
CAP_PA_3P
5k
0.1%
VDDANA
CAP_PRIME_1P
CAP_PRIME_1M
CAP_PRIME_2P
UART_TX
UART_TX_RTSn
UART_TX_CTSn
UART_RX
UART_RX_RTSn
UART_RX_CTSn
1000pF
PA15 (USART1_RXD)
PA17 (EXTINT2)
PA05 (AD1)
PA13 (GPO13)
VDDOUT
VDDCORE
47µF
0.1µF
CAP_PRIME_3M
CAP_PRIME_4P
10k, 0.2C
OMEGA 44006
5k
0.1%
1000pF
PA16 (USART1_TXD)
PA14 (GPIO14)
PA18 (EXTINT3)
CAP_PRIME_2M
CAP_PRIME_3P
GND1
PA04 (AD0)
0.1µF
CAP_PA_4M
0.1µF
GND2
0.1µF
FB
CAP_PA_3M
CAP_PA_4P
VOUT
0.1µF
VDDIO
CAP_PA_1M
CAP_PA_2P
0.47µF
56nF
47µF
CAP_PA_1P
VDDPA
56nF
VDDIN
2.2µF
1pF
56nF
ATMEL SAM4L2
2.2µH
VSUPPLY
5k
0.1%
ADVREFP
XOUT32
32.768kHz
GND
XIN32
CAP_PRIME_4M
VPRIME
VDDA
RT = 5k • AI_0 / (2 • AI_1 – AI_0)
T(°C) = 1 / {A + B [Ln(RT)] + C[Ln(RT)]3} – 273.15
A = 1.032 • 10–3
B = 2.387 • 10–4
C = 1.580 • 10–7
DISC_20M_XOUT
20MHz
VCORE
OSC_20M_XIN
VOSC
OSC_32K_XOUT
32.768kHz
GND
OSC_32K_XIN
5800WHM TA02
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTP5903IPC-WHRB
WirelessHART Embedded 250 Mote Manager
Manages Networks of Up to 250 SmartMesh WirelessHart Nodes
LTP5901-WHMA
66-Lead WirelessHART Mote PCB Module with Chip
Antenna
Includes Modular Radio Certification in the United States, Canada, Europe,
Japan, South Korea, Taiwan, India, Australia and New Zealand
LTP5902-WHMA
66-Lead WirelessHART Mote PCB Module with
MMCX Antenna Connector
Includes Modular Radio Certification in the United States, Canada, Europe,
Japan, South Korea, Taiwan, India, Australia and New Zealand
LT6654-2.048
Precision High Output Drive Low Noise Reference
1.6ppm Peak-to-Peak Noise (0.1Hz to 10Hz, Sink/Source ±10mA,
5ppm/°C Max Drift, 2.048 V output
LTC2379-18
18-Bit,1.6Msps/1Msps/500ksps/250ksps Serial, Low 2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC
Power ADC
LTC3388-1/
LTC3388-3
20V High Efficiency Nanopower Step-Down
Regulator
860nA IQ in Sleep, 2.7V to 20V Input, VOUT = 1.2V to 5.0V, Enable and
Standby Pins
LTC3588-1
Piezoelectric Energy Generator with Integrated High
Efficiency Buck Converter
VIN = 2.7V to 20V, VOUT(MIN) = Fixed to 1.8V/2.5V/3.3V/3.6V, IQ = 0.95μA,
3mm × 3mm DFN-10 and MSOP-10E Packages
LTC3108-1
Ultralow Voltage Step-Up Converter and Power
Manager
VIN = 0.02V to 1V, VOUT = 2.5V/3V/3.7V/4.5V Fixed, IQ = 6μA, 3mm × 4mm
DFN-12 and SSOP-16 Packages
LTC3459
Micropower Synchronous Boost Converter
VIN = 1.5V to 5.5V, VOUT(MAX) = 10V, IQ = 10μA, 2mm × 2mm DFN,
2mm × 3mm DFN or SOT-23 Package
32 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA For
95035-7417
more information www.linear.com/LTC5800-WHM
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC5800-WHM
5800whmfa
LT 1215 REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2013