High Speed ADC USB FIFO Evaluation Kit HSC-ADC-EVALB FEATURES FUNCTIONAL BLOCK DIAGRAM Buffer memory board for capturing digital data used with high speed ADC evaluation boards to simplify evaluation 32 kB FIFO depth at 133 MSPS (upgradable) Measures performance with ADC Analyzer™ Real-time FFT and time domain analysis Analyze SNR, SINAD, SFDR, and harmonics Simple USB port interface (2.0) Supporting ADCs with serial port interfaces (SPI) On-board regulator circuit, no power supply required 6 V, 2 A switching power supply included Compatible with Windows 98 (2nd ed.), Windows 2000, Windows ME, and Windows XP STANDARD USB 2.0 SINGLE OR DUAL HIGH-SPEED ADC EVALUATION BOARD FILTERED ANALOG INPUT CHB FIFO, 32k, 133MHz n ADC TIMING CIRCUIT SPI The high speed ADC FIFO evaluation kit includes the latest version of ADC Analyzer and a buffer memory board to capture blocks of digital data from the Analog Devices, Inc., high speed analog-to-digital converter (ADC) evaluation boards. The FIFO board is connected to the PC through a USB port and is used with ADC Analyzer to quickly evaluate the performance of high speed ADCs. Users can view an FFT for a specific analog input and encode rate to analyze SNR, SINAD, SFDR, and harmonic information. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC. The HSC-ADC-EVALB-DCZ can be used with single and multichannel ADCs and converters with demultiplexed digital outputs. PRODUCT HIGHLIGHTS 1. Easy to Set Up. Connect the included power supply and signal sources to the two evaluation boards. Then connect to the PC and instantly evaluate the performance. USB CTLR SPI CLOCK INPUT PRODUCT DESCRIPTION +3.0V REG CHA FIFO, 32k, 133MHz n CLOCK CIRCUIT PS 120-PIN CONNECTOR 05870-001 Analog signal source and antialiasing filter Low jitter clock source High speed ADC evaluation board and ADC data sheet PC running Windows 98 (2nd ed.), Windows 2000, Windows ME, or Windows XP Latest version of ADC Analyzer USB 2.0 (USB 1.1-compatible) port recommended REG LOGIC PS EQUIPMENT NEEDED HSC-ADC-EVALB-DCZ Figure 1. 2. ADIsimADC™. ADC Analyzer supports virtual ADC evaluation using Analog Devices proprietary behavioral modeling technology. This allows rapid comparison between multiple ADCs, with or without hardware evaluation boards. For more information, see the AN-737 Application Note at www.analog.com/ADIsimADC. 3. USB Port Connection to PC. The PC interface is a USB 2.0 (1.1-compatible) connection. A USB cable is provided in the kit. 4. FIFO of 32 kB. The FIFO stores data from the ADC for processing. A pin-compatible FIFO family is used for easy upgrading. 5. Up to 133 MSPS Encode Rate on Each Channel. Single-channel ADCs with encode rates of up to 133 MSPS can be used with the FIFO board. Multichannel and demultiplexed output ADCs can also be used with the FIFO board with clock rates up to 266 MSPS. 6. Supports ADC with Serial Port Interface (SPI). Some ADCs include a feature set that can be changed via the SPI. The FIFO supports these features through the existing USB connection to the computer without requiring additional cabling. Rev. A Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards are supplied “as is” and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not authorized to be used in life support devices or systems. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved. HSC-ADC-EVALB TABLE OF CONTENTS Features .............................................................................................. 1 Equipment Needed........................................................................... 1 Connecting to the HSC-ADC-AD922xFFA or HSC-ADCAD9283FFA Adapter Boards .......................................................8 Product Description......................................................................... 1 Connecting to the HSC-ADC-DEMUX Adapter Board .........8 Product Highlights ........................................................................... 1 Connecting ADC Evaluation Boards with Double Row Connectors .....................................................................................8 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Quick Start Guide: FIFO Evaluation Board .................................. 3 Requirements ................................................................................ 3 Quick Start Steps .......................................................................... 3 Quick Start Guide: Virtual Evaluation Using ADIsimADC ....... 4 Requirements ................................................................................ 4 Quick Start Steps .......................................................................... 4 FIFO 4.1 Data Capture Board Features ......................................... 5 FIFO 4.1 Supported ADC Evaluation Boards .......................... 6 Theory of Operation ........................................................................ 7 Clocking Description................................................................... 7 SPI Description............................................................................. 7 Clocking with Interleaved Data.................................................. 7 Connecting to the HSC-ADC-FPGA-8Z.................................. 8 Upgrading FIFO Memory............................................................8 Jumpers ...............................................................................................9 Default Settings..............................................................................9 Evaluation Board ............................................................................ 11 Power Supplies ............................................................................ 11 Connection and Setup ............................................................... 11 FIFO Schematics and PCB Layout ............................................... 12 Pin Definitions/Assignments.................................................... 12 Schematics................................................................................... 13 PCB Layout ................................................................................. 20 Ordering Information.................................................................... 22 Bill of Materials........................................................................... 22 Ordering Guide .......................................................................... 24 ESD Caution................................................................................ 24 REVISION HISTORY 7/07—Rev. 0 to Rev. A Deleted HSC-ADC-EVALB-SC........................................Universal Changes to Table 1............................................................................ 8 Added the Connecting to the HSC-ADC-AD922xFFA or HSC-ADC-AD9283FFA Adapter Boards Section .................. 8 Changes to the Connecting to the HSC-ADC-DEMUX Adapter Board Section .......................... 8 Added the Connecting ADC Evaluation Boards with Double Row Connectors Section...................................... 8 Added Figure 4 and Figure 5........................................................... 8 Added Figure 7................................................................................ 12 Changes to Schematics................................................................... 13 Changes to Bill of Materials .......................................................... 22 Changes to Ordering Guide .......................................................... 24 2/06—Revision 0: Initial Version Rev. A | Page 2 of 24 HSC-ADC-EVALB QUICK START GUIDE: FIFO EVALUATION BOARD 6. REQUIREMENTS • • • • • • • FIFO evaluation board, ADC Analyzer, and USB cable High speed ADC evaluation board and ADC data sheet Power supply for ADC evaluation board Analog signal source and appropriate filtering Low jitter clock source applicable for specific ADC evaluation, typically <1 ps rms PC running Windows® 98 (2nd ed.), Windows 2000, Windows ME, or Windows XP PC with a USB 2.0 (USB 1.1-compatible) port recommended The first time, the Found New Hardware Wizard opens with the text message This wizard helps you install software for…Pre-FIFO 4.1. Click the recommended install, and go to the next screen. A hardware installation warning window displays. Click Continue Anyway. The next window that opens finishes the pre-FIFO 4.1 installation. Click Finish. The Found New Hardware Wizard dialog box opens for the second time, but with the text message This wizard helps you install software for…Analog Devices FIFO 4.1 displayed. Click the recommended install, and go to the next screen. Again, a hardware installation warning window displays. Click Continue Anyway. Then click Finish on the next two windows. This completes the installation. QUICK START STEPS Note that you need administrative rights for the Windows operating systems during the entire easy start procedure. It is recommended to complete all steps before reverting to a normal user mode. 1. 2. Install ADC Analyzer from the CD provided in the FIFO evaluation kit or download the latest version from the Web. For the latest software updates, check the Analog Devices website at www.analog.com/hsc-FIFO. Connect the FIFO evaluation board to the ADC evaluation board. If an adapter is required, insert the adapter between the ADC evaluation board and the FIFO board. Connect the evaluation board to the bottom two rows of the 120-pin connector, closest to the installed IDT FIFO chip. If using an ADC with a SPI interface, remove the two 4-pin corner keys so that the third row can be connected. 3. Connect the provided USB cable to the FIFO evaluation board and to an available USB port on the computer. 4. Refer to Table 4 to make necessary jumper changes. Most evaluation boards can be used with the default settings. 5. After verification of the first four steps, connect the appropriate power supplies to the ADC evaluation boards. The FIFO evaluation board is supplied with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply end to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at J301. Refer to the instructions included in the ADC data sheet (at www.analog.com) for more information about the ADC evaluation board’s power supply and other requirements. Once the cable is connected to both the computer and the FIFO board and power is supplied, the USB drivers start to install. To complete the total installation of the FIFO drivers, you need to complete the new hardware sequence two times. 7. (Optional) Verify in the device manager that Analog Devices FIFO 4.1 is listed under the USB hardware. 8. Apply power to the evaluation board and check the voltage levels at the board level. 9. Connect the appropriate analog input (which should be filtered with a band-pass filter) and low jitter clock signal. Make sure that the evaluation boards are powered on before connecting the analog input and clock. 10. Start ADC Analyzer. 11. Choose an existing configuration file for the ADC evaluation board or create a new one. 12. Click Time Data (the leftmost button under the menus) in ADC Analyzer. A reconstruction of the analog input is displayed. If the expected signal does not appear, or if there is only a flat red line, refer to the ADC Analyzer data sheet at www.analog.com/hsc-FIFO for more information. Rev. A | Page 3 of 24 HSC-ADC-EVALB QUICK START GUIDE: VIRTUAL EVALUATION USING ADIsimADC REQUIREMENTS • Complete installation of ADC Analyzer, Version 4.8.2 or later. • Download ADIsimADC product model files for the desired converter. (Models are not installed with the software, but they can be downloaded from the ADIsimADC Virtual Evaluation Board website at no charge.) Note that no hardware is required to virtually evaluate an ADC using ADIsimADC. However, if you wish to compare these results to those using a real evaluation board, you can easily switch between the two, as outlined in the following Quick Start Steps section. 5. In the ADC Modeling dialog box, click the Device tab and then click … (Browse), which is the button adjacent to the open box in the dialog window. This opens a file browser and displays all of the models found in the default directory: c:\program files\adc_analyzer\models. If no model files are found, follow the on-screen directions or repeat Step 1 to install the available models. If you have saved the models somewhere other than the default location, use the browser to navigate to that location and select the file of interest. 6. From the menu, click Config > FFT. In the FFT Configuration dialog box, ensure that the Encode Frequency is set to a valid rate for the simulated device under test. If set too low or too high, the model will not run. 7. Once a model has been selected, information about the model displays on the Device tab of the ADC Modeling dialog box. After ensuring that you have selected the correct model, click the Input tab. This lets you configure the input to the model. Click either Sine Wave or Two Tone for the input signal. 8. Click Time Data (the leftmost button under the pull-down menus). A reconstruction of the analog input is displayed. The model can now be used as a standard evaluation board would be. 9. The model supports additional features not found when testing a standard evaluation board. When using the modeling capabilities, it is possible to sweep either the analog amplitude or the analog frequency. Consult the ADC Analyzer User Manual at www.analog.com/hsc-FIFO for more information. QUICK START STEPS 1. Visit www.analog.com/ADIsimADC and download the ADC model files of interest to a local drive. The default location is c:\program files\adc_analyzer\models. 2. Start ADC Analyzer (see the ADC Analyzer User Manual). 3. From the menu, click Config > Buffer > Model as the buffer memory. In effect, the model functions in place of the ADC and data capture hardware. 4. After selecting the model, click Model (located next to the Stop button) to select and configure which converter is to be modeled. A dialog box appears in the workspace, where you can select and configure the behavior of the model. Rev. A | Page 4 of 24 HSC-ADC-EVALB FIFO 4.1 DATA CAPTURE BOARD FEATURES 6V SWITCHING POWER SUPPLY CONNECTION IDT72V283 32k × 16-BIT 133MHz FIFO TIMING ADJUSTMENT JUMPERS ON-BOARD +3.3V REGULATOR 120-PIN CONNECTOR (PARALLEL CMOS INPUTS) OPTIONAL POWER CONNECTION IDT72V283 32k × 16-BIT 133MHz FIFO USB CONNECTION TO COMPUTER OPTIONAL SERIAL PORT INTERFACE CONNECTOR RESET SWITCH WHEN ENCODE RATE IS INTERRUPTED Figure 2. FIFO Components (Top View) Rev. A | Page 5 of 24 µCONTROLLER CRYSTAL CLOCK = 24MHz, OFF DURING DATA CAPTURE 05870-002 OPEN SOLDER MASK ON ALL DATA AND CLOCK LINES FOR EASY PROBING HSC-ADC-EVALB 120-PIN CONNECTOR (PARALLEL CMOS INPUTS) TIMING ADJUSTMENT JUMPERS EPROM TO LOAD USB FIRMWARE CYPRESS Fx2 HIGH SPEED USB 2.0 µCONTROLLER OPTIONAL SERIAL PORT INTERFACE (SPI) CONNECTOR 05870-003 DRIVER CIRCUIT FOR SERIAL PORT INTERFACE (SPI) LINES Figure 3. FIFO Components (Bottom View) FIFO 4.1 SUPPORTED ADC EVALUATION BOARDS All the evaluation boards that can be used with the high speed ADC FIFO evaluation kit can be found at www.analog.com/fifo. Some evaluation boards may require an adapter between the ADC evaluation board output connector and the FIFO input connector. If an adapter is needed, send an email to [email protected] indicating the part number of the adapter, the ADC being used, and contact information. Rev. A | Page 6 of 24 HSC-ADC-EVALB THEORY OF OPERATION The FIFO evaluation board can be divided into several circuits, each of which plays an important part in acquiring digital data from the ADC and allows the PC to upload and process that data. The evaluation kit is based on the IDT72V283 FIFO chip from Integrated Device Technology, Inc. (IDT). The system can acquire digital data at speeds of up to 133 MSPS and data record lengths of up to 32 kB using the HSC-ADC-EVALB-DCZ, which has two FIFO chips and is available to evaluate single and multichannel ADCs or demultiplexed data from ADCs sampling faster than 133 MSPS. A USB 2.0 microcontroller communicating with ADC Analyzer allows for easy interfacing to newer computers using the USB 2.0 (USB 1.1-compatible) interface. The process of filling the FIFO chip or chips and reading the data back requires several steps. First, ADC Analyzer initiates the FIFO chip fill process. The FIFO chips are reset using a master reset signal (MRS). The USB microcontroller is then suspended, which turns off the USB oscillator and ensures that it does not add noise to the ADC input. After the FIFO chips completely fill, the full flags from the FIFO chips send a signal to the USB microcontroller to wake up the microcontroller from suspend. ADC Analyzer waits for approximately 30 ms and then begins the readback process. During the readback process, the acquisition of data from FIFO 1 (U201) or FIFO 2 (U101) is controlled via Signal OEA and Signal OEB. Because the data outputs of both FIFO chips drive the same 16-bit data bus, the USB microcontroller controls the OEA and OEB signals to read data from the correct FIFO chip. From an application standpoint, ADC Analyzer sends commands to the USB microcontroller to initiate a read from the correct FIFO chip, or from both FIFO chips in dual or demultiplexed mode. CLOCKING DESCRIPTION Each channel of the buffer memory requires a clock signal to capture data. These clock signals are normally provided by the ADC evaluation board and are passed along with the data through Connector J104 (Pin 37 for both Channel A and Channel B). If only a single clock is passed for both channels, they can be connected together by Jumper J303. Jumpers J304 and J305 at the output of the LVDS receiver allow the output clock to be inverted by the LVDS receiver. By default, the clock outputs are inverted by the LVDS receiver. The single-ended clock signal from each data channel is buffered and converted to a differential CMOS signal by two gates of a low voltage differential signal (LVDS) receiver, U301. This allows the clock source for each channel to be CMOS, TTL, or ECL. The clock signals are ac-coupled by 0.1 μF capacitors. Potentiometer R312 and Potentiometer R315 allow for finetuning the threshold of the LVDS gates. In applications where fine-tuning the threshold is critical, these potentiometers can be replaced with a higher resistance value to increase the adjustment range. Resistors R301, R302, R303, R304, R311, R313, R314, and R316 set the static input to each of the differential gates to a dc voltage of approximately 1.5 V. At assembly, Solder Jumper J310 to Solder Jumper J313 are set to bypass the potentiometer. For fine adjustment using the potentiometers, the solder jumpers must be removed and R312 and R315 must be populated. U302, an XOR gate array, is included in the design to let users add gate delays to the clock paths of the FIFO memory chips. They are not required under normal conditions and are bypassed at assembly by Jumper J314 and Jumper J315. Jumper J306 and Jumper J307 allow the clock signals to be inverted through an XOR gate. In the default setting, the clocks are not inverted by the XOR gate. These clock paths determine the WRT_CLK1 and WRT_CLK2 signals at each FIFO memory chip (U101 and U201). These timing options should let you choose a clock signal that meets the setup time and hold time requirements to capture valid data. A clock generator can be applied directly to S1 and/or S3. This clock generator should be the same unit that provides the clock for the ADC. These clock paths are ac-coupled so that a sine wave generator can be used. DC bias can be adjusted by R301/R302 and R303/R304. The DS90LV048A differential line receiver is used to square the clock signal levels applied externally to the FIFO evaluation board. The output of this clock receiver can either directly drive the write clock of the IDT72V283 FIFO(s), or first pass through the XOR gate timing circuitry previously described. SPI DESCRIPTION The Cypress IC (U502) supports the HSC SPI standard to allow programming of ADCs that have SPI-accessible register maps. U102 is a buffer that drives the 4-wire SPI (SCLK, SDI, SDO, CSB) through the 120-pin connector (J104) on the third or top row. (Note that CSB1 is the default CSB line used.) J502 is an auxiliary SPI connector that monitors the SPI signals connected directly to the Cypress IC. For more information on this and other functions, consult the user manual titled Interfacing to High Speed ADCs via SPI at www.analog.com/hsc-FIFO. The SPI interface designed on the Cypress IC can communicate with up to five different SPI-enabled devices. The CLK and data lines are common to all SPI devices. The correct device is chosen to communicate by using one of the five active low chip select pins. This functionality is controlled by selecting a SPI channel in the software. CLOCKING WITH INTERLEAVED DATA ADCs with very high data rates can exceed the capability of a single buffer memory channel (~133 MSPS). These converters often demultiplex the data into two channels to reduce the rate Rev. A | Page 7 of 24 HSC-ADC-EVALB required to capture the data. In these applications, ADC Analyzer must interleave the data from both channels to process it as a single channel. The user can configure the software to process the first sample from Channel A, the second from Channel B, and so on, or vice versa. The synchronization circuit included in the buffer memory forces a small delay between the write enable signals (WENA and WENB) being sent to the FIFO memory chips (Pin 1, U101, and U201), ensuring that the data is captured in one FIFO before the other. Jumper J401 and Jumper J402 determine which FIFO receives WENA and which FIFO receives WENB. has a 120-pin, triple row input connector to allow connection with newer ADCs that have SPI. Two examples of connecting FIFO 4.1 to an older style ADC evaluation board are shown in Figure 4 and Figure 5. CONNECTING TO THE HSC-ADC-FPGA-8Z 05870-004 ADCs that have serial LVDS outputs require that another board, that is, the HSC-ADC-FPGA-8Z, be connected between the ADC evaluation board and the FIFO data capture card. This board converts the serial data into parallel CMOS so that the FIFO data capture card can accept the data. Refer to the HSC-ADC-FPGA data sheet at www.analog.com/hsc-FIFO for more detailed information on this board. CONNECTING TO THE HSC-ADC-AD922xFFA OR HSC-ADC-AD9283FFA ADAPTER BOARDS Figure 4. Single-Channel ADC When connecting the HSC-ADC-AD922xFFA or HSC-ADCAD9283FFA adapter board, connect the female connector to the ADC evaluation board, and then connect the male connector to the FIFO board. Next, ensure that the HSC-ADC-AD922xFFA or HSC-ADC-AD9283FFA adapter board connects to the data lines (Row A and Row B) of the FIFO board connector as shown in Figure 4. Email [email protected] for more detailed information about this board. CONNECTING TO THE HSC-ADC-DEMUX ADAPTER BOARD The AD9480 and AD9430 ADCs have parallel LVDS outputs and require another board connected between the ADC evaluation board and the FIFO data capture card. This board converts parallel LVDS to parallel CMOS, using both channels of the FIFO data capture card. Email [email protected] for more detailed information about this board. CONNECTING ADC EVALUATION BOARDS WITH DOUBLE ROW CONNECTORS The HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC (FIFO 4) was the predecessor to the HSC-ADC-EVALB-DCZ (FIFO 4.1) and had only an 80-pin, double row input connector. The FIFO 4.1 05870-005 Older ADC evaluation boards, such as the AD9203, AD9220, AD9226, and AD9283, have different pinouts and therefore require that another board, that is, the HSC-ADC-AD922xFFA or HSC-ADC-AD9283FFA adapter board, be connected between the ADC evaluation board and the FIFO data capture card. This board routes the outputs of the ADC evaluation board to the correct locations on the FIFO board. Figure 5. Dual-Channel ADC UPGRADING FIFO MEMORY The FIFO evaluation board includes two 32 kB FIFOs that are capable of 133 MHz clock signals. Pin-compatible FIFO upgrades are available from Integrated Device Technology. See Table 1 for the IDT part number matrix. Table 1. IDT Part Number Matrix1 Part Number IDT72V283L7-5PF (Default ) IDT72V293L7-5PF IDT72V2103L7-5PF IDT72V2113L7-5PF IDT72V283L6PF IDT72V293L6PF IDT72V2103L6PF IDT72V2113L6PF 1 FIFO Depth 32 kB 64 kB 132 kB 256 kB 32 kB 64 kB 132 kB 256 kB Visit the IDT website for more information. Rev. A | Page 8 of 24 FIFO Speed 133 MHz 133 MHz 133 MHz 133 MHz 166 MHz 166 MHz 166 MHz 166 MHz HSC-ADC-EVALB JUMPERS Use the information in Table 2 and Table 3 to configure the jumpers. On the FIFO evaluation board, Channel A is associated with the bottom IDT FIFO chip, and Channel B is associated with the top IDT FIFO chip (the one closest to the Analog Devices logo). DEFAULT SETTINGS Table 4 lists the jumper settings to configure the data capture board for use with single-channel, multichannel, and interleaving ADCs. The ADC settings are shown in separate columns, as are the settings for the opposite (top) FIFO, U101, for a single-channel ADC. To align the timing properly, some evaluation boards require modifications to these settings. Refer to the Clocking Description section in the Theory of Operation section for more information. Table 2. Jumper Position Descriptions Position In Out Position 1 or Position 3 Description Jumper in place (2-pin header) Jumper removed (2-pin header) Denotes the position of a 3-pin header. Position 1 is marked on the board. Another way to easily configure the jumper settings for various configurations is to first consult ADC Analyzer’s Help menu, selecting About HSC_ADC_EVALB from the menu, in order to determine the appropriate configuration setting for your application. Next, click Setup Default Jumper Wizard and choose the configuration setting that applies to the application of interest. A picture of the FIFO board is displayed for that application, providing a visual example of the correct jumper settings. Table 3. Solder Jumper Position Descriptions Position In Description Solder pads should be connected with a 0 Ω resistor Solder pads should not be connected with a 0 Ω resistor Out Table 4. Jumper Configurations Jumper J303 J304 Single-Channel Settings (Top) 1 In In Single-Channel Settings, Default (Bottom) In In Demultiplexed Settings Out In Dual-Channel Settings Out In J305 In In In In J306 Out Out Out Out J307 Out Out Out Out J310 to J313 J314 In In In In In In In In J315 In In In In J316 J401 In In In In In In In In J402 Out Out Out Out J403 Out Out Out Out J404 In In In In J405 Out Out In Out J406 In In In In Rev. A | Page 9 of 24 Description Position 2 to Position 4, ties write clocks together Position 1 to Position 2, POS3: inverts clock out of DS90 (U301) Position 2 to Position 3, POS3: inverts clock out of DS90 (U301) No invert to encode clock from XOR (U302), 0 Ω resistor No invert to encode clock from XOR (U302), 0 Ω resistor All solder jumpers are shorted with 0 Ω resistors, (bypass level shifting to input of DS90) Position 1 to Position 2, one XOR gate timing delay for top FIFO (U101) Position 1 to Position 2, one XOR gate timing delay for bottom FIFO (U201) Power connected using switching power supply Controls if the top FIFO (U101) receives a write enable before or after bottom FIFO, 0 Ω resistor Controls if the top FIFO (U101) receives a write enable before or after bottom FIFO, 0 Ω resistor Controls if the bottom FIFO (U201) receives a write enable before or after the top FIFO, 0 Ω resistor Controls if the bottom FIFO (U201) receives a write enable before or after the top FIFO, 0 Ω resistor When this jumper is in, WRT_CLK1 is used to create write enable signals for FIFOs, 0 Ω resistor (significant only for interleave mode) WRT_CLK2 is used to create write enable signals for FIFOs, 0 Ω resistor (significant only for interleave mode) HSC-ADC-EVALB Jumper J503 Single-Channel Settings (Top) 1 In Single-Channel Settings, Default (Bottom) In Demultiplexed Settings In Dual-Channel Settings In J504 J505 Out In Out In Out In Out In J506 J602 J603 Out Out In Out Out In Out Out In Out Out In 1 Description Connect enable empty flag of top FIFO (U101) to USB MCU, 0 Ω resistor N/A Connect enable full flag of top FIFO (U101) to USB MCU, 0 Ω resistor N/A N/A N/A Some jumpers can be a 0 Ω resistor instead of a physical jumper. This is indicated in Table 4 in the jumper description column. Rev. A | Page 10 of 24 HSC-ADC-EVALB EVALUATION BOARD to the PCB at J301. On the PC board, the 6 V supply is then fused and conditioned before connecting to the low dropout 3.3 V linear regulator that supplies the proper bias to the entire board. The FIFO provides all of the support circuitry required to accept two channels of an ADC’s digital parallel CMOS outputs. Each of the various functions and configurations can be selected by properly connecting various jumpers (see Table 4). When using this in conjunction with an ADC evaluation board, it is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the ultimate performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. When operating the evaluation board in a nondefault condition, J316 can be removed to disconnect the switching power supply. This enables the user to bias the board independently. Use P302 to connect an independent supply to the board. A 3.3 V supply is needed with at least a 1 A current capability. CONNECTION AND SETUP The FIFO board has a 120-pin (three rows of 40 pins each) connector that accepts two 16-bit channels of parallel CMOS inputs (see Figure 6). For those ADC evaluation boards that have only an 80-pin (two rows of 40 pins each) connector, it is pertinent that the lower two rows of the FIFO’s triple row connector be connected in order for the data to pass to either FIFO channel correctly. The top, or third row, is used to pass SPI signals across to the adjacent ADC evaluation board that supports this feature. See Figure 8 to Figure 18 for complete schematics and layout diagrams. POWER SUPPLIES The FIFO board is supplied with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER HSC-ADC-EVALB-DCZ FIFO DATA CAPTURE BOARD EVALUATION BOARD BAND-PASS FILTER XFMR INPUT CLK CHA PARALLEL CMOS OUTPUTS SPI PC RUNNING ADC ANALYZER USB CONNECTION SPI SPI Figure 6. Example Setup Using Quad ADC Evaluation Board and FIFO Data Capture Board Rev. A | Page 11 of 24 05870-006 ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER CHB PARALLEL CMOS OUTPUTS + VCC SWITCHING POWER SUPPLY – GND 3.3V 6V DC 2A MAX HSC-ADC-EVALB FIFO SCHEMATICS AND PCB LAYOUT PIN DEFINITIONS/ASSIGNMENTS CHANNEL B HEAD-ON VIEW (TOP) CHANNEL A SPI CONNECTIONS DIGITAL DATA BIT CONNECTIONS GROUND CONNECTIONS 40 C B A CHANNEL B CHANNEL A CONNECT ONLY BOTTOM TWO ROWS FOR ADCs THAT DO NOT SUPPORT SPI. HEAD-ON VIEW (BOTTOM) SPI CONTROL LINES GROUND CONNECTIONS DIGITAL DATA BITS OPTIONAL CONTROL LINES CLOCK LINES Figure 7. FIFO 4.1 Triple Row, 120-Pin Input Header Rev. A | Page 12 of 24 05870-007 1 HSC-ADC-EVALB SCHEMATICS ALLOW Fx2 TO CONTROL FIFO’S OUTPUT WIDTH RCLK REN1 61 EF1_TF FF1_TF REN RCLK 63 RM 64 EF/OR 66 65 PFM VCC PAE 67 68 IP 70 69 BE HF FSEL1 71 72 FSEL0 73 OW 74 PAF 75 FF/IR 76 FWFT/SI 77 LD 78 MRS 79 PRS GND D11 Q10 D10 VCC D9 Q9 60 59 OE1 58 57 Q17 56 Q16 55 54 53 Q15 52 Q14 51 50 Q13 49 Q12 48 47 Q11 46 45 Q10 44 Q9 42 Q8 41 Q7 40 Q6 43 Q6 Q5 GND 39 38 Q5 Q4 37 36 Q4 Q3 35 Q3 Q2 34 C107 0.1µF 33 C106 0.1µF Q2 32 22 D1_6 U101 VCC Q7 GND VCC Q1 Q8 Q0 D8 D7 20 D12 31 19 Q11 Q1 D1_8 GND Q0 18 GND GND D1_9 D13 D0 17 Q13 Q12 30 D1_10 VCC D14 29 16 D15 D1 D1_11 D16 D1_0 15 Q14 IDT72V283 TQFP 80 TOP FIFO CHANNEL B D2 D1_12 VCC 28 14 Q15 27 13 D17 D1_1 D1_13 GND D1_2 12 GND D3 D1_14 GND 26 11 IW D4 D1_15 9 Q16 D1_3 10 DNC D5 D1_16 R108 DNP Q17 25 8 VCC 24 D1_17 VCC D1_4 VCC DNC GND 7 OE D1_5 6 RT SEN D6 5 WEN 23 2 4 VCC C101 0.1µF C102 0.1µF C103 0.1µF C104 0.1µF C105 0.1µF Figure 8. PCB Schematic Rev. A | Page 13 of 24 C108 0.1µF C109 0.1µF 05870-008 R109 DNP MRS WRT_CLK1 80 1 WCLK WEN1 21 E102 3 WRT_CLK1 R102 10kΩ VCC D1_7 POPULATE WITH PIN SOCKET E101 R101 0Ω 62 PC2: TRISTATED, NORMAL 16-BIT DATAPATH PC2: DRIVEN HIGH, 9-BIT OUTPUT ALLOWS READING 18 BITS IN TWO READS. PC2 HSC-ADC-EVALB CMOS INPUTS J104:1 CLKB J104:2 A1 A2 DUT_CLK1 A3 MSB CHB LSB CLKA A4 D1_15 A5 D1_14 A6 D1_13 A7 D1_12 A8 D1_11 A9 D1_10 A10 D1_9 A11 D1_8 A12 D1_7 A13 D1_6 A14 D1_5 A15 D1_4 A16 D1_3 A17 D1_2 A18 D1_1 A19 D1_0 A20 CTRL_B D1_15 D1_14 D1_13 D1_12 D1_11 D1_10 D1_9 D1_8 D1_7 D1_6 D1_5 D1_4 D1_3 D1_2 D1_1 D1_0 CHA LSB B1 D1_17 B2 D1_16 C4 C5 B6 C6 B7 C7 B8 C8 B9 C9 B10 C10 B11 C11 B12 C12 B13 C13 B14 C14 B15 C15 B16 C16 B17 C17 B18 C18 C19 B19 D2_17 A22 B22 D2_16 D2_15 A25 D2_14 A26 D2_13 A27 D2_12 A28 D2_11 A29 D2_10 A30 D2_9 A31 D2_8 A32 D2_7 A33 D2_6 A34 D2_5 A35 D2_4 A36 D2_3 A37 D2_2 A38 D2_1 A39 D2_0 A40 CTRL_D D2_15 D2_14 D2_13 D2_12 D2_11 D2_10 D2_9 D2_8 D2_7 D2_6 D2_5 D2_4 D2_3 D2_2 D2_1 D2_0 CTRL_D C2 B5 B21 A24 D1_16 C1 C3 A21 DUT_CLK2 D1_17 B4 CTRL_A CTRL_B PLACEMENT OF HEADER KEY HERE J104:3 B3 B20 A23 MSB TEST POINTS CTRL_A D2_17 D2_16 C20 C21 C22 B23 C23 B24 C24 B25 C25 B26 C26 B27 C27 B28 C28 B29 C29 16 1 18 B30 C30 15 2 17 B31 C31 14 3 16 B32 C32 13 4 15 B33 C33 12 5 14 B34 C34 11 6 13 B35 C35 10 7 12 B36 C36 8 11 B37 C37 B38 C38 VCC 19 SDO 9 22Ω RZ101 20 OE2 VCC O0 I0 O1 O2 OE1 I1 U102 74VHC541M I2 O3 I3 O4 I4 O5 I5 O6 I6 O7 I7 GND 10 1 2 3 4 CSB1 CSB2 5 6 7 8 SDI SCLK CSB3 CSB4 9 R103 10kΩ R104 10kΩ C39 B39 B40 ALL SPI LABELS ARE WITH RESPECT TO THE DUT. CTRL_C CTRL_C C40 PLACEMENT OF HEADER KEY HERE Figure 9. PCB Schematic (Continued) Rev. A | Page 14 of 24 05870-009 TEST POINTS HSC-ADC-EVALB RCLK REN2 61 EF2 FF2 MRS E201 R202 10kΩ 62 WRT_CLK2 R201 0Ω REN RCLK 63 RM 64 EF/OR 66 65 PFM VCC PAE 67 68 IP 70 69 BE HF FSEL1 71 72 FSEL0 74 73 OW FF/IR PAF 75 76 FWFT/SI 77 LD 78 MRS 79 GND D11 Q10 D10 VCC D9 Q9 60 59 OE2 58 57 Q17 56 Q16 55 54 53 Q15 52 Q14 51 50 Q13 49 Q12 48 47 Q11 46 45 Q10 44 Q9 42 Q8 41 Q7 Q6 43 40 GND Q5 38 Q5 39 37 Q4 36 35 Q3 Q2 34 33 22 D2_6 Q2 21 U201 Q4 Q7 VCC VCC Q3 Q8 GND D8 D7 20 D12 Q1 19 Q11 Q0 D2_8 GND 32 18 GND 31 D2_9 D13 Q1 17 Q13 Q12 Q0 D2_10 VCC D14 GND 16 D15 D0 15 D2_11 D16 30 D2_12 IDT72V283 TQFP 80 BOTTOM FIFO CHANNEL A D1 14 Q14 VCC 29 13 Q15 28 D2_13 D17 D2_0 12 GND D2 D2_14 GND 27 11 GND D2_1 D2_15 IW D2_2 10 Q16 D3 D2_16 DNC 26 8 9 Q17 D4 D2_17 VCC D2_3 7 VCC D5 6 DNC 25 5 OE 24 4 RT SEN D2_4 3 WEN GND 2 PRS 1 D6 WEN2 23 E202 WCLK 80 VCC D2_7 R203 DNP WRT_CLK2 Q6 VCC D2_5 R204 DNP VCC C201 0.1µF C202 0.1µF C203 0.1µF C204 0.1µF C205 0.1µF C206 0.1µF C207 0.1µF C208 0.1µF Figure 10. PCB Schematic (Continued) Rev. A | Page 15 of 24 05870-010 POPULATE WITH PIN SOCKET PC3 J311 J310 C310 0.1µF 2 3 1 J301 RAPC722X + R316 332Ω R315 DNP C301 10µF 2.2A F301 J313 J312 1 T301 C311 0.1µF R304 332Ω R303 332Ω VCC CR301 S2A-TP 4 VCC R302 332Ω R301 332Ω R314 332Ω POWER SUPPLY INPUT 6V, 2A MAX R313 332Ω R312 DNP R311 332Ω VCC PLACE JUMPERS BETWEEN PADS ON TOP SIDE FOR COHERENT SAMPLING, REMOVE R301-R304 AND SHORT C302 AND C303 3 2 4 U301 RIN4– RIN4+ RIN3– RIN3+ RIN2– RIN2+ RIN1– RIN1+ 3 IN 4 1 GND OUT OUT EN 16 VCC 13 DNP 2 GND J302 C313 1µF 12 VCC + 3 J305 1 J316 C308 + 0.1µF DNP C309 10µF 74VCX86 74VCX86 U302:C 8 3 13 12 74VCX86 U302:D VCC 74VCX86 U302:B C306 0.1µF 5 4 9 20 15 17 19 MRS VCC 18 13 OE1 REN1 CR303 16 14 11 EF1_F 12 8 10 7 6 5 FF1_F 4 3 2 WRT_CLK1 DNP J308 1 R317 499Ω 11 6 E305 J315 E306 J314 1 SET 0, 1, OR 2 XOR GATE DELAYS CONTROLS BOTTOM FIFO 3 WRT_CLK2 SET 0, 1, OR 2 XOR GATE DELAYS 1 CONTROLS 3 TOP FIFO WRT_CLK1 WENS REN2 OE2 EF2 FF2 BOTTOM FIFO WRT_CLK2 RCLK AUX CLOCK SIGNAL MONITOR CONNECTOR 9 10 R310 1kΩ R309 1kΩ 2 1 U302:A VCC DNP J307 J306 TOP FIFO INVERT CLOCK 2 INVERT CLOCK 1 1 J304 3 INVERT CLOCK 2 10 11 14 C307 10µF ROUT4 ROUT3 ROUT2 15 INVERT CLOCK 1 C305 0.1µF ROUT1 DS90LV048A EN 9 VR301 ADP3339AKCZ-3.3-R L 8 7 5 6 4 3 1 2 OPTIONAL POWER INPUT HEADER C312 1µF SK33-TP CR302 REMOVE JUMPER FOR DUAL CHANNEL CONFIGURATION 3 TOP FIFO DUT_CLK1 BOTTOM FIFO DUT_CLK2 J303 1 2 C303 0.1µF C302 0.1µF 1 VCC 1 Rev. A | Page 16 of 24 2 Figure 11. PCB Schematic (Continued) 2 POPULATE WITH PIN SOCKET E302 E301 HSC-ADC-EVALB 05870-011 WRT_CLK2 WRT_CLK1 WENS C401 DNP J406 DNP J405 R401 20KΩ 2 1 R404 49.9Ω R407 49.9Ω R405 49.9Ω Rev. A | Page 17 of 24 R409 40.2Ω R408 49.9Ω U401:A MC100EPT22DG 7 U401:B MC100EPT22DG 3 6 4 R403 DNP R402 DNP VCC D1 9 Figure 12. PCB Schematic (Continued) VCC 20 VBB 3 C403 0.1µF 11 VEE CLK D CLK D Q Q C404 0.1µF Q S R Q S R MC100EP29DTG VCC C402 0.1µF VCC U402 D1 CLK1 CLK1 8 7 6 CLK0 CLK0 4 5 D0 D0 VCC 10 2 1 R406 40.2Ω 13 S1 C405 0.1µF 12 14 Q1 R1 15 Q1 16 17 Q0 Q0 18 19 S0 R0 R410 49.9Ω R415 40.2Ω R414 49.9Ω R412 40.2Ω R413 49.9Ω R411 49.9Ω 7 3 4 6 U403:B MC100EPT23DG DNP U403:A MC100EPT23DG 2 1 J402 J401 J404 DNP J403 WEN2 WEN1 CONTROLS BOTTOM FIFO CONTROLS TOP FIFO HSC-ADC-EVALB 05870-012 VCC C506 0.1µF 1 FROM BOTTOM FIFO FF2 FROM TOP FIFO FF1_TF 3 C507 0.1µF 7 U505:B 14 VCC U505:A C508 0.1µF 2 R521 332Ω VCC R522 332Ω 4 VCC C509 0.1µF 1 2 7 D 4 Q Q CLR GND CLK PRE VCC 8 VCC 3 5 6 5 MRS C511 0.1µF E505 E504 E503 U505:C C512 0.1µF J505 J503 C505 12pF C504 12pF FF1_TF 2 1 C502 2.2µF Y501 24MHz 2 L501 1 EF1_TF VCC 6 R524 0Ω C515 0.1µF C516 0.1µF C517 0.1µF USB_VBUS E502 R503 499Ω FF2 EF2 RCLK INTERLEAVE_FIRSTWORD C514 0.1µF R523 2kΩ VCC C513 0.1µF CR501 J501 USB CONNECTION 4 3 2 1 DNP J506 DNP 3 GND GROUND TEST POINTS U504 C510 0.1µF NOTES * = PROGRAMMABLE POLARITY. FF1_BHB EF1_BHB J504 2 25 24 23 22 21 128 127 126 120 119 118 117 97 96 95 94 19 18 12 11 9 8 7 6 5 4 32 1 VCC A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DMINUS DPLUS XTALIN XTALOUT RDY5 RDY4 RDY3 RDY2 RDY1/*SLWR RDY0/*SLRD IFCLK* CLKOUT C503 0.1µF AGND 20 R518 10kΩ 13 R519 10kΩ 4 3 2 1 SDA SCL WP VCC 24LC00/P VSS A2 A1 U503 A0 AGND 3 GND CS FF2 2 VCC WR 41 FROM BOTTOM FIFO CR502 17 AVCC 10 AVCC 42 FF_USB 2 1 101 5 6 7 8 39 4 FF_USB S501 51 50 VCC 4 3 + S501 = RESET USB CONTROLLER C501 1µF 53 52 R517 2kΩ R516 2kΩ VCC INT5 PA6/*PKTEND PA5/FIFOADR1 PA4/FIFOADR0 PA3/*WU2 PA2/*SLOE PA1/INT1 PA0/INT0 INT4 CTRL_D PC3 74 75 SDI CSB1 CSB2 CSB3 CSB4 CSB5 SDO 109 110 111 112 113 114 115 12 11 AUX SPI PORT CONNECTION 16 15 14 16 NC 10 9 8 7 6 5 4 3 2 1 J502 DNP 13 15 14 SCLK 108 79 78 77 76 Q17 PC2 73 CONTROL FIFO OUTPUT WIDTH OE2 R526 24.9Ω Q16 OE1 R525 24.9Ω INTERLEAVE_FIRSTWORD CTRL_C R507 24.9Ω R520 24.9Ω CTRL_B R506 24.9Ω CTRL_A R505 24.9Ω R504 24.9Ω 72 92 91 90 89 85 84 83 82 28 106 NC NC PE7/GPIFADR8 PE6/T2EX PE5/INT6 PE4/RXD1OUT PE3/RXD0OUT PE2/T2OUT PE1/T1OUT PE0/T0OUT PC7/GPIFADR7 PC6/GPIFADR6 PC5/GPIFADR5 PC4/GPIFADR4 PC3/GPIFADR3 PC2/GPIFADR2 PC1/GPIFADR1 PC0/GPIFADR0 PA7/*FLAGD/SLCS ALL SPI LABELS ARE WITH RESPECT TO THE DUT VCC: 26, 43, 48, 64, 68, 81, 100, 107 GND: 27, 49, 58, 65, 80, 93, 116, 125 U502 CY7C68013A-128AXC R509 10kΩ 5 34 BKPT 33 RESERVED +V CTL0/*FLAGA 69 R510 24.9Ω MRS 1 CTL1/*FLAGB 70 R511 24.9Ω WENS FROM TOP FIFO CTL2/*FLAGC 71 R512 24.9Ω REN1 99 RD RESET 40 *WAKEUP Q15 124 CTL3 66 RENEXT R513 24.9Ω CTL5 98 TXD0 PSEN 38 OE Q14 123 CTL4 67 R514 24.9Ω REN2 31 RXD0 SDA 37 TXD1 Q13 122 PD7/FD15 Q12 121 PD6/FD14 Q11 105 PD5/FD13 Q10 104 PD4/FD12 Q9 103 R515 24.9Ω REN2M T2 R502 100kΩ 30 T1 29 T0 VCC 59 D0 60 D1 VCC 61 RXD1 36 SCL 35 EA R508 10kΩ D2 PD3/FD11 Q8 D3 PD2/FD10 Q7 102 D4 62 PD1/FD9 Q6 57 D5 63 PD0/FD8 Q5 56 D6 86 PB7/FD7 Q4 55 PB6/FD6 Q3 54 PB5/FD5 Q2 47 PB4/FD4 Q1 46 PB3/FD3 Q0 PB2/FD2 45 PB1/FD1 44 PB0/FD0 D7 87 Rev. A | Page 18 of 24 88 Figure 13. PCB Schematic (Continued) 05870-013 U501 HSC-ADC-EVALB HSC-ADC-EVALB VCC CONNECTIONS FOR 2M WORD EXTERNAL MEMORY EXTERNAL MEMORY OVERRIDES ON-BOARD MEMORIES WHEN PLUGGED IN. ONLY A SIDE DATA. C601 0.1µF DNP D1_9 D1_10 D1_11 D1_12 D1_13 D1_14 D1_15 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 DC9 DC10 DC11 DC12 DC13 DC14 DC15 RZ601 DNP D1_0 D1_1 D1_2 D1_3 D1_4 D1_5 D1_6 D1_7 J601 DC8 1 DC0 DC3 DC2 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 DC0 D1_17 R603 0Ω R604 0Ω 4 36 QL0 2 37 QL1 3 38 QL2 4 5 DC6 5 39 DC8 6 40 QL4 6 DC7 7 41 QL5 7 DC11 8 42 QL6 8 43 QL7 9 DC13 DC1 9 10 44 DC14 11 45 DC15 DC2 DC4 12 46 DC3 DC5 13 47 DC16 14 48 DC1 DC4 DC5 DC9 15 49 DC6 DC17 16 50 17 51 18 52 DC7 RZ602 DNP D1_16 3 RENEXT 1 QL3 DC10 1 2 U601 35 DC12 19 53 DC16 20 54 DC17 21 55 22 56 23 57 REN1 24 58 RCLK EF1_BHB 25 59 FF1_BHB 26 60 MRS 27 61 WEN1 WRT_CLK1 28 62 QL0 29 63 QL1 30 64 QL2 QL3 31 65 QL4 32 66 QL5 33 67 QL6 34 68 QL7 Figure 14. PCB Schematic (Continued) Rev. A | Page 19 of 24 10 OE D0 D1 D2 VCC O0 O1 O2 D3 O3 D4 O4 D5 D6 D7 GND O5 O6 O7 CP 20 VCC 19 1 16 Q0 18 2 15 Q1 17 3 14 Q2 16 4 13 Q3 15 5 12 Q4 14 6 11 Q5 13 7 10 Q6 12 8 9 11 Q7 RZ605 74LCX574WMX J602 REN2M J603 RCLK DNP J603: ALLOWS 2M BUFFER TO READ BACK DATA ON EACH RCLK EDGE. J602: ALLOWS 2M BUFFER TO READ BACK ONE DATA ON EVERY THIRD RCLK EDGE. J602 IS FOR BACKWARD COMPATABILITY IF NEEDED. 05870-014 D1_8 HSC-ADC-EVALB PCB LAYOUT 05870-015 HSC-ADC-E VALB-DCZ 05870-016 Figure 15. Layer 1—Primary Side Figure 16. Layer 2—Ground Plane Rev. A | Page 20 of 24 05870-017 HSC-ADC-EVALB 05870-018 Figure 17. Layer 3—Power Plane Figure 18. Layer 4—Secondary Side Rev. A | Page 21 of 24 HSC-ADC-EVALB ORDERING INFORMATION BILL OF MATERIALS Table 5. HSC-ADC-EVALB-DCZ Bill of Materials 1 Item 1 Qty 42 Device Capacitor Package 402 Description Ceramic, 0.1 μF, 16 V, X5R, 10% Manufacturer Panasonic Mfg Part Number ECJ0EB1A104K 3 Reference Designation C101 to C109, C201 to C208, C302, C303, C305, C306, C308, C310, C311, C402 to C405, C503, C506 to C517, C601 C301, C307, C309 2 Capacitor 6032-28 2 C312, C313 Capacitor 603 Kemet Corporation Panasonic T491C106K016AT 3 4 1 C501 Capacitor 3216-18 1 C502 Capacitor 805 6 2 C504, C505 Capacitor 402 Kemet Corporation Murata Manufacturing Co., Ltd. Panasonic T491A105M016AT 5 Tantalum, 10 μF, 16 V, 10% Ceramic, 1 μF, 10 V, X5R, 10% Tantalum, 1 μF, 16 V, 20% Ceramic, 2.2 μF, 25 V, X5R 10% 7 1 CR301 Diode DO-214AA S2A-TP 8 1 CR302 Diode DO-214AB Schottky diode, 30 V, 3 A, SMC 9 2 CR303, CR501 LED 603 10 1 CR502 Diode SOD-123 Diodes, Inc. 1N4148W-7-F 11 1 F301 Fuse 1210 Tyco Electronics/ Raychem NANOSMDC110F-2 12 1 J104 Connector AMP 5650874-4 13 1 J301 Connector 0.08”, PCMT Switchcraft, Inc. RAPC722X 14 1 J303 Connector 4-pin Samtec, Inc. TSW-110-08-G-D 15 4 J304, J305, J314, J315 Connector 3-pin Samtec, Inc. TWS-103-08-G-S 16 10 Connector 603 Panasonic ERJ-3GEY0R00V 17 1 J310 to J313, J401, J404, J406, J503, J505, J603 J316 Connector 2-pin Samtec, Inc. TSW-102-08-G-S 18 1 J501 Connector 4-pin AMP USB-B-S-S-B-TH-R 19 1 L501 805 Steward HZ0805E601R-10 20 21 5 8 402 402 Panasonic Panasonic ERJ-2GE0R00X ERJ-2RKF1002X 22 10 Resistor 402 332 Ω, 1/16 W, 1% Panasonic ERJ-2RKF3320X 23 24 25 26 2 2 1 8 R101, R201, R524, R603, R604 R102 to R104, R202, R508, R509, R518, R519 R301 to R304, R311, R313, R314, R316, R521, R522 R309, R310 R317, R503 R401 R404, R405, R407, R408, R410, R411, R413, R414 Ferrite bead Resistor Resistor Green, 4 V 5 m, candela Switching, 75 V, 150 mA 6.0 V, 2.2 A trip current resettable fuse 120-pin, female, PC mount, right angle RAPC722, power supply connector Male, straight, 100 mil Male, straight, 100 mil 2-pin solder jumper, 0 Ω, 1/10 W, 5% Male, straight, 100 mil USB, PC mount, right angle, Type B, female 500 mA, 600 Ω @ 100 MHz 0 Ω, 1/16 W, 5% 10 kΩ, 1/16 W, 1% Micro Commercial Components Corp. Micro Commercial Components Corp. Panasonic Resistor Resistor Resistor Resistor 402 402 402 402 1 kΩ, 1/16 W, 1% 499 Ω, 1/16 W, 1% 20 kΩ, 1/16 W, 1% 49.9 Ω, 1/16 W, 1% Panasonic Panasonic Panasonic Panasonic ERJ-2RKF1001X ERJ-2RKF4990X ERJ-2RKF2002X ERJ-2RKF49R9X Ceramic, 12 pF, NPO, 50 V, 5% Schottky diode, 50 V, 2 A, SMC Rev. A | Page 22 of 24 ECJ1VB1A105K GRM219R61E225KA12D ECJ-0EC1H120J SK33-TP LNJ314G8TRA HSC-ADC-EVALB Item 27 28 29 Qty 4 1 13 Device Resistor Resistor Resistor Package 402 402 402 Description 40.2 Ω, 1/16 W, 1% 100 kΩ, 1/16 W, 1% 24.9 Ω, 1/16 W, 1% Manufacturer Panasonic Panasonic Panasonic Mfg Part Number ERJ-2RKF40R2X ERJ-2RKF1003X ERJ-2RKF24R9X 3 1 Reference Designation R406, R409, R412, R415 R502 R504 to R507, R510, R511 to R515, R520, R525, R526 R516, R517, R523 RZ101 30 31 Resistor Resistor 402 Panasonic Panasonic ERJ-2RKF2001X EXB-2HV220JX 32 1 S501 Switch Panasonic EVQPLDA15 33 1 T301 Choke 2020 2 kΩ, 1/16 W, 1% Resistor array, 22 Ω, 1/4 W, 5% Momentary (normally open), 100 GE, 5 mm, SPST 10 μH, 5 A, 50 V, 190 Ω @ 100 MHz DLW5BSN191SQ2L 34 2 U101, U201 IC TQFP 80 35 1 U102 IC SOIC-20 Murata Manufacturing Co., Ltd. Integrated Device Technology, Inc. Fairchild Semiconductor 36 1 U301 IC SOIC-16 IC line receiver quad CMOS DS90LV048ATM/NOPB 37 1 U302 IC SOIC-14 38 1 U401 IC SOIC-8 1 U402 IC 20-TSSOP 40 1 U403 IC SOIC-8 ON Semiconductor ON Semiconductor Motorola MC100EPT22DG 39 IC gate exclusive OR quad 2 in IC translator DL TTL/CMOS-PECL IC driver clock dual 1:5 diff IC translator DL LVPECL-LVTTL National Semiconductor Corporation Fairchild 41 1 U501 IC SOT23-5 Tiny logic UHS 2input OR gate NC7SZ32M5X 42 1 U502 IC 128 TQFP IC MCU USB periph high speed 43 1 U503 IC 8-DIP 44 1 U504 IC 8-SSOP IC SRL EEPROM 16 × 8, 2.5 V IC D-type flip-flop w/clear preset 45 1 U505 IC SOIC-14 46 1 U601 IC SOIC-20 47 1 VR301 IC SOT-223 IC reg LDO 1.5 A 3.3 V 48 1 Y501 Crystal Crystal Oscillator, 24 MHz Fairchild Semiconductor Cypress Semiconductor Corporation Microchip Technology Inc. Texas Instruments Incorporated Fairchild Semiconductor Fairchild Semiconductor Analog Devices, Inc. Ecliptek Corporation 1 3.3 V, IDT72V283L7-5PF 74VHC541, octal buffer/line driver, three-state Low voltage hex inverter Octal D-type flip-flop This BOM is RoHS compliant. Rev. A | Page 23 of 24 IDT72V283L7-5PFG 74VHC541M 74VCX86M MC100EP29DTG MC100EPT23DG CY7C68013A-128AXC 24LC00/P SN74LVC2G74DCTR 74LVQ04SC 74LCX574WMX ADP3339AKCZ-3.3-RL EUAA-12-24.000M HSC-ADC-EVALB ORDERING GUIDE Model HSC-ADC-EVALB-DCZ1 HSC-ADC-FPGA-8Z1 HSC-ADC-FPGA-9289 HSC-ADC-DEMUX2 HSC-ADC-AD922xFFA2 HSC-ADC-AD9283FFA2 1 2 ESD CAUTION Description Dual FIFO Version of USB Evaluation Kit Quad/Octal Serial LVDS to Dual Parallel CMOS Interface, Supports All Quad/ Octal ADCs in This Family Except the AD9289 (Not Included in Evaluation Kit) Quad Serial LVDS to Dual Parallel CMOS Interface for the AD9289 Only (Not Included in Evaluation Kit) Adapter for AD9480-LVDS and AD9430-LVDS Evaluation Boards (Not Included in Evaluation Kit) Adapter for AD922x Family (Not Included in Evaluation Kit) Adapter for the AD9283 and AD9057 (Not Included in Evaluation Kit) Z = RoHS Compliant part. If an adapter is needed, send an email to [email protected]. ©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. EB05870-0-7/07(A) Rev. A | Page 24 of 24