MC100EPT22 D

MC100EPT22
3.3V Dual LVTTL/LVCMOS
to Differential LVPECL
Translator
Description
The MC100EPT22 is a dual LVTTL/LVCMOS to differential
LVPECL translator. Because LVPECL (Positive ECL) levels are used
only +3.3 V and ground are required. The small outline 8−lead
package and the single gate of the EPT22 makes it ideal for those
applications where space, performance, and low power are at a
premium. Because the mature MOSAIC 5 process is used, low cost
and high speed can be added to the list of features.
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MARKING
DIAGRAMS*
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
Features
8
420 ps Typical Propagation Delay
Maximum Frequency > 1.1 GHz Typical
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
PNP LVTTL Inputs for Minimal Loading
Q Output Will Default HIGH with Inputs Open
The 100 Series Contains Temperature Compensation.
Pb−Free Packages are Available
8
1
TSSOP−8
DT SUFFIX
CASE 948R
1
KA22
ALYWG
G
DFN8
MN SUFFIX
CASE 506AA
3S MG
G
•
•
•
•
•
•
•
KPT22
ALYW
G
1
4
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
September, 2012 − Rev. 13
1
Publication Order Number:
MC100EPT22/D
MC100EPT22
Table 1. PIN DESCRIPTION
Q0
1
8
VCC
Q0
2
7
D0
LVPECL
Q1
Q1
LVTTL
3
6
4
5
D1
PIN
FUNCTION
Q0, Q1, Q0, Q1
LVPECL Differential Outputs
D0, D1
LVTTL Inputs
VCC
Positive Supply
GND
Ground
EP
(DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND) or
leave unconnected, floating open.
GND
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 4 kV
> 200 V
> 2 kV
Pb Pkg
Pb−Free Pkg
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
UL 94 V−0 @ 0.125 in
164 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC100EPT22
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
6
V
6 to 0
V
50
100
mA
mA
−40 to +85
°C
VCC
Power Supply
GND = 0 V
VI
Input Voltage
GND = 0 V
Iout
Output Current
Continuous
Surge
TA
Operating Temperature Range
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−8
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol
Wave Solder
265
265
°C
qJC
Thermal Resistance (Junction−to−Case)
35 to 40
°C/W
VI v VCC
Pb
Pb−Free
(Note 2)
DFN8
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 4. TTL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0 V, TA= −40°C to 85°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
20
mA
IIH
Input HIGH Current
VIN = 2.7 V
IIHH
Input HIGH Current MAX
VIN = VCC
100
mA
IIL
Input LOW Current
VIN = 0.5 V
−0.6
mA
VIK
Input Clamp Voltage
IIN = −18 mA
−1.0
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
2.0
V
0.8
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 5. PECL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V (Note 3)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
32
43
55
35
45
60
37
46
62
mA
ICC
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 4)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Output parameters vary 1:1 with VCC.
4. All loading with 50 W to VCC − 2.0 V.
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3
MC100EPT22
Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0.0 V (Note 5)
−40°C
Characteristic
Symbol
Min
Typ
25°C
Max
85°C
Min
Typ
Max
0.8
1.1
250
420
675
Min
Typ
Max
0.8
1.1
300
500
700
ps
Unit
fmax
Maximum Frequency (Figure 2)
0.8
1.1
tPLH,
tPHL
Propagation Delay to
Output Differential
250
400
650
tskew
Within−Device Skew (Note 6)
Device−to−Device Skew (Note 7)
50
200
100
400
50
200
100
425
50
200
100
400
ps
tJITTER
Random Clock Jitter (Figure 2)
0.2
<1
0.2
<1
0.2
<1
ps
tJIT(F)
Additive Phase RMS Jitter
Integration Range 12 kHz to 20 MHz
25 MHz
156.25 MHz
tr
tf
Output Rise/Fall Times
(20% − 80%)
Q, Q
GHz
ps
0.05
0.16
50
110
200
60
120
220
70
140
250
ps
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
100
0
0
200
400
600
800
1000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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4
1
(JITTER)
1200
1400
1600
JITTEROUT ps (RMS)
VOUTpp (mV)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Measured using a 2.4 V source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
6. Skew is measured between outputs under identical transitions and conditions on any one device.
7. Device−to−Device Skew for identical transitions at identical VCC levels.
ÉÉ
ÉÉ
MC100EPT22
Figure 4. Typical Phase Noise Plot at
fcarrier = 156.25 MHz
Figure 3. Typical Phase Noise Plot at
fcarrier = 25 MHz
between 12 kHz and 20 MHz; as shown in the shaded region
of the plot) at each of the frequencies is 158 fs and 48 fs
respectively. The input source used for the phase noise
measurements is Agilent E8663B.
The above phase noise plots captured using Agilent
E5052A show additive phase noise of the MC100EPT22
device at frequencies 25 MHz and 156.25 MHz respectively
at an operating voltage of 3.3 V in room temperature. The
RMS Phase Jitter contributed by the device (integrated
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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5
MC100EPT22
ORDERING INFORMATION
Package
Shipping†
SOIC−8
98 Units / Rail
MC100EPT22DG
SOIC−8
(Pb−Free)
98 Units / Rail
MC100EPT22DR2
SOIC−8
2500 / Tape & Reel
MC100EPT22DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC100EPT22DT
TSSOP−8
100 Units / Rail
MC100EPT22DTG
TSSOP−8
(Pb−Free)
100 Units / Rail
MC100EPT22DTR2
TSSOP−8
2500 / Tape & Reel
MC100EPT22DTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
MC100EPT22MNR4G
DFN8
(Pb−Free)
1000 / Tape & Reel
Device
MC100EPT22D
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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6
MC100EPT22
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
MC100EPT22
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
CASE 948R−02
ISSUE A
8x
0.15 (0.006) T U
0.10 (0.004)
S
2X
L/2
L
8
5
1
PIN 1
IDENT
0.15 (0.006) T U
K REF
M
T U
S
V
0.25 (0.010)
B
−U−
4
M
A
−V−
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
−W−
G
DETAIL E
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8
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0_
6_
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0_
6_
MC100EPT22
PACKAGE DIMENSIONS
DFN8 2x2, 0.5P
CASE 506AA
ISSUE E
D
0.10 C
2X
0.10 C
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
ÉÉ
ÉÉ
EXPOSED Cu
TOP VIEW
A
DETAIL B
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
L1
ÇÇ
ÇÇ
PIN ONE
REFERENCE
2X
A
B
MOLD CMPD
DETAIL B
OPTIONAL
CONSTRUCTION
0.08 C
(A3)
NOTE 4
SIDE VIEW
DETAIL A
A1
D2
1
4
C
8X
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
L
8
5
e/2
e
8X
1.30
PACKAGE
OUTLINE
E2
K
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
1.10
1.30
2.00 BSC
0.70
0.90
0.50 BSC
0.30 REF
0.25
0.35
−−−
0.10
0.90
b
8X
0.50
2.30
1
0.10 C A B
0.05 C
8X
0.30
NOTE 3
BOTTOM VIEW
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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Sales Representative
MC100EPT22/D