Low Power CMOS SRAM 512K X 8 Bits UC62LV4008 -55/-70 Description Features: • Vcc operation voltage : 1.5V ~ 3.6V • Low power consumption : 35mA (Max.) operating current 2uA (Typ.) CMOS standby current • High Speed Access time : 70ns (Max.) at Vcc = 1.5V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Data retention supply voltage as low as 1.2V • Easy expansion with CE\ and OE\ options The UC62LV2008 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 words by 8 bits and operates from 1.5V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 2uA and maximum access time of 70ns in 1.5V operation. Easy memory expansion is provided enable (CE\), and active LOW output enable (OE\) and three-state output drivers. The UC62LV4008 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The UC62LV4008 is available in the JEDEC standard 32 pin 450mil Plastic SOP, 8mmx20.0mm TSOP (type I), and 8mmx13.4mm STSOP. PRODUCT FAMILY Product Family UC62LV4008HC UC62LV4008FC UC62LV4008GC UC62LV4008AC UC62LV4008HI UC62LV4008FI UC62LV4008GI UC62LV4008AI Operating Tempature Speed (ns) Vcc Range Vcc=1.5V(Max.) Vcc=3.3V(Typ.) Vcc=3.6V(Max.) 0℃ ~ 70℃ 1.5V ~ 3.6V 55/70 2uA 35mA -40℃ ~ 85℃ 1.5V ~ 3.6V 55/70 2uA 35mA PIN CONFIGURATIONS COL Address ROW DECODER ROW Address TSOP(I)-32 SOP-32 STSOP-32 DICE TSOP(I)-32 SOP-32 STSOP-32 DICE MEMORY ARRAY 512K X 8 Bits COLUMN DECODER CE WE OE CONTROL BLOCK CE WE OE CONTROL INPUT BUFFER VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 ADDRESS INPUT BUFFER 32 1 31 2 30 3 29 4 28 5 27 6 26 7 25 8 9 CS62LV4008FI 24 CS62LV4008FC 23 10 22 11 21 12 20 13 19 14 15 18 16 17 Package Type BLOCK DIAGRAM A0 - A18 A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND Power Consumption STANDBY Operating SENSE AMPLIFIER & WRITE DRIVER X8 I/O BUFFER DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A11 A9 A8 A13 WE A18 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CS62LV4008HI CS62LV4008HC CS62LV4008GI CS62LV4008GC OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 U-Chip Technology Corp. LTD. . Reserves the right to modify document contents without notice. Preliminary Rev.1.0 PAGE 1 Low Power CMOS SRAM 512K X 8 Bits UC62LV4008 -55/-70 PIN DESCRIPTION Name Type Function A0 – A18 Input Address inputs for selecting one of the 524,288 x 8 bit words in the RAM CE\ Input CE\ is active LOW. Chip enable must be active when data read from or write to the device. If chip enable is not active, the device is deselected and not in a standby power down mode. The DQ pins will be in high impedance state when the device is deselected. WE\ Input The Write enable input is active LOW and controls read and write operations. With the chip selected, when WE\ is HIGH and OE\ is LOW, output data will be present on the DQ pins, when WE\ is LOW, the data present on the DQ pins will be written into the selected memory location. OE\ Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE\ is inactive. DQ0 – DQ7 I/O Vcc Power Power Supply Gnd Power Ground These 8 bi-directional ports are used to read data from or write data into the RAM. TRUTH TABLE Mode WE\ CE\ OE\ I/O state Vcc Current Not Selected X H X High Z ISB,ISB1 Output Disabled H L H High Z ICC Read H L L DOUT ICC Write L L X DIN ICC ABSOLUTE MAXIMUM RATINGS(1) SYMBOL PARAMETER RATING OPERATING RANGE -0.5 to VCC+0.5 VTERM Terminal Voltage with Respect to GND TBIAS Temperature Under Bias -40 to 125 ℃ TSTG Storage Temperature -50 to 150 ℃ V PT Power Dissipation 1 W IOUT DC Output Current 20 mA 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. U-Chip Technology Corp. LTD. RANGE UNIT Commercial AMBIENT TEMPERATURE VCC 0℃ to 70℃ 1.5V ~ 3.6V CAPACITANCE(1)(TA=25℃,f=1.0MHz) SYMBOL PARAMETER CONDITIONS MAX. UNIT Input VIN=0V 6 pF Capacitance Input/Output VDQ 8 pF CDQ Capacitance 1. This parameter is guaranteed and not 100% tested. . Reserves the right to modify document contents without notice. CIN Preliminary Rev.1.0 PAGE 2 Low Power CMOS SRAM 512K X 8 Bits UC62LV4008 -55/-70 DC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃) Symbol MIN. TYP.(1) MAX. UNITS VCC=2.4V -0.5 - 0.8 V VCC=3.6V 2.0 - Vcc-0.2 V Test Condition Comment VIH Guaranteed Input Low (2) Voltage Guaranteed Input High (2) Voltage IL Input Leakage Current VCC=3.6V VIN=0V to VCC - - 1 uA IOL Output Leakage Current VCC=3.6V CE\=VIH or OE\=VIH VIO=0V t VCC - - 1 uA VOL Output Low Voltage VCC=3.6V, IOL=2mA - - 0.4 V VOH Output High Voltage VCC=3.0V, IOH=-1mA 2.4 - - V ICC Operating Power Supply Current CE\=VIL,IDQ=0mA, F=Fmax - - 35 mA ISB1 TTL Standby Current CE\=VIH, VIN=VIH to VIL - - 1 mA ISB2 CMOS Standby Current CE\≧VCC-0.2V, VIN=VCC-0.2V to 0.2V - 2 10 uA VIL (3) 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . DATA RETENTION CHARACTERISTICS ( TA=0℃ to 70℃) Symbol VDR ICCDR tDR tR Comment Test Condition CE\≧VCC - 0.2V VIN≧VCC-0.2V or VIN≦0.2V CE\≧VCC - 0.2V VIN≧VCC-0.2V or VIN≦0.2V VCC to Data Retention Data Retention Current Chip Deselect to Data Retention Time VCC = 1.5V, TA = 25℃. 2. tRC = Read Cycle Time (1) TYP. MAX. UNITS 1.2 - - V - 0.1 1 uA 0 - - ns - - ns See Retention Waveform Operation Recovery Time 1. MIN. TRC (2) LOW VCC DATA RETENTION WAVEFORM(1) (CE\ Controlled) Vcc CE Data Retention Mode VDR >= 1. 2V tCDR CE >= VCC - 0. 2V VIH U-Chip Technology Corp. LTD. . Reserves the right to modify document contents without notice. tR VIH Preliminary Rev.1.0 PAGE 3 Low Power CMOS SRAM 512K X 8 Bits AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level UC62LV4008 -55/-70 KEY TO SWITCHING WAVEFORMS VCC/0V 1V/ns 0.5VCC WAVEFORMS INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H DON’T CARE ANY CHANGE PERMITTED CHANGE STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE OFF STATE AC TEST LOADS AND WAVEFORMS 3.3V 3.3V 1269Ω INCLUDING JIG AND SCOPE 1269Ω INCLUDING JIG AND SCOPE 5pF 100pF 1404Ω OUTPUT 1404Ω OUTPUT FIGURE 1A FIGURE 1B TERMINAL EQUIVALENT 667Ω OUTPUT 1.73V ALL INPUT PULSES VCC GND 90% 90% 10% 10% FIGURE 2 1V/ns 1V/ns AC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃, VCC=1.5V~3.6V) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION tAVAX tRC Read Cycle Time tAVQV tAA tELQV UC62LV4008-55 UC62LV4008-70 Min Typ Max Min Typ Max 55 - - 70 - - ns Address Access Time - - 55 - - 70 ns tCE Chip Select Access Time - - 55 - - 70 ns tGLQV tOE Output Enable to Output Valid - - 30 - - 35 ns tELQX tCLZ Chip Select to Output Low Z 10 - - 10 - - ns tGLQX tOLZ Output Enable to Output Low Z 5 - - 5 - - ns tEHQZ tCHZ Chip Deselect to Output in High Z 0 - 20 0 - 20 ns tGHQZ tOHZ Output Disable to Output in High Z 0 - 20 0 - 20 ns tAXOX tOH Address Chang to Output Change 10 - - 10 - - ns U-Chip Technology Corp. LTD. . Reserves the right to modify document contents without notice. Preliminary Rev.1.0 PAGE 4 UNIT Low Power CMOS SRAM 512K X 8 Bits UC62LV4008 -55/-70 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) tRC ADDRESS tAA tOH tOH DOUT READ CYCLE2 (1,3,4) CE tCE tCLZ (5) tCHZ (5) DOUT READ CYCLE3 (1,4) tRC ADDRESS tAA tOH OE tOE tOHZ (1,5) tOLZ CE tCE tCLZ (5) tCHZ (5) DOUT NOTES: 1. WE\ is high in read cycle. 2. Device is continuously selected when CE\ = VIL 3. Address valid prior to or coincident with CE\ transition low. 4. OE\ = VIL. 5. Transition is measured ±500mV from steady state with CL=5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. U-Chip Technology Corp. LTD. . Reserves the right to modify document contents without notice. Preliminary Rev.1.0 PAGE 5 Low Power CMOS SRAM 512K X 8 Bits UC62LV4008 -55/-70 AC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃, VCC=1.5V~3.6V) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION tAVAX tWC tE1LWH UC62LV4008-55 UC62LV4008-70 Min Typ Max Min Typ Max Write Cycle Time 55 - - 70 - - ns tCW Chip Select to END of Write 40 - - 50 - - ns tAVWL tAS Address Setup Time 0 - - 0 - - ns tAVWH tAW Address valid to End of Write 40 - - 50 - - ns tWLWH tWP Write Pulse Width 40 - - 50 - - ns tWHAX tWR Write Recovery Time 0 - - 0 - - ns tWLOZ tWHZ Write to Output in High Z - - 20 - - 20 ns tDVWH tDW Data to Write Time Overlap 35 - 40 - tWHDX tDH Data Hold Time for Write End 0 - - 0 - - ns tGHOZ tOHZ Output Disable to Output In High Z 0 - 20 0 - 20 ns tWHQX tOW End of Write to Output Active 5 - - 5 - - ns ns SWITCHING WAVEFORMS (WRITE CYCLE) WRITECYCLE1(1) tWC ADDRESS tAW OE tCW(11) CE tAS (4,10) tWP(2) WE tOHZ DOUT tDW tDH DIN U-Chip Technology Corp. LTD. . Reserves the right to modify document contents without notice. Preliminary UNIT Rev.1.0 PAGE 6 Low Power CMOS SRAM 512K X 8 Bits UC62LV4008 -55/-70 WRITE CYCLE2(1,6) tWC ADDRESS tAW tCW(11) CE tAS tWP(2) WE tWHZ tOH DOUT (7) tDW (8) tDH DIN NOTES: 1. WE\ must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals must be active to initiate a write and any one can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE\ or WE\ going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\ transition, output remain in a high impedance state. 6. OE\ is continuously low (OE\ = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE\ going low to the end of write. U-Chip Technology Corp. LTD. . Reserves the right to modify document contents without notice. Preliminary Rev.1.0 PAGE 7 Low Power CMOS SRAM 512K X 8 Bits UC62LV4008 -55/-70 ORDERING INFORMATION UC62LV4008 AB -- YY A => GRADE C:COMMERCIAL; 0 ~ 70℃ I : INDUSTRIAL; -40 ~ 85℃ B => PACKAGE H:TSOP(I) F:SOP G:STSOP A:DICE YY => SPEED 55: 55ns 70: 70ns U-Chip Technology Corp. LTD. . Reserves the right to modify document contents without notice. Preliminary Rev.1.0 PAGE 8 Low Power CMOS SRAM 512K X 8 Bits UC62LV4008 -55/-70 PACKAGE DIMENSIONS Unit Inch mm A A1 A2 b b1 c c1 D E e HD 0.0433±0.004 0.004±0.002 0.039±0.002 0.009±0.002 0.008±0.001 0.004~0.008 0.004~0.006 0.465±0.004 0.315±0.004 0.020±0.004 0.528±0.008 1.10±0.10 0.10±0.05 1.00±0.05 0.22±0.05 0.2±0.03 0.10~0.21 0.10~0.16 11.8±0.10 8.00±0.10 0.50±0.10 13.40±0.20 L 0.0197+0.008 -0.004 0.5 +0.2 -0.1 L1 y θ 0.0315±0.004 0.004 Max 0” ~ 8” 0.80±0.10 0.1 Max 0” ~ 8” Symbol 1 2 ° (2 X ) 1 2 °(2 X ) e b E HD 32 1 S E A T IN G P L A N E "y" 1 2 °(2 X ) 16 G AU G E PLANE A A2 "A " D A A1 17 A θ 1 2 ° (2 X ) L L1 S E A T IN G P L A N E 1 0 .2 5 4 "A " D E T A IL V IE W 32 b W IT H P L A T IN G c 16 17 c1 BASE M ETAL b1 S E C T IO N A -A 32 - STSO P U-Chip Technology Corp. LTD. . Reserves the right to modify document contents without notice. Preliminary Rev.1.0 PAGE 9 Low Power CMOS SRAM 512K X 8 Bits Unit Inch UC62LV4008 -55/-70 mm Symbol A A1 A2 b b1 c c1 D E e HD L L1 y θ 0.0433±0.004 0.004±0.002 0.039±0.002 0.009±0.002 0.008±0.001 0.004~0.008 0.004~0.006 0.724±0.004 0.315±0.004 0.020±0.004 0.787±0.008 0.0197+0.008 -0.004 0.0315±0.004 0.004 Max 0” ~ 8” 1.10±0.10 0.10±0.05 1.00±0.05 0.22±0.05 0.2±0.03 0.10~0.21 0.10~0.16 18.40±0.10 8.00±0.10 0.50±0.10 20.00±0.20 0.5 +0.2 -0.1 0.80±0.10 0.1 Max 0” ~ 8” 12°(2X) 12°(2X) e b E HD 1 32 SEATING PLANE "y" 12°(2X) 16 GAUGE PLANE 17 A A A2 "A" D A1 θ A 12°(2X) L L1 SEATING PLANE 1 0.254 "A" DETAIL VIEW 32 b WITH PLATING c 16 17 c1 BASE METAL b1 SECTION A-A 32 - TSOP U-Chip Technology Corp. LTD. . Reserves the right to modify document contents without notice. Preliminary Rev.1.0 PAGE 10 Low Power CMOS SRAM 512K X 8 Bits Unit Inch UC62LV4008 -55/-70 mm Symbol A A1 A2 b b1 c c1 D E E1 e L L1 y θ 0.111±0.007 0.009±0.005 0.1055±0.0055 0.014 ~ 0.020 0.014 ~ 0.018 0.006 ~ 0.012 0.006 ~ 0.011 0.805±0.005 0.445±0.005 0.555±0.012 0.050±0.006 0.033±0.010 0.055±0.008 0.004 Max 0” ~ 10” 2.821±0.176 0.229±0.127 2.680±0.140 0.35 ~ 0.50 0.35 ~ 0.46 0.15 ~ 0.32 0.15 ~ 0.28 20.447±0.127 11.303±0.127 14.097±0.305 1.270±0.152 0.834±0.25 1.397±0.203 0.1 Max 0” ~ 10” 17 32 1 E1 E "A" 16 b e A D θ A L 10°(4X) L1 b A A2 DETAIL "A" (2:1) A1 WITH PLATING Seating Plane "y" c c1 BASE METAL SOP - 32 U-Chip Technology Corp. LTD. b1 SECTION A-A . Reserves the right to modify document contents without notice. Preliminary Rev.1.0 PAGE 11