Schematic PDF

6
5
4
3
2
1
REVISION RECORD
LTR
ECO NO:
APPROVED:
DATE:
D
VLCD_VDD
VLCD_13
VLCD_23
VLCD_FLY2
VLCD_FLY1
D
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.14
L1
L2 P4.0
P4.1
R1
P4.2
RCAL1
RCAL2
TRST
TRACECLK
TRACEDATA0
TRACEDATA1
TRACEDATA2
TRACEDATA3
VUSB
DGND_USB
VBUS
USB_DM
USB_DP
R4
K9 AVDD_TX/RX
AGND_TX/RX
K10
AGND_REF
P14 AGND_CTOUCH
P4.0
P4.1
P4.2
P5
RCAL1 R5
RCAL2
R6
P6
R7
P7
R8
P8
R9
P9
R12
P12
AN_A P13
AN_B R13
AN_C R14
AN_D
VCCM_ANA
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.14
F14
G14
F15
F10
G10
H10
G15
J10
F8
F9
C14
E14
K6
K7
J6
RESETX
VREF
VBIAS
REF_EXCITE
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
KERNEL_GPIO
R10
VREF P10
VBIAS
P11
TIA_I R11
TIA_O
P4
B2
A2
B3
A3
B4
A4
D15
C15
B15
A14
A13
B13
B14
D14
E15
A15
N2
KERNEL_GPIO A1
APLATFORM_TEST K8
RESETX
AFE1
AFE2
AFE3
AFE4
AFE5
AFE6
AFE7
AFE8
VCCM_DIG
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P1.8
P1.9
P1.10
P1.11
P1.12
P1.13
P1.14
P1.15
H6
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
A11
B11
A12
B12
ADUCM350-OM
K1
DVDD
M1
H15 VBACK
VDD_IO
B
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P1.8
P1.9
P1.10
P1.11
P1.12
P1.13
P1.14
P1.15
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.8
P0.9
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
H14
G6 DGND
DGND1
F7
DGND2
C
K15
J15
L15
K14
J14
L14
J1
J2
H1
H2
R2
K2
R3
P2
P3
M2
D2
VLCD_VDD
C2
VLCD_13
VLCD_23 B1
F2
VLCD_FLY2 E2
VLCD_FLY1
U1
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.8
P0.9
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
ADuCM350
C
AFE1
AFE2
AFE3
AFE4
AFE5
AFE6
AFE7
AFE8
TIA_I
TIA_O
REF_EXCITE
AN_A
AN_B
AN_C
AN_D
R15
M15
M14
N15
N14
P15
TRST
TRACECLK
TRACEDATA0
TRACEDATA1
TRACEDATA2
TRACEDATA3
E1
F6
G2
F1
G1
VUSB
N1
RTC_XTAL2 P1
RTC_XTAL1
D1
HF_XTAL1 C1
HF_XTAL2
B
VBUS
USB_DM
USB_DP
RTC_XTAL2
RTC_XTAL1
HF_XTAL1
HF_XTAL2
AVDD_TX/RX
VCCM_ANA
VCCM_DIG
VBACK
VDD_IO
A
DVDD
COMPANY:
Analog Devices
A
TITLE:
DRAWN:
Pat Sheahan
CHECKED:
Liam Riordan
Eval-ADuCM350EBZ
DATED:
Dec 2013
DATED:
CODE:
Dec 2013
QUALITY CONTROL:
DATED:
RELEASED:
DATED:
SIZE:
A2
SCALE:
DRAWING NO:
REV:
B1
02-038364
SHEET: 1
OF
7
6
5
4
3
2
1
REVISION RECORD
LTR
ECO NO:
APPROVED:
DATE:
D
D
LF 32KHz XTAL
HF 16MHz Xtal
P2.1
LK2
R60
560r
HF_XTAL1
C7
DISPLAY2
VCCM_DIG
P0.11
LK8
DISPLAY
R2
560r
LED-0603-RED
3.3V_BOARD
LED-0603-RED
HF_XTAL2
RTC_XTAL1
15pF
Y3
Y1
C2
C8
RTC_XTAL2
1
3
2
4
GND GND
P3.6
XTAL-FA238
560r
DNI
C4
24pF
R61
R62
DISPLAY3
3.3V_BOARD
P4.2
LK12
DISPLAY1
R59
560r
LED-0603-RED
3.3V_BOARD
LED-0603-RED
24pF
15pF
C
GPIO LEDs
Layout: Needs To Be Near DUT
Layout: Shielding on 16MHz
C
EXT INT
T4
B
T6
T7
C21
DNI
C11
4700pF
VLCD_FLY1
LCD Charge Pump
T9
VLCD_13
VLCD_FLY2
T5
P0.10
P3.4
VLCD_VDD
T8
C14
1uF
C22
DNI
R48
S2
S4
R12
VLCD_23
0r
0r
B
P0.10
P3.4
C15
0.1uF
C5
0.1uF
COMPANY:
A
Analog Devices
A
TITLE:
DRAWN:
Pat Sheahan
CHECKED:
Liam Riordan
Eval-ADuCM350EBZ
DATED:
Dec 2013
DATED:
CODE:
Dec 2013
QUALITY CONTROL:
DATED:
RELEASED:
DATED:
SIZE:
A2
SCALE:
DRAWING NO:
REV:
B1
02-038364
SHEET: 2
OF
7
6
5
4
3
2
1
REVISION RECORD
LTR
ECO NO:
APPROVED:
DATE:
DIGITAL PERIPHERAL CONNECTORS
D
D
Digital Header 1
Digital Header 2
P0.12
C
DGND1
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
*
*
*
*
*
*
*
*
*
*
*
*
*
CONNECTOR
STANDARD
SDP
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P2.0
P2.1
R33
0r
R23
0r
3.3V_BOARD
P2.2
P2.3
VCCM_ANA
P2.4
P2.5
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P1.8
P1.9
J5-12
J5-11
J5-10
J5-9
J5-8
J5-7
J5-6
J5-5
J5-4
J5-3
J5-2
J5-1
P0.15
P1.10
P0.14
P1.12
P0.13
P1.14
P0.12
P2.10
P0.11
P2.9
P0.10
P2.8
P4.2
P2.7
P4.1
P2.6
P4.0
P2.14
J20-1
J20-2
J20-3
J20-4
J20-5
J20-6
J20-8
J20-7
J20-10
J20-9
J20-12
J20-11
J20-14
J20-13
J20-19
J20-15
J20-21
J20-23
J20-25
J20-27
J20-29
J20-31
J20-33
J20-35
J20-37
J20-39
P3.14
P3.2
P3.13
P3.4
P3.12
P3.6
P3.8
J20-41
J20-43
J20-16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
*
*
*
*
*
*
*
*
*
*
*
*
*
CONNECTOR
STANDARD
SDP
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P0.13
0r
R3
VUSB
0r
R34
VCCM_DIG
P0.14
P0.15
0r
R44
0r
R35
0r
R36
VLCD_VDD
C
3.3V_BOARD
VDD_IO
J20-20
P1.11
J20-22
P1.13
J20-24
P1.15
J20-26
P2.11
J20-28
P2.12
J20-30
P2.15
J20-32
P3.10
J20-34
P2.13
J20-36
P3.11
J20-38
P3.0
J20-40
P3.1
J20-18
P3.3
J20-42
P3.5
J20-44
P3.7
J20-17
B
P3.9
J6
J1
EXT INT = P4.0 and P0.10
DO NOT POPULATE TESTPOINTS
DO NOT POPULATE TESTPOINTS
EXT INT = P3.4
COMPANY:
A
Analog Devices
A
TITLE:
DRAWN:
Pat Sheahan
CHECKED:
Liam Riordan
Eval-ADuCM350EBZ
DIGITAL 2
DATED:
Dec 2013
DATED:
CODE:
Dec 2013
QUALITY CONTROL:
DATED:
RELEASED:
DATED:
SIZE:
A2
SCALE:
DRAWING NO:
REV:
B1
02-038364
SHEET: 3
OF
7
6
5
4
3
2
1
REVISION RECORD
LTR
IV GAIN
APPROVED:
DATE:
RCAL
LAyout: Needs To Be Near DUT
R5
TIA_I
D
ECO NO:
D
RCAL2
DNI
R7
R47
DNI
DNI
RCAL1
TIA_O
AFE Daughtercard
R24
J8-1
J9-1
0r
AFE1
J8-2
J8-3
R66
0r
P4.2
AFE2
J8-5
J8-6
C
J8-8
AFE6
J8-43
J8-24
J8-44
J8-25
J8-45
R25
R67
0r
R26
P0.10
0r
AFE3
J8-28
J8-48
REF_EXCITE_1
J8-29
J8-11
J8-31
J8-12
J8-32
J8-33
R15
0r
J8-50
RCAL1
J8-51
0r
RCAL2
J8-34
J8-54
J8-15
J8-35
J8-55
J8-16
J8-36
J8-17
J8-37
J8-57
J8-38
J8-58
AFE5
J8-19
J8-39
J8-20
J8-40
R39
R57
0r
0r
TIA_I
TIA_O
AN_D_1
J9-42
J9-23
J9-43
J9-24
J9-44
J9-5
J9-25
J9-45
J9-6
J9-26
J9-46
J9-7
J9-27
J9-47
J9-8
J9-28
J9-48
3.3V_BOARD J9-29
0r
J9-30
J9-49
R8
R10
J9-9
R70
R74
0r
0r
J8-56
VBIAS_1
J8-59
J8-60
J9-22
J9-4
AN_C_1
J8-53
J8-14
J8-18
AN_B_1
J8-52
R38
J9-41
J9-3
J8-49
AFE8
J9-21
J9-2
J8-46
J8-47
J8-30
AFE4
AFE7
J8-27
J8-10
J8-13
0r
AN_A_1
J8-42
J8-23
J8-26
J8-9
B
J8-41
J8-22
J8-4
J8-7
J8-21
J9-10
3.3V_BOARD
J9-11
R68
R69
VCCM_ANA
0r
0r
0r
C
J9-50
J9-31
J9-51
J9-12
J9-32
J9-52
J9-13
J9-33
J9-53
J9-14
J9-34
J9-54
J9-15
J9-35
J9-55
J9-16
J9-36
J9-56
J9-17
J9-37
J9-57
J9-18
J9-38
J9-58
J9-19
J9-39
J9-59
J9-20
J9-40
J9-60
VREF_1
B
ESD SENSOR PROTECTION
AFE4
AFE3
AFE8
AFE7
R14
R16
0r
0r
U2
6
1 I/O1
I/O4
5
2 GND
VCC
3 I/O3
4
I/O2
R18
0r
AFE1
VCCM_ANA
R51
0r
AFE2
R54
0r
AFE5
DIODE-SP3004
R52
R53
0r
0r
U4
6
1 I/O1
I/O4
5
2 GND
VCC
3 I/O3
4
I/O2
VCCM_ANA
R55
0r
AFE6
DIODE-SP3004
COMPANY:
A
Analog Devices
A
TITLE:
DRAWN:
Pat Sheahan
CHECKED:
Liam Riordan
Eval-ADuCM350EBZ
ANALOG 1 - STRIP
DATED:
Dec 2013
DATED:
CODE:
Dec 2013
QUALITY CONTROL:
DATED:
RELEASED:
DATED:
SIZE:
A2
SCALE:
DRAWING NO:
REV:
B1
02-038364
SHEET: 4
OF
7
6
5
4
3
2
1
REVISION RECORD
LTR
ECO NO:
APPROVED:
DATE:
REF_EXCITE_1
A
REF_EXCITE
R9
22.6K
D
M3
Thermistor
B
T67
T77
LK6
AN_A
R11
47K
C20
100pF
AGND
UNCOMITTED INPUTS - Connectors.
LK11
AN_D_1
LK9
AN_C_1
C
LK3
AN_B_1
LK1
AN_A_1
AN_A
AN_B
AN_C
AN_D
T10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
*
*
*
*
*
*
*
*
*
*
*
*
*
CONNECTOR
STANDARD
SDP
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
D
R58
0r
3.3V_BOARD
These can be re-arranged
to suit Layout
P0-1
P0.1
P0-0
P0.0
P0-2
P0.2
C
P0-3
P0.3
P0-5
P0.5
P0-4
P0.4
J21
Int On Cap Touch
B
S1
R63
0r
P0.2
CAP TOUCH CONNECTOR.
B
C18
0.1uF
S3
R65
0r
P0.4
C23
0.1uF
COMPANY:
A
Analog Devices
A
TITLE:
DRAWN:
Pat Sheahan
CHECKED:
Liam Riordan
Eval-ADuCM350EBZ
ANALOG 2
DATED:
Dec 2013
DATED:
CODE:
Dec 2013
QUALITY CONTROL:
DATED:
RELEASED:
DATED:
SCALE:
SIZE:
DRAWING NO:
A2
02-038364
SHEET: 5
REV:
B1
OF
7
6
5
4
3
2
1
REVISION RECORD
LTR
SERIAL WIRE
EMULATOR
ECO NO:
APPROVED:
DATE:
RESET BUTTON
UART
D
T75
J14-5
J14-4
J14-3
J14-2
J14-1
5VUSB
RX
SWCLK
TX
UART_RX
T74
5V_USB
UART_RX
M2
RESETX
P3.7
RESET
S5
Rx
P0.9
T72
UART_TX
C33
0.1uF
SWIO
T76
P0.8
GND
RESET
T2
P0.7
M1
UART_TX
RESETX
B
J14-6
VDDOUT
P0.6
A
J14-7
VDDOUT
B
J14-8
A
INTERFACE BOARD CONNECTOR
D
P3.6
Tx
C
R49
10K
T1
S6
KERNEL_GPIO
3.3V_BOARD
C
SERIAL
DOWNLOAD
SERIAL DOWNLOAD
LK13
PTC1
VBUS
L4
IND-MOLDED
1
2
C29
4.7uF
C0805
0.1uF
3.3V_BOARD
B
3
C17
4
5
J17
JTRACE
Note: Notch to face boards edge
Allow Access Area For Connector
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
EHF-120-01-L-D
P0.8
P0.9
P0.6
P0.7
USB_DP
USB_DM
J4
USB-MICRO-B
VBUS
DD+
ID
6
SHLD1
7
SHLD2
8
SHLD3
9
SHLD4
GND
B
R1
40.2r
R4
40.2r
R6
33K
U5
5
TRST
TRACECLK
TRACEDATA0
TRACEDATA1
TRACEDATA2
TRACEDATA3
VCC
DGND
4
I/O2
I/O1
GND
USB
2
NC
3
1
DIODE-824011
Note: KEEP TRACK LENGHTS THE SAME
KEEP CLOSE TO DUT
COMPANY:
A
Analog Devices
A
TITLE:
DRAWN:
Pat Sheahan
CHECKED:
Liam Riordan
Eval-ADuCM350EBZ
INTERFACE
DATED:
Dec 2013
DATED:
CODE:
Dec 2013
QUALITY CONTROL:
DATED:
RELEASED:
DATED:
SCALE:
SIZE:
DRAWING NO:
A2
02-038364
SHEET: 6
REV:
B1
OF
7
6
5
4
3
2
1
REVISION RECORD
LTR
ECO NO:
APPROVED:
DATE:
RTC BACK UP
D
D
T69
LK4
VBACK
1
+
VCCM GENERATION
C10
C44
TESTCAP
4.7uF
2
SUPER CAP
DNI
3.3V_BOARD
Option 1
VLCD
T68
U6
2
5V_USB
IN
OUT
1
L2
R32
BEAD
0r
+
SD GND
7
3
C37
10uF
C
LK5
R31
VDDOUT
VCCM_ANA
1r6
R30
560r
LK14
VLCD_VDD
Analog Decoupling
AVDD_TX/RX
D4
POWER
C9
0.47uF
Option 2
VCCM_DIG
USB Regulator
LK24
0r
VBIAS_1
C41
0.47uF
VCCM_ANA
LK7
C
VBIAS
R43
C43
10uF
VREF_1
R45
0r
VDD_IO
C42
4.7uF
C48
0.1uF
T3
VREF
VUSB
J10
A
VCCM_ANA
Layout: Resistors Close to Decoupling Cap
B
3.3V_BOARD
B
C
M5
Digital Decoupling
+
J19
BATT-3002-20MM
BATTERY CONTACT
VCCM_DIG
LK10
B
A
VDD_IO
VCCM_ANA
C3
0.1uF
B
C36
0.47uF
3.3V_BOARD
C13
4.7uF
DVDD
VUSB
C35
0.22uF
VDD_IO
C38
0.47uF
VLCD_VDD
C1
0.47uF
Option 3
J12-2
C34
0.1uF
C40
10uF
J12-1
COMPANY:
A
Analog Devices
A
TITLE:
DRAWN:
Pat Sheahan
CHECKED:
Liam Riordan
Eval-ADuCM350EBZ
POWER
DATED:
Dec 2013
DATED:
CODE:
Dec 2013
QUALITY CONTROL:
DATED:
RELEASED:
DATED:
SCALE:
SIZE:
DRAWING NO:
A2
02-038364
SHEET: 7
REV:
B1
OF
7