SAMSUNG K4X51163PE

K4X51163PE - L(F)E/G
Mobile DDR SDRAM
32Mx16 Mobile DDR SDRAM
1. FEATURES
• VDD/VDDQ = 1.8V/1.8V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• MRS cycle with address key programs
- CAS Latency ( 3 )
- Burst Length ( 2, 4, 8, 16 )
- Burst Type (Sequential & Interleave)
• EMRS cycle with address key programs
- Partial Array Self Refresh ( Full, 1/2, 1/4 Array )
- Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 )
• Internal Temperature Compensated Self Refresh
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
• Data I/O transactions on both edges of data strobe, DM for masking.
• Edge aligned data output, center aligned data input.
• No DLL; CK to DQS is not synchronized.
• DM0 - DM3 for write masking only.
• Auto refresh duty cycle
- 7.8us for -25 to 85 °C
2. Operating Frequency
DDR333
DDR266
@CL21)
83Mhz
83Mhz
Speed @CL31)
166Mhz
133Mhz
Speed
NOTE:
1) CAS Latency
3. Address configuration
Organization
Bank Address
Row Address
Column Address
32Mx16
BA0,BA1
A0 - A12
A0 - A9
- DM is internally loaded to match DQ and DQS identically.
4. Ordering Information
Part No.
Max Freq.
K4X51163PE-L(F)E/GC6
166MHz(CL=3),83MHz(CL=2)
K4X51163PE-L(F)E/GC3
133MHz(CL=3),83MHz(CL=2)
Interface
Package
LVCMOS
60FBGA
Pb (Pb Free)
- L(F)E : 60FBGA Pb(Pb Free), Normal Power, Extended Temperature(-25 °C ~ 85 °C)
- L(F)G : 60FBGA Pb(Pb Free), Low Power, Extended Temperature(-25 °C ~ 85 °C)
- C6/C3 : 166MHz(CL=3) / 133MHz(CL=3)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY
INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS"
BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in
loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
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June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
5. FUNCTIONAL BLOCK DIAGRAM
CK, CK
LWE
I/O Control
16
Data Input Register
LDM
Serial to parallel
Bank Select
32
4Mx32
16
Output Buffer
2-bit prefetch
Sense AMP
4Mx32
32
X16
DQi
4Mx32
Column Decoder
Col. Buffer
LCBR
LRAS
Latency & Burst Length
Strobe
Gen.
LCKE
Row Decoder
Refresh Counter
Row Buffer
ADD
Address Register
CK, CK
4Mx32
Programming Register
LRAS LCBR
LWE
LCAS
CKE
CS
RAS
LDM
LWCBR
Timing Register
CK, CK
Data Strobe
CAS
DM Input Register
WE
-5-
DM
June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
6. Package Dimension and Pin Configuration
< Top View*2 >
< Bottom View*1 >
E1
60Ball(6x10) FBGA
9
8
7
6
5
4
3
2
1
e
A
2
3
7
8
A
VSS
B
VDDQ
9
DQ15
VSSQ
VDDQ
DQ0
VDD
DQ13
DQ14
DQ1
DQ2
VSSQ
C
C
VSSQ
DQ11
DQ12
DQ3
DQ4
VDDQ
D
D
VDDQ
DQ9
DQ10
DQ5
DQ6
VSSQ
E
E
VSSQ
UDQS
DQ8
DQ7
LDQS
VDDQ
F
VSS
UDM
N.C.
N.C.
LDM
VDD
G
G
CKE
CK
CK
WE
CAS
RAS
H
H
A9
A11
A12
CS
BA0
BA1
J
A6
A7
A8
A10/AP
A0
A1
K
VSS
A4
A5
A2
A3
VDD
D
D1
B
1
F
J
K
E
*2: Top View
A
A1
b
z
*1: Bottom View
< Top View*2 >
#A1 Ball Origin Indicator
Ball Name
Ball Function
CK, CK
System Differential Clock
CS
Chip Select
CKE
Clock Enable
A0 ~ A12
Address
BA0 ~ BA1
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
L(U)DM
Data Input Mask
L(U)DQS
Data Strobe
DQ0 ~ 15
Data Input/Output
VDD/VSS
Power Supply/Ground
VDDQ/VSSQ
Data Output Power/Ground
SEC week XXXX
K4X51163PE
[Unit::mm]
Symbol
-6-
Min
Typ
Max
A
-
-
1.0
A1
0.25
-
-
E
7.9
8.0
8.1
E1
-
6.4
-
D
9.9
10.0
10.1
D1
-
7.2
-
e
-
0.80
-
b
0.45
0.50
0.55
z
-
-
0.10
June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
7. Input/Output Function Description
Symbol
Type
Description
CK, CK
Input
Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Internal clock signals are derived from CK/CK.
CKE
Input
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any banks). CKE is synchronous for all
functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and
CKE , are disabled during power-down and self refresh mode which are contrived for low standby power consumption.
CS
Input
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder.
All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems
with multiple banks. CS is considered part of the command code.
RAS, CAS, WE
Input
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
LDM,UDM
Input
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH
along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include
dummy loading internally, to matches the DQ and DQS loading. For the x16, LDM corresponds to the data on
DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15.
BA0, BA1
Input
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied.
A [n : 0]
Input
Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective
bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one
bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0,
BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1
determines which mode register( mode register or extended mode register ) is loaded during the MODE REGISTER SET command.
DQ
I/O
Data Input/Output : Data bus
LDQS,UDQS
I/O
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write data.
it is used to fetch write data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to
the data on DQ8-DQ15.
NC
-
VDDQ
Supply
DQ Power Supply : 1.7V to 1.95V
VSSQ
Supply
DQ Ground.
VDD
Supply
Power Supply : 1.7V to 1.95V
VSS
Supply
Ground.
No Connect : No internal electrical connection is present.
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June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
8. Functional Description
Figure 1. State diagram
POWER
APPLIED
DEEP
POWER
DOWN
CKEH
POWER
ON
PARTIAL
SELF
REFRESH
SELF
REFRESH
DEEP
POWER
DOWN
PRECHARGE
ALL BANKS
REFS
REFSX
MRS
EMRS
MRS
IDLE
ALL BANKS
PRECHARGED
REFA
AUTO
REFRESH
CKEL
CKEH
ACT
POWER
DOWN
POWER
DOWN
CKEH
ROW
ACTIVE
CKEL
BURST STOP
WRITE
READ
WRITEA
WRITEA
WRITE
READA
READ
READ
READA
WRITEA
READA
PRE
WRITEA
PRE
PRE
READA
PRE
PRECHARGE
PREALL
Automatic Sequence
Command Sequence
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June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
9. Mode Register Definition
9.1. Mode Register Set(MRS)
The mode register is designed to support the various operating modes of Mobile DDR SDRAM. It includes Cas latency, addressing mode,
burst length, test mode and vendor specific options to make Mobile DDR SDRAM useful for variety of applications. The default value of the
mode register is not defined, therefore the mode register must be written in the power up sequence of Mobile DDR SDRAM. The mode register is written by asserting low on CS, RAS, CAS and WE(The Mobile DDR SDRAM should be in active mode with CKE already high prior to
writing into the mode register). The states of address pins A0 ~ A12 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low are
written in the mode register. Two clock cycles are required to complete the write operation in the mode register. Even if the power-up
sequence is finished and some read or write operation is executed afterward, the mode register contents can be changed with the same command and two clock cycles. This command must be issued only when all banks are in the idle state. If mode register is changed, extended
mode register automatically is reset and come into default state. So extended mode register must be set again. The mode register is divided
into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, Cas latency(read latency from column address) uses A4 ~ A6, A7 ~ A12 is used for test mode. BA0 and BA1 must be set to low for proper MRS operation.
Figure 2. Mode Register Set
BA1
0
BA0
0
A12 ~ A10/AP
RFU1)
A9
A8
A7
0
0
0
A6
A5
A4
CAS Latency
A3
BT
A2
A1
A0
Mode Register
Burst Length
A3
Burst Type
0
Sequential
1
Interleave
Address Bus
A6
A5
A4
CAS Latency
A2
A1
A0
Burst Type
0
0
0
Reserved
0
0
0
Reserved
0
0
1
Reserved
0
0
1
2
0
1
0
2
0
1
0
4
0
1
1
3
0
1
1
8
1
0
0
Reserved
1
0
0
16
1
0
1
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
0
Reserved
1
1
1
Reserved
1
1
1
Reserved
NOTE :
1) RFU(Reserved for future use) should stay "0" during MRS cycle
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June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
Table 1. Burst address ordering for burst length
Burst
Length
2
4
8
16
Starting
Address
(A3, A2, A1, A0)
Sequential Mode
Interleave Mode
xxx0
0, 1
0, 1
xxx1
1, 0
1, 0
xx00
0, 1, 2, 3
0, 1, 2, 3
xx01
1, 2, 3, 0
1, 0, 3, 2
xx10
2, 3, 0, 1
2, 3, 0, 1
xx11
3, 0, 1, 2
3, 2, 1, 0
x000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
x001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
x010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
x011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
x100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
x101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
x110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
x111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
0000
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15
0001
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0
1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11,10,13,12,15,14
0010
2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1
2, 3, 0, 1, 6, 7, 4, 5,10,11, 8, 9, 14,15,12,13
0011
3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4,11,10, 9, 8, 15,14,13,12
0100
4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3,12,13,14,15, 8, 9, 10,11
0101
5, 6, 7,8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2,13,12,15,14, 9, 8,11,10
0110
6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1,14,15,12,13,10,11, 8, 9
0111
7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0, 15,14,13,12,11,10, 9, 8
1000
8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7
8, 9,10,11,12,13,14,15, 0, 1, 2, 3, 4, 5, 6, 7
1001
9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7, 8
9, 8, 11,10,13,12,15,14,1, 0, 3, 2, 5, 4, 7, 6
1010
10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
10,11, 8, 9, 14,15,12,13, 2, 3, 0, 1, 6, 7, 4, 5
1011
11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
11,10, 9, 8, 15,14,13,12, 3, 2, 1, 0, 7, 6, 5, 4
1100
12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
12,13,14,15, 8, 9, 10,11, 4, 5, 6, 7, 0, 1, 2, 3
1101
13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,12
13,12,15,14, 9, 8,11,10, 5, 4, 7, 6, 1, 0, 3, 2
1110
14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
14,15,12,13,10,11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1
1111
15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
15,14,13,12,11,10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
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June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
9.2. Extended Mode Register Set(EMRS)
The extended mode register is designed to support partial array self refresh or driver strength control. EMRS cycle is not mandatory and the
EMRS command needs to be issued only when either PASR or DS is used. The default state without EMRS command issued is half driver
strength, and Full array refreshed. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA1 ,low on
BA0(The Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The
state of address pins A0 ~ A12 in the same cycle as CS, RAS, CAS and WE going low is written in the extended mode register. Two clock
cycles are required to complete the write operation in the extended mode register. Even if the power-up sequence is finished and some read
or write operations is executed afterward, the mode register contents can be changed with the same command and two clock cycles. But this
command must be issued only when all banks are in the idle state. A0 - A2 are used for partial array self refresh and A5 - A6 are used for
driver strength control. "High" on BA1 and"Low" on BA0 are used for EMRS. All the other address pins except A0,A1,A2,A5,A6, BA1, BA0
must be set to low for proper EMRS operation. Refer to the table for specific codes.
Figure 3. Extended Mode Register Set
BA1
BA0
A12 ~ A10/AP
1
0
RFU1)
A9
0
A8
0
A7
A6
A5
DS
0
A4
A3
A2
RFU1)
A1
A0
PASR
DS
Address Bus
Mode Register
PASR
A6
A5
Driver Strength
A2
A1
A0
Refreshed Area
0
0
Full
0
0
0
Full Array
0
1
1/2
0
0
1
1/2 Array
1
0
1/4
0
1
0
1/4 Array
1
1
1/8
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
NOTE :
1) RFU(Reserved for future use) should stay "0" during EMRS cycle
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June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
9.3. Internal Temperature Compensated Self Refresh (TCSR)
1. In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control the self
refresh cycle automatically according to the two temperature ranges ; 45 °C and 85 °C.
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
Self Refresh Current (IDD6)
Temperature Range
-E
-G
Full Array
1/2 Array
1/4 Array
Full Array
1/2 Array
1/4 Array
45 °C1)
300
270
255
250
220
205
85 °C
600
500
450
500
400
350
Unit
uA
NOTE :
1) It has +/- 5 °C tolerance.
9.4. Partial Array Self Refresh (PASR)
1. In order to save power consumption, Mobile DDR SDRAM includes PASR option.
2. Mobile DDR SDRAM supports three kinds of PASR in self refresh mode; Full array, 1/2 Array, 1/4 Array.
Figure 4. EMRS code and TCSR , PASR
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
- Full Array
- 1/2 Array
- 1/4 Array
Partial Self Refresh Area
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June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
10. Absolute maximum ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 2.7
V
Voltage on VDD supply relative to VSS
VDD
-0.5 ~ 2.7
V
Voltage on VDDQ supply relative to VSS
VDDQ
-0.5 ~ 2.7
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
1.0
W
Short circuit current
IOS
50
mA
NOTE :
1) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
2) Functional operation should be restricted to recommend operation condition.
3) Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
11. DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, Tc = -25°C to 85°C)
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage(for device with a nominal VDD of 1.8V)
VDD
1.7
1.95
V
1
I/O Supply voltage
VDDQ
1.7
1.95
V
1
Input logic high voltage
VIH(DC)
0.7 x VDDQ
VDDQ+0.3
V
2
Input logic low voltage
VIL(DC)
-0.3
0.3 x VDDQ
V
2
Output logic high voltage
VOH(DC)
0.9 x VDDQ
-
V
IOH = -0.1mA
Output logic low voltage
VOL(DC)
-
0.1 x VDDQ
V
IOL = 0.1mA
Input leakage current
II
-2
2
uA
IOZ
-5
5
uA
Output leakage current
NOTE:
1) Under all conditions, VDDQ must be less than or equal to VDD.
2) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.
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June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
12. DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, Tc = -25 to 85°C)
Parameter
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
Symbol
Test Condition
IDD0
tRC=tRCmin; tCK=tCKmin; CKE is HIGH; CS is HIGH between valid commands;
address inputs are SWITCHING; data bus inputs are STABLE
65
mA
all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
0.3
IDD2PS
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
0.3
IDD2N
all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
15
12
IDD2NS
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
8
8
IDD3P
one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
5
IDD3PS
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
2
IDD3N
one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
25
25
IDD3NS
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
20
20
IDD4R
one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; I OUT =0 mA
address inputs are SWITCHING; 50% data change each burst transfer
140
115
IDD4W
one bank active; BL = 4; tCK = tCKmin ; continuous write bursts;
address inputs are SWITCHING; 50% data change each burst transfer
115
100
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
150
135
mA
451)
85
°C
Full Array
300
600
1/2 Array
270
500
1/4 Array
255
450
Full Array
250
500
1/2 Array
220
400
1/4 Array
205
IDD5
Internal TCSR
-E
IDD6
-G
Deep Power Down Current
70
IDD2P
CKE is LOW; t CK = t CKmin ;
Extended Mode Register set to all 0’s;
address and control inputs are STABLE;
data bus inputs are STABLE
Self Refresh Current
DDR333 DDR266 Unit Note
IDD8
Deep Power Down Mode Current
mA
mA
mA
mA
mA
uA
350
15
uA
2
NOTE :
1) It has +/- 5°C tolerance.
2) DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request.
Please contact Samsung for more information.
3) IDD specifications are tested after the device is properly intialized.
4) Input slew rate is 1V/ns.
5) Definitions for IDD: LOW is defined as V IN ≤ 0.1 * VDDQ ;
HIGH is defined as V IN ≥ 0.9 * VDDQ ;
STABLE is defined as inputs stable at a HIGH or LOW level ;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ;
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
- 14 -
June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
13. AC Operating Conditions & Timming Specification
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, all inputs
VIH(AC)
0.8 x VDDQ
VDDQ+0.3
V
1
Input Low (Logic 0) Voltage, all inputs
VIL(AC)
-0.3
0.2 x VDDQ
V
1
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
0.4 x VDDQ
0.6 x VDDQ
V
2
NOTE :
1) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.
2) The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
- 15 -
June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
14. AC Timming Parameters & Specifications
Parameter
Symbol
Min
DDR266
Max
Min
Max
Unit
12.0
12.0
6
7.5
tRC
60
67.5
Row active time
tRAS
42
RAS to CAS delay
tRCD
18
22.5
ns
tRP
18
22.5
ns
tRRD
12
15
ns
Clock cycle time
CL=2
DDR333
CL=3
Row cycle time
Row precharge time
Row active to Row active delay
tCK
70,000
45
ns
ns
70,000
ns
Write recovery time
tWR
12
15
ns
Last data in to Active delay
tDAL
2tCK+tRP
2tCK+tRP
-
Last data in to Read command
tCDLR
1
1
tCK
Col. address to Col. address delay
tCCD
1
1
tCK
tCH
0.45
0.55
0.45
0.55
tCK
tCL
0.45
0.55
0.45
0.55
tCK
2
8
2
8
2
5.5
2
6
2
8
2
8
2
5.5
2
6
Clock high level width
Clock low level width
DQ Output data access time
from CK/CK
CL=2
DQS Output data access time
from CK/CK
CL=2
CL=3
CL=3
Data strobe edge to ouput data edge
Read Preamble
tAC
tDQSCK
tDQSQ
CL=2
CL=3
tRPRE
0.5
Note
0.6
0.5
1.1
0.5
1.1
0.9
1.1
0.9
1.1
ns
2
3
ns
ns
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
0
ns
DQS-in hold time
tWPREH
0.25
0.25
tCK
DQS-in high level width
tDQSH
0.4
0.6
0.4
0.6
tCK
DQS-in low level width
tDQSL
0.4
0.6
0.4
0.6
tCK
DQS falling edge to CK setup time
tDSS
0.2
0.2
tCK
DQS falling edge hold time from CK
tDSH
0.2
0.2
tCK
DQS-in cycle time
tDSC
0.9
tIS
1.1
1.3
ns
1
Address and Control Input hold time
tIH
1.1
1.3
ns
1
Address & Control input pulse width
tIPW
2.2
2.6
DQ & DM setup time to DQS
tDS
0.6
0.8
ns
5,6
5,6
Address and Control Input setup time
1.1
0.9
1.1
tCK
1
DQ & DM hold time to DQS
tDH
0.6
0.8
ns
DQ & DM input pulse width
tDIPW
1.2
1.8
ns
tLZ
1.0
1.0
ns
DQ & DQS low-impedence time from CK/CK
DQ & DQS high-impedence time from CK/CK
tHZ
5.5
DQS write postamble time
tWPST
0.4
DQS write preamble time
tWPRE
0.25
Refresh interval time
tREF
0.6
0.4
6.0
ns
0.6
tCK
0.25
64
tCK
64
ms
Mode register set cycle time
tMRD
2
2
tCK
Power down exit time
tPDEX
1
1
tCK
- 16 -
4
June 2007
K4X51163PE - L(F)E/G
Parameter
Mobile DDR SDRAM
Symbol
CKE min. pulse width(high and low pulse width)
tCKE
DDR333
Min
DDR266
Max
Min
2
Unit
Max
2
tCK
Auto refresh cycle time
tRFC
72
80
ns
Exit self refresh to active command
tXSR
120
120
ns
Data hold from DQS to earliest DQ edge
tQH
tHPmin tQHS
tHPmin tQHS
ns
Data hold skew factor
tQHS
Clock half period
tHP
0.65
0.75
tCLmin or
tCHmin
Note
7
ns
tCLmin or
tCHmin
ns
NOTE :
1) Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
∆tIS
∆tIH
(V/ns)
(ps)
(ps)
1.0
0
0
0.8
+50
+50
0.6
+100
+100
This derating table is used to increase tIS/tIH in the case where the input slew rate is below 1.0V/ns.
2) Minimum 3CLK of tDAL(= tWR + tRP) is required because it need minimum 2CLK for tWR and minimum 1CLK for tRP.
3) tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25°C).
tAC(max) value is measured at the low Vdd(1.7V) and hot temperature(85°C).
tAC is measured in the device with half driver strength and under the AC output load condition (Fig.6 in next Page).
4) The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
5) I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
∆tIS
∆tIH
(V/ns)
(ps)
(ps)
1.0
0
0
0.8
+75
+75
0.6
+150
+150
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 1.0V/ns.
6) I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Data Rise/Fall Rate
∆tIS
∆tIH
(ns/V)
(ps)
(ps)
0
0
0
±0.25
+50
+50
±0.5
+100
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as
1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall Rate =-0.25ns/V.
7) Maximum burst refresh cycle : 8
- 17 -
June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
15. AC Operating Test Conditions(VDD = 1.7V to 1.95V, Tc = -25 to 85°C)
Parameter
Value
Unit
AC input levels (Vih/Vil)
0.8 x VDDQ / 0.2 x VDDQ
V
Input timing measurement reference level
0.5 x VDDQ
V
Input signal minimum slew rate
1.0
V/ns
Output timing measurement reference level
0.5 x VDDQ
V
Output load condition
See Figure 6
1.8V
13.9KΩ
VOH (DC) = 0.9 x VDDQ , IOH = -0.1mA
VOL (DC) = 0.1 x VDDQ , IOL = 0.1mA
Output
20pF
10.6KΩ
Figure 5. DC Output Load Circuit
Vtt=0.5 x VDDQ
50Ω
Output
Z0=50Ω
20pF
Figure 6. AC Output Load Circuit
16. Input/Output Capacitance(VDD=1.8, VDDQ=1.8V, TC = 25°C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance
(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
CIN1
1.5
3.0
pF
Input capacitance( CK, CK )
CIN2
1.5
3.5
pF
Data & DQS input/output capacitance
COUT
2.0
4.5
pF
Input capacitance(DM)
CIN3
2.0
4.5
pF
- 18 -
June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
17. AC Overshoot/Undershoot Specification for Address & Control Pins
Parameter
Specification
Maximum peak Amplitude allowed for overshoot area
0.9V
Maximum peak Amplitude allowed for undershoot area
0.9V
Maximum overshoot area above VDD
3V-ns
Maximum undershoot area below VSS
3V-ns
Maximum Amplitude
Overshoot Area
Volts
(V)
VDD
VSS
Maximum Amplitude
Undershoot Area
Time (ns)
Figure 7. AC Overshoot and Undershoot Definition for Address and Control Pins
18. AC Overshoot/Undershoot Specification for CLK, DQ, DQS and DM Pins
Parameter
Specification
Maximum peak Amplitude allowed for overshoot area
0.9V
Maximum peak Amplitude allowed for undershoot area
0.9V
Maximum overshoot area above VDDQ
3V-ns
Maximum undershoot area below VSSQ
3V-ns
Maximum Amplitude
Overshoot Area
Volts
(V)
VDDQ
VSSQ
Maximum Amplitude
Undershoot Area
Time (ns)
Figure 8. AC Overshoot and Undershoot Definition for CLK, DQ, DQS and DM Pins
- 19 -
June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
19. Command Truth Table
Command
Register
Mode Register Set
Auto Refresh
Entry
Refresh
Self
Refresh
Exit
RAS
CAS
WE
H
X
L
L
L
L
OP CODE
L
L
L
H
X
L
H
H
H
H
X
X
X
H
H
L
BA0,1
H
X
L
L
H
H
V
H
X
L
H
L
H
V
H
X
L
H
L
L
V
Entry
H
L
L
H
H
L
Exit
L
H
H
X
X
X
H
X
L
H
H
L
H
X
L
L
H
L
Entry
H
L
H
X
X
X
L
V
V
V
Exit
L
H
X
X
X
X
Entry
H
L
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
Auto Precharge Disable
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Enable
Burst Stop
Bank Selection
All Banks
Active Power Down
CS
H
Read &
Column Address
Precharge
CKEn
L
Bank Active & Row Addr.
Deep Power Down
CKEn-1
Precharge Power Down
Exit
L
DM
H
No operation (NOP) : Not defined
H
H
X
X
A10/AP
X
X
X
L
H
H
H
Note
1, 2
3
3
3
X
3
Row Address
L
Column
Address
(A0~A9)
H
L
Column
Address
(A0~A9)
H
4
4
4
4, 6
X
X
V
L
X
H
7
X
5
X
X
X
H
A12,A11,
A9~A0
X
8
9
9
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
NOTE :
1) OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2) EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3) Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4) BA0 ~ BA1 : Bank select addresses.
5) If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6) During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7) Burst stop command is valid at every burst length.
8) DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9) This combination is not defined for any function, which means "No Operation(NOP)" in Mobile DDR SDRAM.
- 20 -
June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
20. Functional Truth Table
Current State
PRECHARGE
STANDBY
ACTIVE
STANDBY
CS
RAS
CAS
WE
Address
Command
Action
L
H
H
L
X
Burst Stop
ILLEGAL2)
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL2)
L
L
H
H
BA, RA
Active
Bank Active, Latch RA
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL4)
L
L
L
H
X
Refresh
AUTO-Refresh5)
L
L
L
L
Op-Code, Mode-Add
MRS
Mode Register Set5)
L
H
H
L
X
Burst Stop
NOP
L
H
L
H
BA, CA, A10
READ/READA
Begin Read, Latch CA,
Determine Auto-Precharge
L
H
L
L
BA, CA, A10
WRITE/WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
L
L
H
H
BA, RA
Active
Bank Active/ILLEGAL2)
L
L
H
L
BA, A10
PRE/PREA
Precharge/Precharge All
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
Terminate Burst
READ/READA
Terminate Burst, Latch CA,
Begin New Read, Determine
L
H
L
H
BA, CA, A10
Auto-Precharge3)
READ
L
H
L
L
BA, CA, A10
WRITE/WRITEA
ILLEGAL
L
L
H
H
BA, RA
Active
Bank Active/ILLEGAL2)
L
L
H
L
BA, A10
PRE/PREA
Terminate Burst, Precharge10)
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
MRS
ILLEGAL
L
H
H
L
L
WRITE
READ with
AUTO
PRECHARGE6)
(READA)
H
L
H
Op-Code, Mode-Add
X
Burst Stop
BA, CA, A10
READ/READA
ILLEGAL
Terminate Burst With DM=High,
Latch CA, Begin Read, Determine
Auto-Precharge3)
Terminate Burst, Latch CA,
Begin new Write, Determine Auto-
L
H
L
L
BA, CA, A10
WRITE/WRITEA
L
L
H
H
BA, RA
Active
L
L
H
L
BA, A10
PRE/PREA
L
L
L
H
X
Refresh
ILLEGAL
Precharge3)
Bank Active/ILLEGAL2)
Terminate Burst With DM=High,
Precharge10)
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
6)
L
H
L
L
BA, CA, A10
WRITE/WRITEA
ILLEGAL
L
L
H
H
BA, RA
Active
6)
L
L
H
L
BA, A10
PRE/PREA
6)
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
- 21 -
June 2007
K4X51163PE - L(F)E/G
Current State
Mobile DDR SDRAM
CS
RAS
CAS
WE
L
H
H
L
L
H
L
H
BA, CA, A10
READ/READA
7)
L
H
L
L
BA, CA, A10
WRITE/WRITEA
7)
L
L
H
H
BA, RA
Active
7)
L
L
H
L
BA, A10
PRE/PREA
7)
L
L
L
H
X
Refresh
L
L
L
L
L
H
H
L
X
Burst Stop
ILLEGAL2)
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL2)
L
L
H
H
BA, RA
Active
ILLEGAL2)
L
L
H
L
BA, A10
PRE/PREA
NOP4)(Idle after tRP)
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL2)
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL2)
L
L
H
H
BA, RA
Active
ILLEGAL2)
ACTIVE TO
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL2)
tRCD)
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL2)
L
H
L
H
BA, CA, A10
READ
ILLEGAL2)
L
H
L
L
BA, CA, A10
WRITE
WRITE
(DURING tWR
L
L
H
H
BA, RA
Active
ILLEGAL2)
OR tCDLR)
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL2)
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL
L
L
H
H
BA, RA
Active
ILLEGAL
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL
L
L
H
H
BA, RA
Active
ILLEGAL
WRITE with
AUTO
RECHARGE7)
(WRITEA)
PRECHARGING
(DURING tRP)
ROW
ACTIVATING
(FROM ROW
WRITE
RECOVERING
REFRESHING
MODE
REGISTER
SETTING
Address
Command
X
Burst Stop
Op-Code, Mode-Add MRS
Action
ILLEGAL
ILLEGAL
ILLEGAL
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
- 22 -
June 2007
K4X51163PE - L(F)E/G
Mobile DDR SDRAM
CKE
n-1
CKE
n
CS
L
H
H
X
X
X
X
Exit Self-Refresh
L
H
L
H
H
H
X
Exit Self-Refresh
SELF-
L
H
L
H
H
L
X
ILLEGAL
REFRESHING8)
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
POWER
DOWN
L
H
X
X
X
X
X
Exit Power Down(Idle after tPDEX)
L
L
X
X
X
X
X
NOP (Maintain Power Down)
DEEP POWER
L
H
H
X
X
X
X
Exit Deep Power Down10)
DOWN
L
L
X
X
X
X
X
NOP (Maintain Deep Power Down)
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
Enter Deep Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State=Power Down
Current State
ALL BANKS
IDLE9)
RAS
CAS
WE
Add
Action
(H=High Level, L=Low level, X=Don′t Care)
NOTE :
1) All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2) ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank.
(ILLEGAL = Device operation and/or data integrity are not guaranteed.)
3) Must satisfy bus contention, bus turn around and write recovery requirements.
4) NOP to bank precharging or in idle sate. May precharge bank indicated by BA.
5) ILLEGAL if any bank is not idle.
6) Refer to "Read with Auto Precharge Timing Diagram" for detailed information.
7) Refer to "Write with Auto Precharge Timing Diagram" for detailed information.
8) CKE Low to High transition will re-enable CK, CK and other inputs asynchronously.
A minimum setup time must be satisfied before issuing any command other than EXIT.
9) Power-Down, Self-Refresh and Deep Power Down Mode can be entered only from All Bank Idle state.
10) The Deep Power Down Mode is exited by asserting CKE high and full initialization is required after exiting Deep Power Down Mode.
- 23 -
June 2007