HYNIX HY5DU561622FTP-5I

HY5DU561622FTP-5I / HY5DU561622FTP-4I
256M(16Mx16) DDR SDRAM
HY5DU561622F(L)TP-5I
HY5DU561622F(L)TP-4I
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1 / Mar. 2008
1
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
Revision History
Revision No.
History
Draft Date
1.0
First Version Release
Nov. 2007
1.1
Correction
- P.3 Ordering Information
Mar. 2008
Rev. 1.1 / Mar. 2008
Remark
2
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
DESCRIPTION
The Hynix HY5DU561622FTP-5I, -4I series are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM,
ideally suited for the point-to-point applications which requires high bandwidth.
The Hynix 16Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
•
VDD, VDDQ = 2.5V + / - 0.2V for 200MHz
VDD, VDDQ = 2.6V + 0.1 / -0.2V for 250MHz
•
All inputs and outputs are compatible with SSTL_2
interface
•
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
•
Write mask byte controls by LDM and UDM
•
Programmable /CAS latency 3 / 4 supported
•
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
•
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
•
Fully differential clock inputs (CK, /CK) operation
•
Double data rate interface
•
Internal 4 bank operations with single pulsed /RAS
•
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
•
tRAS Lock-Out function supported
•
Auto refresh and self refresh supported
•
x16 device has 2 bytewide data strobes (LDQS,
UDQS) per each x8 I/O
•
8192 refresh cycles / 64ms
•
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
•
Full, Half and Matched Impedance(Weak) strength
driver option controlled by EMRS
•
Operation temperature : -40oC to 85oC
•
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
ORDERING INFORMATION
Part No.
Power Supply
(VDD, VDDQ)
Clock
Frequency
Max Data
Rate
HY5DU561622FTP-4I
2.6V + 0.1 / - 0.2V
250MHz
500Mbps/pin
HY5DU561622FTP-5I
2.5V + / - 0.2V
200MHz
400Mbps/pin
Rev. 1.1 / Mar. 2008
interface
Temp
SSTL-2
IT Part
Package
400mil 66pin
TSOP-II
3
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
PIN CONFIGURATION
V DD
DQ0
VDDQ
DQ1
DQ2
V SSQ
DQ3
DQ4
V DDQ
DQ5
DQ6
V SSQ
DQ7
NC
V DDQ
LDQS
NC
V DD
NC
LDM
/WE
/ CAS
/ RAS
/ CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
TOP VIEW
400 mil X 875mil
66 Pin TSOP
- II
0.65mm Pin Pitch
V SS
DQ15
V SSQ
DQ14
DQ13
V DDQ
DQ12
DQ11
V SSQ
DQ10
DQ9
V DDQ
DQ8
NC
V SSQ
UDQS
NC
V REF
V SS
UDM
/ CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V SS
ROW and COLUMN ADDRESS TABLE
Rev. 1.1 / Mar. 2008
Items
16Mx16
Organization
4M x 16 x 4banks
Row Address
A0 ~ A12
Column Address
A0 ~ A8
Bank Address
BA0, BA1
Auto Precharge Flag
A10
Refresh
8K
4
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
PIN DESCRIPTION
PIN
TYPE
CK, /CK
Input
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied.
/CS
Input
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All commands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied.
A0 ~ A12
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
/RAS, /CAS, /WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
LDM, UDM
Input
Input Data Mask: DM(LDM,UDM) is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a WRITE access.
DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. LDM corresponds to the data on DQ0-Q7; UDM corresponds to the data on DQ8-Q15.
LDQS, UDQS
I/O
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. LDQS corresponds to the data on
DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.
DQ0 ~ DQ15
I/O
Data input / output pin : Data Bus
VDD/VSS
Supply
Power supply for internal circuits and input buffers.
VDDQ/VSSQ
Supply
Power supply for output buffers for noise immunity.
VREF
Supply
Reference voltage for inputs for SSTL interface.
NC
NC
Rev. 1.1 / Mar. 2008
DESCRIPTION
No connection.
5
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
FUNCTIONAL BLOCK DIAGRAM
4Banks x 4Mbit x 16 I/O Double Data Rate Synchronous DRAM
In p u t B u ffer
16
W rite Data Register
2-bit Prefetch Unit
32
4Mx16/Bank0
4Mx16 /Bank2
4Mx16 /Bank3
Mode
Register
64
32
O u tpu t B u ffer
4Mx16 /Bank1
Command
Decoder
2 -b it Prefe tch U n it
Bank
Control
S en se A M P
CLK
/CLK
CKE
/CS
/RAS
/CAS
LDM
UDM
DS
DQ[0:15]
Row
Decoder
Column Decoder
A0-12
BA0,BA1
LDQS,UDQS
Address
Buffer
Column Address
Counter
Data Strobe
Transmitter
CLK_DLL
DS
CLK,
/CLK
Data Strobe
Receiver
DLL
Block
Mode
Register
Rev. 1.1 / Mar. 2008
6
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
SIMPLIFIED COMMAND TRUTH TABLE
A10/
AP
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
Extended Mode Register Set
H
X
L
L
L
L
OP code
1,2
Mode Register Set
H
X
L
L
L
L
OP code
1,2
H
X
H
X
X
X
L
H
H
H
X
1
H
X
L
L
H
H
H
X
L
H
L
H
CA
H
X
L
H
L
L
CA
H
X
L
L
H
L
X
Read Burst Stop
H
X
L
H
H
L
X
1
Auto Refresh
H
H
L
L
L
H
X
1
Entry
H
L
L
L
L
H
Exit
L
H
H
X
X
X
L
H
H
H
Entry
H
L
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
1
H
X
X
X
1
L
V
V
V
Device Deselect
No Operation
Bank Active
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Self Refresh
Precharge Power
Down Mode
Active Power
Down Mode
Exit
L
H
Entry
H
L
Exit
L
H
X
ADDR
RA
BA
V
L
H
L
H
V
V
Note
1
1
1,3
1
1,4
H
X
1,5
L
V
1
1
X
1
1
X
X
1
1
1
1
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
Rev. 1.1 / Mar. 2008
7
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
WRITE MASK TRUTH TABLE
Function
A10/
AP
CKEn-1
CKEn
/CS, /RAS, /CAS, /WE
LDM
UDM
Data Write
H
X
X
L
L
X
1,2
Data-In Mask
H
X
X
H
H
X
1,2
Lower Byte Write /
Upper Byte-In Mask
H
X
X
L
H
X
1,2
Upper Byte Write /
Lower Byte-In Mask
H
X
X
H
L
X
1,2
ADDR
BA
Note
Note :
1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data.
2. LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively.
Rev. 1.1 / Mar. 2008
8
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
OPERATION COMMAND TRUTH TABLE - I
Current
State
IDLE
ROW
ACTIVE
READ
WRITE
/CS
/RAS
/CAS
/WE
Address
Command
Action
H
X
X
X
X
DSEL
NOP or power down3
L
H
H
H
X
NOP
NOP or power down3
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4
L
L
H
H
BA, RA
ACT
Row Activation
L
L
H
L
BA, AP
PRE/PALL
NOP
L
L
L
H
X
AREF/SREF
Auto Refresh or Self Refresh5
L
L
L
L
OPCODE
MRS
Mode Register Set
H
X
X
X
X
DSEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
Begin read : optional AP6
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
Begin write : optional AP6
L
L
H
H
BA, RA
ACT
ILLEGAL4
L
L
H
L
BA, AP
PRE/PALL
Precharge7
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
Terminate burst
L
H
L
H
BA, CA, AP
READ/READAP
Term burst, new read:optional AP8
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL4
L
L
H
L
BA, AP
PRE/PALL
Term burst, precharge
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
Term burst, new read:optional AP8
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
Term burst, new write:optional AP
Rev. 1.1 / Mar. 2008
9
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
OPERATION COMMAND TRUTH TABLE - II
Current
State
WRITE
READ
WITH
AUTOPRECHARGE
WRITE
AUTOPRECHARGE
PRECHARGE
/CS
/RAS
/CAS
/WE
Address
Command
Action
L
L
H
H
BA, RA
ACT
ILLEGAL4
L
L
H
L
BA, AP
PRE/PALL
Term burst, precharge
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,10
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
Continue burst to end
L
H
H
H
X
NOP
Continue burst to end
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,10
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP-Enter IDLE after tRP
L
H
H
H
X
NOP
NOP-Enter IDLE after tRP
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4,10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4,10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
NOP-Enter IDLE after tRP
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
Rev. 1.1 / Mar. 2008
10
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
OPERATION COMMAND TRUTH TABLE - III
Current
State
ROW
ACTIVATING
WRITE
RECOVERING
WRITE
RECOVERING
WITH
AUTOPRECHARGE
REFRESHING
/CS
/RAS
/CAS
/WE
Address
Command
Action
H
X
X
X
X
DSEL
NOP - Enter ROW ACT after tRCD
L
H
H
H
X
NOP
NOP - Enter ROW ACT after tRCD
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4,10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4,10
L
L
H
H
BA, RA
ACT
ILLEGAL4,9,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,10
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP - Enter ROW ACT after tWR
L
H
H
H
X
NOP
NOP - Enter ROW ACT after tWR
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,11
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP - Enter precharge after tDPL
L
H
H
H
X
NOP
NOP - Enter precharge after tDPL
L
H
H
L
X
BST
ILLEGAL4
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL4,8,10
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL4,10
L
L
H
H
BA, RA
ACT
ILLEGAL4,10
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL4,11
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP - Enter IDLE after tRC
L
H
H
H
X
NOP
NOP - Enter IDLE after tRC
L
H
H
L
X
BST
ILLEGAL11
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL11
Rev. 1.1 / Mar. 2008
11
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
OPERATION COMMAND TRUTH TABLE - IV
Current
State
WRITE
MODE
REGISTER
ACCESSING
/CS
/RAS
/CAS
/WE
Address
Command
Action
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL11
L
L
H
H
BA, RA
ACT
ILLEGAL11
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL11
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
H
X
X
X
X
DSEL
NOP - Enter IDLE after tMRD
L
H
H
H
X
NOP
NOP - Enter IDLE after tMRD
L
H
H
L
X
BST
ILLEGAL11
L
H
L
H
BA, CA, AP
READ/READAP
ILLEGAL11
L
H
L
L
BA, CA, AP
WRITE/WRITEAP
ILLEGAL11
L
L
H
H
BA, RA
ACT
ILLEGAL11
L
L
H
L
BA, AP
PRE/PALL
ILLEGAL11
L
L
L
H
X
AREF/SREF
ILLEGAL11
L
L
L
L
OPCODE
MRS
ILLEGAL11
Note :
1. H - Logic High Level, L - Logic Low Level, X - Don’t Care, V - Valid Data Input,
BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation.
2. All entries assume that CKE was active(high level) during the preceding clock cycle.
3. If both banks are idle and CKE is inactive(low level), then in power down mode.
4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of
that bank.
5. If both banks are idle and CKE is inactive(low level), then self refresh mode.
6. Illegal if tRCD is not met.
7. Illegal if tRAS is not met.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Illegal if tRRD is not met.
10. Illegal for single bank, but legal for other banks in multi-bank devices.
11. Illegal for all banks.
Rev. 1.1 / Mar. 2008
12
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
CKE FUNCTION TRUTH TABLE
Current
State
SELF
REFRESH1
POWER
DOWN2
ALL BANKS
IDLE4
ANY STATE
OTHER
THAN
ABOVE
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
/ADD
Action
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit self refresh, enter idle after tSREX
L
H
L
H
H
H
X
Exit self refresh, enter idle after tSREX
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP, continue self refresh
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit power down, enter idle
L
H
L
H
H
H
X
Exit power down, enter idle
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP, continue power down mode
H
H
X
X
X
X
X
See operation command truth table
H
L
L
L
L
H
X
Enter self refresh
H
L
H
X
X
X
X
Exit power down
H
L
L
H
H
H
X
Exit power down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
H
X
X
ILLEGAL
H
L
L
L
L
L
X
ILLEGAL
L
L
X
X
X
X
X
NOP
H
H
X
X
X
X
X
See operation command truth table
H
L
X
X
X
X
X
ILLEGAL5
L
H
X
X
X
X
X
INVALID
L
L
X
X
X
X
X
INVALID
Note :
When CKE=L, all DQ and DQS must be in Hi-Z state.
1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.
2. All command can be stored after 2 clocks from low to high transition of CKE.
3. Illegal if CK is suspended or stopped during the power down mode.
4. Self refresh can be entered only from the all banks idle state.
5. Disabling CK may cause malfunction of any bank which is in active state.
Rev. 1.1 / Mar. 2008
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1HY5DU561622FTP-5I
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SIMPLIFIED STATE DIAGRAM
MRS
MODE
R E G IS T E R
SET
SREF
SELF
REFRESH
ID L E
SREX
PDEN
PDEX
AREF
ACT
POW ER
DOW N
POW ER
DOW N
AUTO
REFRESH
PDEN
BST
PDEX
BANK
A C T IV E
READ
W R IT E
READ
W R IT E
W R IT E A P
W R IT E
W IT H
AUTOPRECHARGE
P R E (P A LL)
READAP
READ
READAP
W IT H
AUTO PRECHARGE
W R IT E A P
READ
W R IT E
P R E (P A LL)
P R E (P A LL)
PRECHARGE
P O W E R -U P
C o m m a n d In p u t
A u t o m a t ic S e q u e n c e
P O W E R A P P L IE D
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POWER-UP SEQUENCE AND DEVICE INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those
specified may result in undefined operation. Except for CKE, inputs are not recognized as valid until after VREF is
applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS
LOW level on CKE during power-up is required to guarantee that the DQ and DQS outputs will be in the High-Z state,
where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200us delay prior to applying an executable command.
Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED
MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE
REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating
parameters. After the DLL reset, tXSRD(DLL locking time) should be satisfied for read command. After the Mode Register set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command
for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting
the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.
1.
Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVCMOS low state. (All the other input pins may be undefined.
No power sequencing is specified during power up or power down given the following cirteria :
• VDD and VDDQ are driven from a single power converter output.
• VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation).
• VREF tracks VDDQ/2.
• A minimum resistance of 42 ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the
input current from the VTT supply into any pin.
If the above criteria cannot be met by the system design, then the following sequencing and voltage relationship must
be adhered to during power up :
Voltage description
Sequencing
Voltage relationship to avoid latch-up
VDDQ
After or with VDD
< VDD + 0.3V
VTT
After or with VDDQ
< VDDQ + 0.3V
VREF
After or with VDDQ
< VDDQ + 0.3V
2.
Start clock and maintain stable clock for a minimum of 200usec.
3.
After stable power and clock, apply NOP condition and take CKE high.
4.
Issue Extended Mode Register Set (EMRS) to enable DLL.
5.
Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200
cycles(tXSRD) of clock are required for locking DLL)
6.
Issue Precharge commands for all banks of the device.
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7.
Issue 2 or more Auto Refresh commands.
8.
Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.
Power-Up Sequence
VDD
VDDQ
tVTD
VTT
VREF
/CLK
CLK
tIS tIH
CKE
LVCMOS Low Level
CMD
NOP
PRE
EMRS
MRS
ADDR
CODE
A10
BA0, BA1
NOP
PRE
MRS
ACT
RD
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
Non-Read
Command
READ
AREF
DM
DQS
DQ'S
T=200usec
tRP
tMRD
tMRD
tRP
tRFC
tMRD
tXSRD*
Power UP
VDD and CK stable
Precharge All
EMRS Set
MRS Set
Reset DLL
(with A8=H)
Precharge All
2 or more
Auto Refresh
MRS Set
(with A8=L)
* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command
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MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low
signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE
must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write
the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until resetted by another MRS command.
BA1
BA0
0
0
A12
A11
A10
A9
RFU
A8
A7
DR
TM
A6
A5
A4
A3
CAS Latency
BA0
MRS Type
A7
Test Mode
0
MRS
0
Normal
1
EMRS
1
Test
A2
BT
A1
A0
Burst Length
Burst Length
Rev. 1.1 / Mar. 2008
A8
DLL Reset
0
No
1
Yes
A2
A1
A0
Sequential
Interleave
0
0
0
Reserved
Reserved
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
A6
A5
A4
CAS Latency
1
0
0
Reserved
Reserved
0
0
0
Reserved
1
0
1
Reserved
Reserved
0
0
1
Reserved
1
1
0
Reserved
Reserved
0
1
0
Reserved
1
1
1
Reserved
Reserved
0
1
1
3
1
0
0
4
A3
Burst Type
1
0
1
Reserved
0
Sequential
1
1
0
Reserved
1
Interleave
1
1
1
Reserved
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BURST DEFINITION
Burst Length
Starting Address (A2,A1,A0)
Sequential
Interleave
XX0
0, 1
0, 1
XX1
1, 0
1, 0
X00
0, 1, 2, 3
0, 1, 2, 3
X01
1, 2, 3, 0
1, 0, 3, 2
X10
2, 3, 0, 1
2, 3, 0, 1
X11
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
2
4
8
BURST LENGTH & TYPE
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst
length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is
set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a
given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to both Read and Write bursts.
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Burst Definitionon Table
CAS LATENCY
The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the
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availability of the first burst of output data. The latency can be programmed 3 or 4 or 5 clocks.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident
with clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
DLL RESET
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically
disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any
time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally
applied clock before an any command can be issued.
OUTPUT DRIVER IMPEDANCE CONTROL
The HY5DU561622FTP supports Full, Half strength driver and Matched impedance driver, intended for lighter load and/
or point-to-point environments. The Full drive strength for all output is specified to be SSTL_2, CLASS II. Half strength
driver is to define about 50% of Full drive strength and Matched impedance driver, about 30% of Full drive strength.
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EXTENDED MODE REGISTER SET (EMRS)
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits
shown below. The Extended Mode Register is programmed via the Mode Register Set command ( BA0=1 and BA1=0)
and will retain the stored information until it is programmed again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller
must wait the specified time before initiating any subsequent operation. Violating either of these requirements will
result in unspecified operation.
BA1
BA0
0
1
A12
A11
A10
A9
RFU*
BA0
MRS Type
0
MRS
1
EMRS
A8
A7
A6
DS
A5
A4
A3
RFU*
A2
A1
A0
DS
DLL
A0
DLL enable
0
Enable
1
Diable
A6
A1
Output Driver Impedance Control
0
0
Full
0
1
Half
1
0
RFU*
1
1
RFU*
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.
Rev. 1.1 / Mar. 2008
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ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Ambient Temperature
TA
-40 ~ 85
o
C
Storage Temperature
TSTG
-55 ~ 125
o
C
VIN, VOUT
-0.5 ~ 3.6
V
V
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Output Short Circuit Current
Power Dissipation
Soldering Temperature ⋅ Time
Unit
VDD
-0.5 ~ 3.6
VDDQ
-0.5 ~ 3.6
V
IOS
50
mA
PD
1
TSOLDER
260 ⋅ 10
W
o
C ⋅ sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
Parameter
(TA=-40 ~ 85oC, Voltage referenced to VSS = 0V)
Symbol
Min
Typ.
Max
Unit
Power Supply Voltage
VDD
2.4
2.6
2.7
V
Note
5
Power Supply Voltage
VDDQ
2.4
2.6
2.7
V
5, 1
Input High Voltage
VIH
VREF + 0.15
-
VDDQ + 0.3
V
Input Low Voltage
VIL
-0.3
-
VREF - 0.15
V
Termination Voltage
VTT
VREF - 0.04
VREF
VREF + 0.04
V
Reference Voltage
VREF
0.49*VDDQ
0.5*VDDQ
0.51*VDDQ
V
2
3
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with ≤ 5ns of duration.
3. VIH (max) is acceptable VDDQ + 1.5V AC pulse width with < 5ns of duration
4. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same.
Peak to peak noise on VREF may not exceed ± 2% of the dc value.
5. Supports 250/ 200 Mhz
DC CHARACTERISTICS I
Parameter
Input Leakage Current
(TA=-40 ~ 85oC, Voltage referenced to VSS = 0V)
Symbol
Min.
Max
Unit
Note
ILI
-5
5
uA
1
Output Leakage Current
ILO
-5
5
uA
Output High Voltage
VOH
VTT + 0.76
-
V
IOH = -15.2mA
2
Output Low Voltage
VOL
-
VTT - 0.76
V
IOL = +15.2mA
Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN = 0V. 2. DOUT is disabled, VOUT = 0 to 2.7V
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DC CHARACTERISTICS II
Parameter
Symbol
(TA=-40 ~ 85oC, Voltage referenced to VSS = 0V)
Test Condition
Speed
4
5
Unit
Operating Current
IDD1
One bank; Active - Read - Precharge;
Burst Length=4; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per clock
cycle; IOUT=0mA
160
150
mA
Precharge Power Down
Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
20
20
mA
Idle Standby Current
IDD2N
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing
once per clock cycle.
VIN=VREF for DQ, DQS and DM
80
70
mA
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode ; CKE=Low,
tCK=tCK(min)
55
50
mA
IDD3N
/CS=HIGH; CKE=HIGH; One bank; ActivePrecharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing
once per clock cycle
90
80
mA
IDD4R
Burst=2;Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
220
200
mA
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
220
200
mA
200
180
mA
5
5
mA
Active Standby Current
Operating Current
Auto Refresh Current
IDD5
tRC=tRFC(min); All banks active
Self Refresh Current
IDD6
CKE=<0.2V; External clock on; tCK=tCK(min)
Rev. 1.1 / Mar. 2008
Note
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AC OPERATING CONDITIONS (TA=-40 ~ 85oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Max
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.35
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
Input Differential Voltage, CK and /CK inputs
VID(AC)
Input Crossing Point Voltage, CK and /CK inputs
VIX(AC)
Unit
Note
V
VREF - 0.35
V
0.7
VDDQ + 0.6
V
1
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=-40 ~ 85oC, Voltage referenced to VSS = 0V)
Parameter
Value
Unit
Reference Voltage
VDDQ x 0.5
V
Termination Voltage
VDDQ x 0.5
V
AC Input High Level Voltage (VIH, min)
VREF + 0.35
V
AC Input Low Level Voltage (VIL, max)
VREF - 0.35
V
Input Timing Measurement Reference Level Voltage
VREF
V
Output Timing Measurement Reference Level Voltage
VTT
V
Input Signal maximum peak swing
1.5
V
Input minimum Signal Slew Rate
1
V/ns
Termination Resistor (RT)
50
Ω
Series Resistor (RS)
25
Ω
Output Load Capacitance for Access Time Measurement (CL)
30
pF
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AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter
Symbol
4
5
Unit
Min
Max
Min
Max
Row Cycle Time
(Manual Precharge)
tRC
15
-
12
-
CK
Row Cycle Time
(Auto Precharge)
tRC_APCG
17
-
14
-
CK
Auto Refresh Row Cycle Time
tRFC
18
-
14
-
CK
Row Active Time
tRAS
40
70K
40
70K
ns
tRCDRD
5
-
4
-
CK
tRCDWT
2
-
2
-
CK
Row Active to Row Active Delay
tRRD
2
-
2
-
CK
Column Address to Column Address Delay
tCCD
1
-
1
-
CK
Row Precharge Time
tRP
5
-
4
-
CK
Last Data-In to Precharge Delay
(Write Recovery Time : tWR)
tDPL
4
-
3
-
CK
Last Data-In to Read Command
tDRL
2
-
2
-
CK
tDAL
9
-
7
-
CK
4.0
7.0
-
-
ns
-
-
5.0
7.0
ns
Row Address to Column Address Delay
Auto Precharge Write Recovery +
Time
System Clock Cycle Time
Precharge
CL = 4.0
CL = 3.0
tCK
Note
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
CK
Data-Out edge to Clock edge Skew
tAC
-0.7
0.7
-0.7
0.7
ns
DQS-Out edge to Clock edge Skew
tDQSCK
-0.7
0.7
-0.7
0.7
ns
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.4
-
0.45
ns
Data-Out hold time from DQS
tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns
1, 6
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
ns
1, 5
Data Hold Skew Factor
tQHS
-
0.4
-
0.5
ns
6
Input Setup Time
tIS
0.75
-
0.75
-
ns
2
Input Hold Time
tIH
0.75
-
0.75
-
ns
2
Write DQS High Level Width
tDQSH
0.4
0.6
0.4
0.6
CK
Write DQS Low Level Width
tDQSL
0.4
0.6
0.4
0.6
CK
Clock to First Rising edge of DQS-In
tDQSS
0.85
1.15
0.75
1.25
CK
Data-In Setup Time to DQS-In (DQ & DM)
tDS
0.4
-
0.4
-
ns
Rev. 1.1 / Mar. 2008
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Parameter
Symbol
4
5
Min
Max
Min
Max
Unit
Note
3
Data-In Hold Time to DQS-In (DQ & DM)
tDH
0.4
-
0.4
-
ns
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
CK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
CK
Write DQS Preamble Setup Time
tWPRES
0
-
0
-
ns
Write DQS Preamble Hold Time
tWPREH
1.5
-
1.5
-
ns
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
CK
Mode Register Set Delay
tMRD
2
-
2
-
CK
Exit Self Refresh to Any Execute Command
tXSC
200
-
200
-
CK
Except Read
Command
tPDEX
1tCK
+ tIS
-
1tCK
+ tIS
-
CK
Read Command
tPDEX_RD
2tCK
+ tIS
-
2tCK
+ tIS
-
CK
-
7.8
-
7.8
us
Power Down Exit Time
Average Periodic Refresh Interval
tREFI
4
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
4. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
5. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
6. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to
n-channel variation of the output drivers.
7. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transitions through the DC region must be monotonic.
Rev. 1.1 / Mar. 2008
25
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
AC CHARACTERISTICS - II
tRC
Frequency
CL
250MHz
(4.0ns)
4
15
200MHz
(5.0ns)
3
12
(Manual Precharge)
Rev. 1.1 / Mar. 2008
tRC_APCG
tRFC
tRAS
tRCDRD
tRCDWT
tRP
tDAL
Unit
17
18
40ns
5
2
5
9
tCK
14
14
40ns
4
2
4
7
tCK
(AUTO Precharge)
26
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
CAPACITANCE (TA=25oC, f=1MHz )
Parameter
Pin
Symbol
Min
Max
Unit
Input Clock Capacitance
CK, CK
CCK
2.0
3.0
pF
Input Capacitance
All other input-only pins
CIN
2.0
3.0
pF
Input / Output Capacitanc
DQ, DQS, DM
CIO
4.0
5.0
pF
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
VTT
RT=50Ω
Output
Zo=50Ω
VREF
CL=30pF
Rev. 1.1 / Mar. 2008
27
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
PACKAGE INFORMATION
400mil 66pin Thin Small Outline Package
Unit : mm(Inch)
11.94 (0.470)
11.79 (0.462)
10.26 (0.404)
10.05 (0.396)
BASE PLANE
22.33 (0.879)
22.12 (0.871)
0.65 (0.0256) BSC
1.194 (0.0470)
0.991 (0.0390)
0.35 (0.0138)
0.25 (0.0098)
0 ~ 5 Deg.
SEATING PLANE
0.15 (0.0059)
0.05 (0.0020)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
Note : Package do not mold protrusion. Allowable protrusion of both sides is 0.4mm.
Rev. 1.1 / Mar. 2008
28