8 7 6 5 4 NOTES: E 1. Project Drawing Numbers: Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework 100-0320202-D1 110-0320202-D1 120-0320202-D1 130-0320202-D1 140-0320202-D1 150-0320202-D1 160-0320202-D1 170-0320202-D1 180-0320202-D1 210-0320202-D1 220-0320202-D1 320-0320202-D1 3 REV DATE PAGES D1 09/11/2012 22 D1.1 05/16/2013 12 2 1 DESCRIPTION REMOVE HSMC RESISTORS (AC CAP PLACEHOLDERS) R3-R18, R28-35. CHANGE MAX_RESETn TO 2.5V PULLUP, FROM 1.8V FOR LAYOUT IMPROVEMENT. DNI U22 E 2. 1148 Parts, 88 Library Parts, 1306 Nets, 6595 Pins Stratix V GX FPGA Development Kit Board D C B PAGE DESCRIPTION 1 Title, Notes, Block Diagram, Rev. History 30 Power 5 - Linear Regulator 2 FPGA Package Top 31 Power 6 - Power & Temp Monitor 3 PCI Express Edge Connector 32 Power 7 - Stratix V GX Power 4 Stratix V GX Bank 3 33 Power 8 - Stratix V GX GND 5 Stratix V GX Bank 4 34 Decoupling 6 Stratix V GX Bank 7 7 Stratix V GX Bank 8 8 Stratix V GX Transceiver Banks 9 Stratix V GX Clocks 10 PLL 11 Stratix V GX Configuration 12 JTAG 13 DDR3 - Part 1 of 2 14 DDR3 - Part 2 of 2 15 QDRII+ SRAM 16 RLDRAM II CIO 17 Flash 18 5M2210 System Controller 19 QSFP Interface 20 Display Port (x4) 21 SDI TX Cable Driver & SMB 22 HSMC Port A & Port B 23 Ethernet PHY & RJ-45 24 User I/O (LEDs, Buttons, Switches, LCD) 25 On-Board USB Blaster II 26 Power 1 - DC Input, 12V, 3.3V 27 Power 2 - 0.90V 28 Power 3 - 5V, 1.5V, 1.8V, 3.3V 29 Power 4 - 1.0V_GXB, 1.5V_FPGA A PAGE DESCRIPTION C B A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 D Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 1 of 1 34 D1.1 8 7 6 5 4 3 2 1 FPGA Package Top View BANK 8A BANK 7B VCCIO = 2.5V BANK 7A HSMA, QSFP CTL, DisplayPort CTL BANK 8B VCCIO = 1.5V VCCIO = 2.5V default/Variable BANK 8C BANK 7C HSMB, USER IO BANK 7D E DDR3, Embedded USB Blaster II BANK 8D E D D XCVR BANK QR3 XCVR BANK QR2 QSFP SDI HSMC Port B x2 (of 4 XCVRS) DisplayPort (x4) C C XCVR BANKS QR0, QR2 XCVR BANKS QR0, QR1 PCI Express x8 HSMC Port A x8 HSMC Port B x2 (of 4 XCVRS) B B BANK 4B VCCIO = 2.5V BANK 3A VCCIO = 2.5V HSMA, USER IO BANK 4A FLASH, USER IO VCCIO = 1.8V A BANK 3B CONFIG, ENET, USER IO Title BANK 4C QDRII+, FLASH VCCIO = 1.8V BANK 4D BANK 3C VCCIO = 1.8V BANK 3D RLDRAM II, FLASH Size B Date: 8 7 6 5 4 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 2 of 1 34 D1.1 8 7 6 5 4 3 2 1 PCI Express Edge Connector E E 12V_PCIE 12V_PCIE 3.3V_PCIE Link Width DIP Switch J18 D 11 11 PCIE_SMBCLK PCIE_SMBDAT 11 PCIE_WAKEn R128 R129 DNI 3.3V_PCIE_AUX DNI PCIE_WAKEn_R PCIE_PRSNT2n_x1 C 8 8 PCIE_RX_P1 PCIE_RX_N1 8 8 PCIE_RX_P2 PCIE_RX_N2 8 8 PCIE_RX_P3 PCIE_RX_N3 B 8 8 PCIE_RX_P4 PCIE_RX_N4 8 8 PCIE_RX_P5 PCIE_RX_N5 8 8 PCIE_RX_P6 PCIE_RX_N6 8 8 PCIE_RX_P7 PCIE_RX_N7 RSVD1 GND X1 GND REFCLK+ PET0P REFCLKPET0N GND GND PER0P PRSNT2_N_X1 PER0N GND GND B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 PCIE_PRSNT2n_x4 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 PCIE_PRSNT2n_x8 SW6 +12V PRSNT1_N +12V +12V +12V +12V GND GND SMCLK JTAG_TCK SMDAT JTAG_TDI GND JTAG_TDO +3_3V JTAG_TMS JTAG_TRSTN +3_3V +3_3VAUX +3_3V WAKE_N PERST_N KEY B12 B13 B14 B15 B16 B17 B18 PCIE_RX_P0 PCIE_RX_N0 8 8 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 PET1P X4 PET1N GND GND PET2P PET2N GND GND PET3P PET3N GND RSVD3 PRSNT2_N_X4 GND RSVD2 GND PER1P PER1N GND GND PER2P PER2N GND GND PER3P PER3N GND RSVD4 PET4P X8 PET4N GND GND PET5P PET5N GND GND PET6P PET6N GND GND PET7P PET7N GND PRSNT2_N_X8 GND RSVD5 GND PER4P PER4N GND GND PER5P PER5N GND GND PER6P PER6N GND GND PER7P PER7N GND A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 PCIE_PRSNT1n A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 PCIE_JTAG_TCK PCIE_JTAG_TDI PCIE_JTAG_TDO PCIE_JTAG_TMS 12 12 12 12 PCIE_PERSTn 11 PCIE_REFCLK_P PCIE_REFCLK_N 8 8 PCIE_TX_CP0 PCIE_TX_CN0 0.22uF 0.22uF C581 C580 PCIE_TX_P0 PCIE_TX_N0 PCIE_TX_CP1 PCIE_TX_CN1 0.22uF 0.22uF C579 C578 PCIE_TX_P1 PCIE_TX_N1 8 8 PCIE_TX_CP2 PCIE_TX_CN2 0.22uF 0.22uF C577 C576 PCIE_TX_P2 PCIE_TX_N2 8 8 PCIE_TX_CP3 PCIE_TX_CN3 0.22uF 0.22uF C575 C574 PCIE_TX_P3 PCIE_TX_N3 8 8 PCIE_TX_CP4 PCIE_TX_CN4 0.22uF 0.22uF C573 C572 PCIE_TX_P4 PCIE_TX_N4 8 8 PCIE_TX_CP5 PCIE_TX_CN5 0.22uF 0.22uF C571 C570 PCIE_TX_P5 PCIE_TX_N5 8 8 PCIE_TX_CP6 PCIE_TX_CN6 0.22uF 0.22uF C569 C568 PCIE_TX_P6 PCIE_TX_N6 8 8 PCIE_TX_CP7 PCIE_TX_CN7 0.22uF 0.22uF C567 C566 PCIE_TX_P7 PCIE_TX_N7 1 2 3 4 8 7 6 5 OPEN 3.3V_PCIE PCIE_PRSNT2n_x1 PCIE_PRSNT2n_x4 PCIE_PRSNT2n_x8 TDA04H0SB1 D 8 8 C A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 B 8 8 PCIE_Slot B5 12V_PCIE C74 0.1uF A 3.3V_PCIE C75 0.1uF C76 0.1uF C584 0.1uF C585 0.1uF C582 0.1uF C583 0.1uF C77 0.1uF PCI BRACKET Title Size B Date: 8 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 3 of 1 34 D1.1 8 7 6 5 4 3 2 Stratix V Bank 3 1 FLASH & MAX BUS INTERFACE FM_D[31:0] U15A Stratix V GX Bank 3 17,18 FM_A[26:0] 17,18,5,9 Bank 3A VCCIO = 2.5V RZQ_0/DQSN1B/DIFFIO_RX_B2N E AR34 ENET_RX_N See Stratix V GX Config sheet for ENET_RX_P LCD & USER I/O INTERFACES USER_LED_R[7:0] 24,9 Bank 3B HSMB_SDA HSMB_SCL HSMA_D1 HSMA_D0 PCIE_LED_X1 PCIE_LED_G2 PCIE_LED_X8 PCIE_LED_X4 AK30 AL30 AK29 AJ29 AL27 AL28 AM28 AN28 HSMA_SDA HSMA_SCL HSMA_D3 HSMA_D2 AL29 AM29 AP28 AR28 DQ11B/DIFFIO_TX_B31P DQ11B/DIFFIO_TX_B31N DQ11B/DIFFIO_TX_B33P DQ11B/DIFFIO_TX_B33N DQ12B/DIFFIO_TX_B35P DQ12B/DIFFIO_TX_B35N DQ12B/DIFFIO_RX_B36P DQ12B/DIFFIO_RX_B36N DQ13B/DIFFIO_TX_B37P DQ13B/DIFFIO_TX_B37N DQ13B/DIFFIO_TX_B39P DQ13B/DIFFIO_TX_B39N DQ14B/DIFFIO_TX_B41P DQ14B/DIFFIO_TX_B41N DQ14B/DIFFIO_RX_B42P DQ14B/DIFFIO_RX_B42N VCCIO = 2.5V DQS11B/DIFFIO_RX_B32P DQSN11B/DIFFIO_RX_B32N DQS12B/DIFFIO_RX_B34P DQSN12B/DIFFIO_RX_B34N 5SGXA7KF40 DQS13B/DIFFIO_RX_B38P DQSN13B/DIFFIO_RX_B38N DQS14B/DIFFIO_RX_B40P DQSN14B/DIFFIO_RX_B40N AA26 AA27 AB27 AC27 AG27 AH27 AJ27 AK27 ENET_MDC ENET_MDIO ENET_TX_P ENET_TX_N QSFP_MOD_SELn QSFP_MOD_PRSn SDI_TX_SD_HDn SDI_TX_EN AA28 AA29 AD27 AE27 ENET_RESETn ENET_INTn QSFP_LP_MODE QSFP_INTERRUPTn USER_LED_G3 ENET_RX_N ENET_INTn ENET_RESETn ENET_MDIO ENET_MDC ENET_TX_P ENET_TX_N HSMC INTERFACE C RLDC_DQ4 RLDC_DQ0 RLDC_QK_P0 RLDC_QK_N0 AV26 AW26 AP27 AR27 RLDC_DQ11 RLDC_DQ12 RLDC_DQ9 RLDC_DQ10 RLDC_DQ13 RLDC_DQ15 RLDC_DQ16 RLDC_DQ17 AD26 AE26 AC25 AC26 AF26 AG26 AG25 AH25 RLDC_DM RLDC_DQ14 RLDC_QK_P1 RLDC_QK_N1 AB25 AA25 AJ26 AK26 DQ15B/DIFFIO_TX_B43P DQ15B/DIFFIO_TX_B43N DQ15B/DIFFIO_TX_B45P DQ15B/DIFFIO_TX_B45N DQ16B/DIFFIO_TX_B47P DQ16B/DIFFIO_TX_B47N DQ16B/DIFFIO_RX_B48P DQ16B/DIFFIO_RX_B48N 22 HSMA_SDA HSMA_SCL Bank 3C AT27 AU27 AT26 AU26 AL26 AM26 AN26 AN27 23 23 23 23 23 23 23 HSMA_D[3:0] Version = 1.0 Pin-out Stratix V GX Bank 3 RLDC_DQ8 RLDC_DQ6 RLDC_DQ7 RLDC_DQ5 RLDC_QVLD RLDC_DQ3 RLDC_DQ2 RLDC_DQ1 24 ETHERNET INTERFACE U15B D DQ19B/DIFFIO_TX_B55P DQ19B/DIFFIO_TX_B55N DQ19B/DIFFIO_TX_B57P DQ19B/DIFFIO_TX_B57N DQ20B/DIFFIO_TX_B59P DQ20B/DIFFIO_TX_B59N DQ20B/DIFFIO_RX_B60P DQ20B/DIFFIO_RX_B60N VCCIO = 1.8V DQS15B/DIFFIO_RX_B44P DQSN15B/DIFFIO_RX_B44N DQS16B/DIFFIO_RX_B46P DQSN16B/DIFFIO_RX_B46N DQS19B/DIFFIO_RX_B56P DQSN19B/DIFFIO_RX_B56N DQS20B/DIFFIO_RX_B58P DQSN20B/DIFFIO_RX_B58N DQ17B/DIFFIO_TX_B49P DQ17B/DIFFIO_TX_B49N DQ17B/DIFFIO_TX_B51P DQ17B/DIFFIO_TX_B51N DQ18B/DIFFIO_TX_B53P DQ18B/DIFFIO_TX_B53N DQ18B/DIFFIO_RX_B54P DQ18B/DIFFIO_RX_B54N DQ21B/DIFFIO_TX_B61P DQ21B/DIFFIO_TX_B61N DQ21B/DIFFIO_TX_B63P DQ21B/DIFFIO_TX_B63N DQ22B/DIFFIO_TX_B65P DQ22B/DIFFIO_TX_B65N DQ22B/DIFFIO_RX_B66P DQ22B/DIFFIO_RX_B66N DQS17B/DIFFIO_RX_B50P DQSN17B/DIFFIO_RX_B50N DQS18B/DIFFIO_RX_B52P DQSN18B/DIFFIO_RX_B52N DQS21B/DIFFIO_RX_B62P DQSN21B/DIFFIO_RX_B62N DQS22B/DIFFIO_RX_B64P DQSN22B/DIFFIO_RX_B64N 22 22 HSMB_SDA HSMB_SCL B A AV23 AW23 AT23 AU23 AM22 AN22 AM23 AN23 RLDC_A22 RLDC_A1 RLDC_A16 RLDC_A18 AV22 AW22 AP22 AR22 RLDC_A3 RLDC_BA0 RLDC_A0 RLDC_A4 RLDC_BA1 RLDC_A13 AD23 AE23 AD22 AE22 AF22 AG22 RLDC_A14 RLDC_A8 AF23 AG23 DQ23B/DIFFIO_TX_B67P DQ23B/DIFFIO_TX_B67N DQ23B/DIFFIO_TX_B69P DQ23B/DIFFIO_TX_B69N DQ24B/DIFFIO_TX_B71P DQ24B/DIFFIO_TX_B71N DQ24B/DIFFIO_RX_B72P DQ24B/DIFFIO_RX_B72N DQ27B/DIFFIO_TX_B79P DQ27B/DIFFIO_TX_B79N DQ27B/DIFFIO_TX_B81P DQ27B/DIFFIO_TX_B81N DQ28B/DIFFIO_TX_B83P DQ28B/DIFFIO_TX_B83N DQ28B/DIFFIO_RX_B84P DQ28B/DIFFIO_RX_B84N VCCIO = 1.8V FM_D30 FM_D29 USER_LED_R3 FM_D31 FM_D14 FM_D13 FM_D16 FM_D15 PCIE_LED_G2 PCIE_LED_X1 PCIE_LED_X4 PCIE_LED_X8 AU24 AU25 AP25 AR25 USER_LED_G3 SDI INTERFACE RLDC_DK_P RLDC_DK_N SDI_TX_SD_HDn SDI_TX_EN AB24 AC24 AD24 AE24 AJ24 AK24 AL25 AL24 FM_D18 FM_D17 FM_D22 FM_D21 FM_D26 FM_D25 FM_D28 FM_D27 AE25 AF25 AH24 AG24 FM_D20 FM_D19 FM_D24 FM_D23 PCIE INTERFACE 24 24 24 24 DQS23B/DIFFIO_RX_B68P DQSN23B/DIFFIO_RX_B68N DQS24B/DIFFIO_RX_B70P DQSN24B/DIFFIO_RX_B70N DQS27B/DIFFIO_RX_B80P DQSN27B/DIFFIO_RX_B80N DQS28B/DIFFIO_RX_B82P DQSN28B/DIFFIO_RX_B82N DQ25B/DIFFIO_TX_B73P DQ25B/DIFFIO_TX_B73N DQ25B/DIFFIO_TX_B75P DQ25B/DIFFIO_TX_B75N DQ26B/DIFFIO_TX_B77P DQ26B/DIFFIO_TX_B77N DQ29B/DIFFIO_TX_B85P DQ29B/DIFFIO_TX_B85N DQ29B/DIFFIO_TX_B87P DQ29B/DIFFIO_TX_B87N DQ30B/DIFFIO_TX_B89P DQ30B/DIFFIO_TX_B89N DQ30B/DIFFIO_RX_B90P DQ30B/DIFFIO_RX_B90N DQS25B/DIFFIO_RX_B74P DQSN25B/DIFFIO_RX_B74N 5SGXA7KF40 DQS29B/DIFFIO_RX_B86P DQSN29B/DIFFIO_RX_B86N DQS30B/DIFFIO_RX_B88P DQSN30B/DIFFIO_RX_B88N RLDC_A12 RLDC_A11 RLDC_A7 RLDC_A20 RLDC_A19 RLDC_A10 FM_D0 FM_A25 AT21 AU21 AR20 AR21 RLDC_CK_P RLDC_CK_N RLDC_A17 RLDC_A15 AD20 AD21 AE20 AE21 AJ20 AJ21 AL20 AL21 FM_D2 FM_D1 FM_D6 FM_D5 FM_D10 FM_D9 FM_D12 FM_D11 AH21 AG21 AK21 AL22 FM_D4 FM_D3 FM_D8 FM_D7 RLDC_DQ[17:0] RLDC_QK_P[1:0] RLDC_QK_N[1:0] 6 RLDC_QK_P[1:0] 16 RLDC_A[22:0] 16 RLDC_BA[2:0] RLDC_BA[2:0] 16,9 RLDC_CK_P RLDC_CK_N 16 16 RLDC_DK_P RLDC_DK_N 16 16 RLDC_CSn RLDC_WEn RLDC_REFn RLDC_CSn RLDC_DM RLDC_QVLD 16,4 16 16 16,4 16 16 RLDC_CSn RLDC_WEn RLDC_REFn RLDC_CSn RLDC_DM RLDC_QVLD B QSFP INTERFACE QSFP_MOD_SELn QSFP_LP_MODE QSFP_INTERRUPTn QSFP_MOD_PRSn 19 19 19 19 QSFP_MOD_SELn QSFP_LP_MODE QSFP_INTERRUPTn QSFP_MOD_PRSn A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size 4 16 16 RLDC_DK_P RLDC_DK_N Version = 1.0 Pin-out 5 RLDC_DQ[17:0] RLDC_QK_N[1:0] Date: 7 C RLDC_A[22:0] B 8 21 18,21 RLDRAM II INTERFACE RLDC_CK_P RLDC_CK_N AV20 AW20 AT20 AU20 AN20 AM20 AN21 AP21 D 22 22 AV25 AW25 AR24 AT24 AM25 AN25 AN24 AP24 Bank 3D RLDC_A21 RLDC_A2 RLDC_A6 RLDC_A5 RLDC_REFn RLDC_WEn RLDC_A9 RLDC_CSn E 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 4 of 1 34 D1.1 8 7 6 5 4 3 2 1 Stratix V Bank 4 QDRII INTERFACE QDRII_A[20:0] 15 QDRII_D[17:0] E 15 U15D Stratix V GX Bank 4 QDRII_Q[17:0] Bank 4C QDRII_C_P QDRII_CQ_P QDRII_CQ_N QDRII_K_P QDRII_K_N QDRII_BWSn0 QDRII_BWSn1 15 15 15 15 15 15 15 QDRII_WPSn QDRII_RPSn QDRII_C_N QDRII_DOFFn 15 15 15 15 15 U15C Stratix V GX Bank 4 Bank 4A HSMA_RX_LED HSMA_PRSNTn HSMB_PRSNTn HSMA_TX_LED HSMB_TX_LED HSMB_RX_LED FLASH_WEn FLASH_CLK AV8 AW8 AU7 AU8 AP6 AR6 AN8 AM8 HSMA_TX_D_P7 HSMA_TX_D_N7 HSMA_TX_D_P4 HSMA_TX_D_N4 HSMA_TX_D_P3 HSMA_TX_D_N3 HSMA_RX_D_P3 HSMA_RX_D_N3 AB12 AC12 AE10 AE11 AG12 AF11 AL12 AK12 HSMA_RX_D_P6 HSMA_RX_D_N6 HSMA_RX_D_P4 HSMA_RX_D_N4 AD12 AE12 AH12 AJ12 HSMA_TX_D_P2 HSMA_TX_D_N2 HSMA_TX_D_P1 HSMA_TX_D_N1 HSMA_TX_D_P0 HSMA_TX_D_N0 HSMA_RX_D_P0 HSMA_RX_D_N0 AK11 AL11 AM11 AN11 AT11 AU11 AV11 AW11 DQ67B/DIFFIO_TX_B199P DQ67B/DIFFIO_TX_B199N DQ67B/DIFFIO_TX_B201P DQ67B/DIFFIO_TX_B201N DQ69B/DIFFIO_TX_B205P DQ69B/DIFFIO_TX_B205N DQ69B/DIFFIO_TX_B207P DQ69B/DIFFIO_TX_B207N VCCIO = 1.8V DQ70B/DIFFIO_RX_B210N DQ70B/DIFFIO_TX_B209P DQ70B/DIFFIO_TX_B209N RZQ_1/DQ70B/DIFFIO_RX_B210P AL6 AJ6 AJ7 AK6 FLASH_RDYBSYn0 FLASH_RESETn FLASH_OEn R199 100, 1% Bank 4B D C HSMA_RX_D_P2 HSMA_RX_D_N2 HSMA_RX_D_P1 HSMA_RX_D_N1 AR11 AR12 AT12 AU12 DQ59B/DIFFIO_TX_B175P DQ59B/DIFFIO_TX_B175N DQ59B/DIFFIO_TX_B177P DQ59B/DIFFIO_TX_B177N DQ60B/DIFFIO_TX_B179P DQ60B/DIFFIO_TX_B179N DQ60B/DIFFIO_RX_B180P DQ60B/DIFFIO_RX_B180N VCCIO = 2.5V DQS59B/DIFFIO_RX_B176P DQSN59B/DIFFIO_RX_B176N DQS60B/DIFFIO_RX_B178P DQSN60B/DIFFIO_RX_B178N DQ61B/DIFFIO_TX_B181P DQ61B/DIFFIO_TX_B181N DQ61B/DIFFIO_TX_B183P DQ61B/DIFFIO_TX_B183N DQ62B/DIFFIO_TX_B185P DQ62B/DIFFIO_TX_B185N DQ62B/DIFFIO_RX_B186P DQ62B/DIFFIO_RX_B186N DQS63B/DIFFIO_RX_B188P DQSN63B/DIFFIO_RX_B188N DQS64B/DIFFIO_RX_B190P DQSN64B/DIFFIO_RX_B190N DQ65B/DIFFIO_TX_B193P DQ65B/DIFFIO_TX_B193N DQ65B/DIFFIO_TX_B195P DQ65B/DIFFIO_TX_B195N DQ66B/DIFFIO_TX_B197P DQ66B/DIFFIO_TX_B197N DQ66B/DIFFIO_RX_B198P DQ66B/DIFFIO_RX_B198N DQS61B/DIFFIO_RX_B182P DQSN61B/DIFFIO_RX_B182N DQS62B/DIFFIO_RX_B184P DQSN62B/DIFFIO_RX_B184N 5SGXA7KF40 DQ63B/DIFFIO_TX_B187P DQ63B/DIFFIO_TX_B187N DQ63B/DIFFIO_TX_B189P DQ63B/DIFFIO_TX_B189N DQ64B/DIFFIO_TX_B191P DQ64B/DIFFIO_TX_B191N DQ64B/DIFFIO_RX_B192P DQ64B/DIFFIO_RX_B192N DQS65B/DIFFIO_RX_B194P DQSN65B/DIFFIO_RX_B194N DQS66B/DIFFIO_RX_B196P DQSN66B/DIFFIO_RX_B196N AB9 AC9 AD9 AE9 AG9 AH9 AH10 AJ10 HSMA_TX_D_P6 HSMA_TX_D_N6 HSMA_TX_D_P5 HSMA_TX_D_N5 HSMA_CLK_OUT_P1 HSMA_CLK_OUT_N1 LCD_D_Cn HSMA_CLK_OUT0 AB10 AC10 AF10 AG10 HSMA_RX_D_P7 HSMA_RX_D_N7 HSMA_RX_D_P5 HSMA_RX_D_N5 AL10 AM10 AN9 AP9 AR9 AT9 AU9 AU10 LCD_DATA3 LCD_DATA2 LCD_DATA5 LCD_DATA4 LCD_DATA7 LCD_DATA6 LCD_CSn SDI_CLK148_DN AN10 AP10 AV10 AW10 AB16 QDRII_D1 AB15 QDRII_D2 AA14 QDRII_D5 AA15 QDRII_D4 QDRII_BWSn0 AH15 QDRII_BWSn1 AJ15 AG15 QDRII_RPSn AG14 QDRII_D8 QDRII_D3 QDRII_D7 QDRII_D0 QDRII_D6 AC15 AD16 AD15 AE15 QDRII_WPSn QDRII_D9 QDRII_D10 QDRII_D12 QDRII_D15 QDRII_D16 QDRII_D13 QDRII_D17 AK15 AL15 AM14 AN14 AR14 AR15 AT15 AU15 QDRII_K_P QDRII_K_N QDRII_D11 QDRII_D14 AK14 AL14 AN15 AP15 DQ51B/DIFFIO_TX_B151P DQ51B/DIFFIO_TX_B151N DQ51B/DIFFIO_TX_B153P DQ51B/DIFFIO_TX_B153N DQ52B/DIFFIO_TX_B155P DQ52B/DIFFIO_TX_B155N DQ52B/DIFFIO_RX_B156P DQ52B/DIFFIO_RX_B156N DQ55B/DIFFIO_TX_B163P DQ55B/DIFFIO_TX_B163N DQ55B/DIFFIO_TX_B165P DQ55B/DIFFIO_TX_B165N DQ56B/DIFFIO_TX_B167P DQ56B/DIFFIO_TX_B167N DQ56B/DIFFIO_RX_B168P DQ56B/DIFFIO_RX_B168N VCCIO = 1.8V DQS51B/DIFFIO_RX_B152P DQSN51B/DIFFIO_RX_B152N DQS52B/DIFFIO_RX_B154P DQSN52B/DIFFIO_RX_B154N DQS55B/DIFFIO_RX_B164P DQSN55B/DIFFIO_RX_B164N DQS56B/DIFFIO_RX_B166P DQSN56B/DIFFIO_RX_B166N DQ53B/DIFFIO_TX_B157P DQ53B/DIFFIO_TX_B157N DQ53B/DIFFIO_TX_B159P DQ53B/DIFFIO_TX_B159N DQ54B/DIFFIO_TX_B161P DQ54B/DIFFIO_TX_B161N DQ54B/DIFFIO_RX_B162P DQ54B/DIFFIO_RX_B162N DQ57B/DIFFIO_TX_B169P DQ57B/DIFFIO_TX_B169N DQ57B/DIFFIO_TX_B171P DQ57B/DIFFIO_TX_B171N DQ58B/DIFFIO_TX_B173P DQ58B/DIFFIO_TX_B173N DQ58B/DIFFIO_RX_B174P DQ58B/DIFFIO_RX_B174N DQS53B/DIFFIO_RX_B158P DQSN53B/DIFFIO_RX_B158N DQS54B/DIFFIO_RX_B160P DQSN54B/DIFFIO_RX_B160N DQS57B/DIFFIO_RX_B170P DQSN57B/DIFFIO_RX_B170N DQS58B/DIFFIO_RX_B172P DQSN58B/DIFFIO_RX_B172N AB13 AC13 AA12 AA13 AH13 AJ13 AF13 AG13 QDRII_A13 QDRII_A14 QDRII_A18 QDRII_A20 QDRII_A7 QDRII_A8 QDRII_A2 QDRII_A4 AC14 AD14 AE14 AF14 QDRII_A9 QDRII_A6 QDRII_A10 QDRII_A15 AL13 AM13 AN13 AP13 AV14 AW14 AV13 AW13 QDRII_A16 QDRII_A11 QDRII_A5 QDRII_A1 FLASH_CEn0 QDRII_A12 QDRII_DOFFn FLASH_CEn1 AN12 AP12 AT14 AU14 QDRII_A17 QDRII_A19 QDRII_A3 QDRII_A0 FLASH INTERFACE FM_A[26:0] 17,18,4,9 FLASH_OEn FLASH_CLK FLASH_WEn FLASH_RDYBSYn0 FLASH_RESETn FLASH_CEn0 FLASH_CEn1 LCD_DATA1 LCD_DATA0 USER_LED_G7 LCD_WEn Version = 1.0 Pin-out AG19 AH19 AH18 AJ18 AE18 AE19 AD18 AD17 QDRII_Q9 QDRII_Q10 QDRII_CQ_N QDRII_Q4 AJ19 AK18 AF19 AG18 QDRII_Q11 QDRII_Q17 QDRII_Q13 QDRII_Q14 QDRII+ QVLD = QDRII C_PQDRII_C_P QDRII+ ODT = QDRII C_N QDRII_C_N FM_A1 FM_A0 B QDRII_CQ_P QDRII_Q16 QDRII_Q15 QDRII_Q12 AL18 AM19 AP18 AR18 AT18 AU18 AV19 AW19 AN19 AN18 AP19 AR19 DQ43B/DIFFIO_TX_B127P DQ43B/DIFFIO_TX_B127N DQ43B/DIFFIO_TX_B129P DQ43B/DIFFIO_TX_B129N DQ44B/DIFFIO_TX_B131P DQ44B/DIFFIO_TX_B131N DQ44B/DIFFIO_RX_B132P DQ44B/DIFFIO_RX_B132N DQ47B/DIFFIO_TX_B141P DQ47B/DIFFIO_TX_B141N VCCIO = 1.8V DQ48B/DIFFIO_TX_B143P DQ48B/DIFFIO_TX_B143N AL16 AM16 FM_A3 FM_A2 AF16 AG16 FM_A4 FM_A5 LCD & USER I/O INTERFACES 24 24 24 USER_LED_G[7:0] 11,24,4,6,9 C HSMC INTERFACE DQS43B/DIFFIO_RX_B128P DQSN43B/DIFFIO_RX_B128N DQS44B/DIFFIO_RX_B130P DQSN44B/DIFFIO_RX_B130N DQS45B/DIFFIO_RX_B134P DQSN45B/DIFFIO_RX_B134N DQS46B/DIFFIO_RX_B136P DQSN46B/DIFFIO_RX_B136N 24 LCD_CSn LCD_D_Cn LCD_WEn HSMB_TX_LED HSMA_CLK_OUT0 24 22 HSMA_TX_LED HSMA_RX_LED 24 24 HSMA_PRSNTn DQ45B/DIFFIO_TX_B133P DQ45B/DIFFIO_TX_B133N DQ45B/DIFFIO_TX_B135P DQ45B/DIFFIO_TX_B135N DQ46B/DIFFIO_TX_B137P DQ46B/DIFFIO_TX_B137N DQ46B/DIFFIO_RX_B138P DQ46B/DIFFIO_RX_B138N DQ49B/DIFFIO_TX_B145P DQ49B/DIFFIO_TX_B145N DQ49B/DIFFIO_TX_B147P DQ49B/DIFFIO_TX_B147N DQ50B/DIFFIO_TX_B149P DQ50B/DIFFIO_TX_B149N DQ50B/DIFFIO_RX_B150P DQ50B/DIFFIO_RX_B150N DQS49B/DIFFIO_RX_B146P DQSN49B/DIFFIO_RX_B146N DQS50B/DIFFIO_RX_B148P DQSN50B/DIFFIO_RX_B148N AM17 AN17 AR17 AT17 AV16 AW16 AV17 AW17 FM_A7 FM_A6 FM_A11 FM_A10 FM_A15 FM_A14 FM_A17 FM_A16 AN16 AP16 AU17 AU16 FM_A9 FM_A8 FM_A13 FM_A12 18,22,24 HSMB_PRSNTn 18,22,24 HSMB_RX_LED 24 HSMA_CLK_OUT_P[2:1] 22,6 HSMA_CLK_OUT_N[2:1] Version = 1.0 Pin-out B 22,6 HSMA_TX_D_P[16:0] 22,6 HSMA_TX_D_N[16:0] 5SGXA7KF40 D 17,18 17,18 17,18 17,18 17,18 17,18 17,18 LCD_DATA[7:0] Bank 4D QDRII_Q5 QDRII_Q8 QDRII_Q6 QDRII_Q7 QDRII_Q1 QDRII_Q3 QDRII_Q2 QDRII_Q0 E 22,6 HSMA_RX_D_P[16:0] 22,6 HSMA_RX_D_N[16:0] 22,6 Si571 VCXO SDI_CLK148_DN A 10 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 5 of 1 34 D1.1 8 7 6 5 4 3 2 1 Stratix V Bank 7 U15F FLASH INTERFACES Stratix V GX Bank 7 U15E Stratix V GX Bank 7 Bank 7A H7 J7 K7 M6 N6 P7 N7 USER_DIPSW1 USER_DIPSW2 USER_DIPSW3 USER_DIPSW4 USER_DIPSW5 USER_DIPSW6 USER_DIPSW7 DQ1T/DIFFIO_RX_T1N DQ1T/DIFFIO_TX_T2P DQ1T/DIFFIO_TX_T2N DQ2T/DIFFIO_TX_T4P DQ2T/DIFFIO_TX_T4N DQ2T/DIFFIO_TX_T6P DQ2T/DIFFIO_TX_T6N VCCIO = HSMB VARIABLE DQ4T/DIFFIO_TX_T10P 1.2V/1.5V/1.8V/2.5V DQ4T/DIFFIO_TX_T10N DQ4T/DIFFIO_TX_T12P DQ4T/DIFFIO_TX_T12N RZQ_4/DQ1T/DIFFIO_RX_T1P E6 D6 F6 E7 J6 USER_DIPSW0 R197 100, 1% Bank 7B D HSMA_RX_D_P13 HSMA_RX_D_N13 HSMA_CLK_OUT_P2 HSMA_CLK_OUT_N2 HSMA_TX_D_P16 HSMA_TX_D_N16 HSMA_TX_D_P13 HSMA_TX_D_N13 HSMA_RX_D_P12 HSMA_RX_D_N12 HSMA_RX_D_P15 HSMA_RX_D_N15 C FM_A[26:0] Bank 7C E F8 E8 G9 G8 A8 B8 E9 D9 G10 F9 C8 C9 HSMA_RX_D_P10 HSMA_RX_D_N10 HSMA_TX_D_P11 HSMA_TX_D_N11 HSMA_TX_D_P10 HSMA_TX_D_N10 HSMA_TX_D_P8 HSMA_TX_D_N8 M8 L8 K9 J9 N8 N9 R8 P8 HSMA_RX_D_P9 HSMA_RX_D_N9 HSMA_RX_D_P8 HSMA_RX_D_N8 M9 L9 T9 R9 DQ5T/DIFFIO_RX_T13P DQ5T/DIFFIO_RX_T13N DQ5T/DIFFIO_TX_T14P DQ5T/DIFFIO_TX_T14N DQ6T/DIFFIO_TX_T16P DQ6T/DIFFIO_TX_T16N DQ6T/DIFFIO_TX_T18P DQ6T/DIFFIO_TX_T18N VCCIO = 2.5V DQS5T/DIFFIO_RX_T15P DQSN5T/DIFFIO_RX_T15N DQS6T/DIFFIO_RX_T17P DQSN6T/DIFFIO_RX_T17N DQS9T/DIFFIO_RX_T27P DQSN9T/DIFFIO_RX_T27N DQS10T/DIFFIO_RX_T29P DQSN10T/DIFFIO_RX_T29N DQ7T/DIFFIO_RX_T19P DQ7T/DIFFIO_RX_T19N DQ7T/DIFFIO_TX_T20P DQ7T/DIFFIO_TX_T20N DQ8T/DIFFIO_TX_T22P DQ8T/DIFFIO_TX_T22N DQ8T/DIFFIO_TX_T24P DQ8T/DIFFIO_TX_T24N DQ11T/DIFFIO_RX_T31P DQ11T/DIFFIO_RX_T31N DQ11T/DIFFIO_TX_T32P DQ11T/DIFFIO_TX_T32N DQ12T/DIFFIO_TX_T34P DQ12T/DIFFIO_TX_T34N DQ12T/DIFFIO_TX_T36P DQ12T/DIFFIO_TX_T36N DQS7T/DIFFIO_RX_T21P DQSN7T/DIFFIO_RX_T21N DQS8T/DIFFIO_RX_T23P DQSN8T/DIFFIO_RX_T23N 5SGXA7KF40 DQ9T/DIFFIO_RX_T25P DQ9T/DIFFIO_RX_T25N DQ9T/DIFFIO_TX_T26P DQ9T/DIFFIO_TX_T26N DQ10T/DIFFIO_TX_T28P DQ10T/DIFFIO_TX_T28N DQ10T/DIFFIO_TX_T30P DQ10T/DIFFIO_TX_T30N DQS11T/DIFFIO_RX_T33P DQSN11T/DIFFIO_RX_T33N DQS12T/DIFFIO_RX_T35P DQSN12T/DIFFIO_RX_T35N H11 G11 J10 H10 D10 C10 B11 A11 HSMA_RX_D_P11 HSMA_RX_D_N11 HSMA_TX_D_P12 HSMA_TX_D_N12 HSMA_TX_D_P14 HSMA_TX_D_N14 HSMA_TX_D_P15 HSMA_TX_D_N15 F11 E11 B10 A10 HSMA_RX_D_P14 HSMA_RX_D_N14 HSMA_RX_D_P16 HSMA_RX_D_N16 B13 A13 D12 C12 G12 G13 J13 H13 HSMB_DQS_P1 HSMB_DQS_N1 HSMB_DQ10 HSMB_DQ11 D13 C13 F12 E12 DQ13T/DIFFIO_RX_T37P DQ17T/DIFFIO_RX_T49P DQ13T/DIFFIO_RX_T37NVCCIO = HSMB VARIABLEDQ17T/DIFFIO_RX_T49N DQ13T/DIFFIO_TX_T38P 1.2V/1.5V/1.8V/2.5V DQ17T/DIFFIO_TX_T50P DQ13T/DIFFIO_TX_T38N DQ17T/DIFFIO_TX_T50N DQ14T/DIFFIO_TX_T40P DQ18T/DIFFIO_TX_T52P DQ14T/DIFFIO_TX_T40N DQ18T/DIFFIO_TX_T52N DQ14T/DIFFIO_TX_T42P DQ18T/DIFFIO_TX_T54P DQ14T/DIFFIO_TX_T42N DQ18T/DIFFIO_TX_T54N DQS13T/DIFFIO_RX_T39P DQSN13T/DIFFIO_RX_T39N DQS14T/DIFFIO_RX_T41P DQSN14T/DIFFIO_RX_T41N DQS17T/DIFFIO_RX_T51P DQSN17T/DIFFIO_RX_T51N DQS18T/DIFFIO_RX_T53P DQSN18T/DIFFIO_RX_T53N C14 C15 B14 A14 F14 E14 H14 G14 HSMB_DQ30 HSMB_DQ31 HSMB_DQ28 HSMB_DQ29 HSMB_DQ25 HSMB_DQ27 HSMB_DM3 HSMB_A3 E15 D15 G15 F15 HSMB_DQS_P3 HSMB_DQS_N3 HSMB_DQ24 HSMB_DQ26 17,18,4,5,9 HSMB_DQ4 HSMB_DQ5 HSMB_DQ6 HSMB_DQ7 HSMB_DQ3 HSMB_DQ2 HSMB_DQ1 HSMB_RASn M12 L12 K12 J12 N13 N12 R12 P13 HSMB_DQS_P0 HSMB_DQS_N0 HSMB_DM0 HSMB_DQ0 L13 K13 U11 T12 HSMB_A9 HSMB_A8 HSMB_CLK_OUT_P2 HSMB_CLK_OUT_N2 B17 A17 B16 A16 F17 E17 H17 G17 DP_RETURN DP_HOT_PLUG DP_AUX_P DP_AUX_N HSMB_CLK_OUT_P1 D16 HSMB_CLK_OUT_N1 C16 H16 G16 Version = 1.0 Pin-out T15 R15 HSMB_C_P DDR ODT HSMB_C_N N15 M15 DQ15T/DIFFIO_RX_T43P DQ15T/DIFFIO_RX_T43N DQ15T/DIFFIO_TX_T44P DQ15T/DIFFIO_TX_T44N DQ16T/DIFFIO_TX_T46P DQ16T/DIFFIO_TX_T46N DQ16T/DIFFIO_TX_T48P DQ16T/DIFFIO_TX_T48N DQ19T/DIFFIO_RX_T55P DQ19T/DIFFIO_RX_T55N DQ19T/DIFFIO_TX_T56P DQ19T/DIFFIO_TX_T56N DQ20T/DIFFIO_TX_T58P DQ20T/DIFFIO_TX_T58N DQ20T/DIFFIO_TX_T60P DQ20T/DIFFIO_TX_T60N USER_DIPSW[7:0] 24 USER_LED_R[7:0] 24,4,9 USER_LED_G[7:0] 11,24,4,5,9 HSMC INTERFACE HSMA_TX_D_P[16:0] 22,5 HSMA_TX_D_N[16:0] DQS15T/DIFFIO_RX_T45P DQSN15T/DIFFIO_RX_T45N DQS16T/DIFFIO_RX_T47P DQSN16T/DIFFIO_RX_T47N DQS19T/DIFFIO_RX_T57P DQSN19T/DIFFIO_RX_T57N DQS20T/DIFFIO_RX_T59P DQSN20T/DIFFIO_RX_T59N Bank 7D DQ21T/DIFFIO_RX_T61P DQ25T/DIFFIO_RX_T73P DQ21T/DIFFIO_RX_T61N DQ25T/DIFFIO_RX_T73N VCCIO = HSMB VARIABLE DQ21T/DIFFIO_TX_T62P DQ25T/DIFFIO_TX_T74P DQ21T/DIFFIO_TX_T62N 1.2V/1.5V/1.8V/2.5V DQ25T/DIFFIO_TX_T74N DQ22T/DIFFIO_TX_T64P DQ26T/DIFFIO_TX_T76P DQ22T/DIFFIO_TX_T64N DQ26T/DIFFIO_TX_T76N DQ22T/DIFFIO_TX_T66P DQ26T/DIFFIO_TX_T78P DQ22T/DIFFIO_TX_T66N DQ26T/DIFFIO_TX_T78N DQS21T/DIFFIO_RX_T63P DQSN21T/DIFFIO_RX_T63N DQS22T/DIFFIO_RX_T65P DQSN22T/DIFFIO_RX_T65N DQS25T/DIFFIO_RX_T75P DQSN25T/DIFFIO_RX_T75N DQS26T/DIFFIO_RX_T77P DQSN26T/DIFFIO_RX_T77N DQ23T/DIFFIO_TX_T68P DQ23T/DIFFIO_TX_T68N DQ27T/DIFFIO_RX_T79P DQ27T/DIFFIO_RX_T79N DQ27T/DIFFIO_TX_T80P DQ27T/DIFFIO_TX_T80N DQ28T/DIFFIO_TX_T82P DQ28T/DIFFIO_TX_T82N DQ28T/DIFFIO_TX_T84P DQ28T/DIFFIO_TX_T84N DQ24T/DIFFIO_TX_T70P DQ24T/DIFFIO_TX_T70N DQS27T/DIFFIO_RX_T81P DQSN27T/DIFFIO_RX_T81N DQS28T/DIFFIO_RX_T83P DQSN28T/DIFFIO_RX_T83N B 5SGXA7KF40 U13 U12 T13 U14 N14 M14 L15 K15 HSMB_DQ16 HSMB_DM2 HSMB_DQ17 HSMB_DQ20 HSMB_DQ18 HSMB_DQ19 HSMB_DQ21 R14 P14 J14 J15 HSMB_DQS_P2 HSMB_DQS_N2 HSMB_DQ22 HSMB_DQ23 B19 A19 D18 C18 E18 E19 H19 G19 HSMB_A14 HSMB_A13 HSMB_A12 HSMB_A11 HSMB_BA0 HSMB_BA3 HSMB_CSn HSMB_CKE D19 C19 G18 F18 HSMB_BA1 HSMB_A15 HSMB_A10 HSMB_BA2 N17 M17 R16 P17 M18 L18 K19 L19 HSMB_A0 HSMB_WEn HSMB_CASn HSMB_A1 HSMB_ADDR_CMD0 HSMB_A4 HSMB_A6 HSMB_A5 N18 N19 K18 J18 HSMB_A7 E USER I/O INTERFACES 22,5 HSMA_RX_D_P[16:0] K10 DP_DIRECTION J11 USER_LED_G0 P10 HSMA_TX_D_P9 N10 HSMA_TX_D_N9 T10 DP_AUX_TX_P R10 DP_AUX_TX_N U10 USER_LED_G1 U9 USER_LED_G2 M11 L11 R11 P11 HSMB_DQ14 HSMB_DQ15 HSMB_DQ12 HSMB_DQ13 HSMB_DQ8 HSMB_DQ9 HSMB_DM1 HSMB_A2 22,5 HSMA_RX_D_N[16:0] 22,5 D HSMA_CLK_OUT_P[2:1] 22,5 HSMA_CLK_OUT_N[2:1] 22,5 HSMB INTERFACE HSMB_A[15:0] 22 HSMB_BA[3:0] 22 HSMB_DM[3:0] 22 HSMB_DQ[31:0] 22 HSMB_DQS_P[3:0] 22 HSMB_DQS_N[3:0] 22 C HSMB_CLK_IN_P[2:1] 22,9 HSMB_CLK_IN_N[2:1] 22,9 HSMB_CLK_OUT_P[2:1] 22 HSMB_CLK_OUT_N[2:1] 22 HSMB_WEn HSMB_CSn HSMB_CKE HSMB_CASn HSMB_RASn HSMB_CLK_IN0 HSMB_CLK_OUT0 HSMB_C_P HSMB_C_N HSMB_ADDR_CMD0 22 22 22 22 22 22,9 22,9 22 22 22 B Version = 1.0 Pin-out DISPLAYPORT INTERFACE DP_HOT_PLUG DP_DIRECTION DP_RETURN DP_AUX_P DP_AUX_N DP_AUX_TX_P DP_AUX_TX_N A DP_HOT_PLUG DP_DIRECTION DP_RETURN DP_AUX_P DP_AUX_N DP_AUX_TX_P DP_AUX_TX_N 20 20 20 20 20 20 20 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 6 of 1 34 D1.1 8 7 6 5 4 3 2 1 Stratix V Bank 8 DDR3 x72 INTERFACE E E U15H DDR3_DQ[71:0] Stratix V GX Bank 8 U15G Stratix V GX Bank 8 Bank 8A MAX5_BEn0 MAX5_BEn1 U31 T31 MAX5_BEn2 MAX5_BEn3 N33 M33 DQ65T/DIFFIO_TX_T194P DQ65T/DIFFIO_TX_T194N VCCIO = 1.5V DQ66T/DIFFIO_TX_T196P DQ66T/DIFFIO_TX_T196N DQ68T/DIFFIO_TX_T202P DQ68T/DIFFIO_TX_T202N DQ68T/DIFFIO_TX_T204P DQ68T/DIFFIO_TX_T204N DQ69T/DIFFIO_RX_T205P DQ69T/DIFFIO_RX_T205N DQ69T/DIFFIO_TX_T206P DQ69T/DIFFIO_TX_T206N DQS68T/DIFFIO_RX_T203P DQS69T/DIFFIO_RX_T207P DQSN69T/DIFFIO_RX_T207N D RZQ_5/DQSN68T/DIFFIO_RX_T203N MAX5_CSn MAX5_OEn B32 A32 DQ67T/DIFFIO_TX_T200P DQ67T/DIFFIO_TX_T200N DQ70T/DIFFIO_TX_T208P DQ70T/DIFFIO_TX_T208N DQ70T/DIFFIO_TX_T210P DQ70T/DIFFIO_TX_T210N DQS70T/DIFFIO_RX_T209P DQSN70T/DIFFIO_RX_T209N A34 A35 A36 A37 E32 F32 G33 G32 MAX5_WEn USB_DATA0 USB_DATA2 USB_DATA3 USB_DATA4 USB_DATA5 USB_DATA6 USB_DATA7 C34 USB_DATA1 F33 E33 USB_SDA USB_OEn B34 100, 1% R297 K33 J33 K34 J34 USB_RDn USB_WRn USB_ADDR1 USB_SCL H34 G34 USB_RESETn USB_ADDR0 Bank 8B C B DDR3_DQ13 DDR3_DQ15 DDR3_DQ11 DDR3_DQ12 DDR3_DQ14 DDR3_DQ9 DDR3_DQ10 DDR3_DQ8 V29 U29 R29 P29 N28 M29 L28 K28 DDR3_DQS_P1 DDR3_DQS_N1 DDR3_A9 DDR3_DM1 U30 T30 J29 J28 DDR3_DQ3 DDR3_DQ1 DDR3_DQ5 DDR3_DQ7 DDR3_DQ4 DDR3_DQ6 DDR3_DQ2 DDR3_DM0 F29 E28 H28 G28 D28 C28 B29 A29 DDR3_DQS_P0 DDR3_DQS_N0 DDR3_CASn DDR3_DQ0 H29 G29 B28 A28 DQ57T/DIFFIO_RX_T169P DQ57T/DIFFIO_RX_T169N DQ57T/DIFFIO_TX_T170P DQ57T/DIFFIO_TX_T170N DQ58T/DIFFIO_TX_T172P DQ58T/DIFFIO_TX_T172N DQ58T/DIFFIO_TX_T174P DQ58T/DIFFIO_TX_T174N VCCIO = 1.5V DQS57T/DIFFIO_RX_T171P DQSN57T/DIFFIO_RX_T171N DQS58T/DIFFIO_RX_T173P DQSN58T/DIFFIO_RX_T173N DQ61T/DIFFIO_RX_T181P DQ61T/DIFFIO_RX_T181N DQ61T/DIFFIO_TX_T182P DQ61T/DIFFIO_TX_T182N DQ62T/DIFFIO_TX_T184P DQ62T/DIFFIO_TX_T184N DQ62T/DIFFIO_TX_T186P DQ62T/DIFFIO_TX_T186N DQS61T/DIFFIO_RX_T183P DQSN61T/DIFFIO_RX_T183N DQS62T/DIFFIO_RX_T185P DQSN62T/DIFFIO_RX_T185N DQ59T/DIFFIO_RX_T175P DQ59T/DIFFIO_RX_T175N DQ59T/DIFFIO_TX_T176P DQ59T/DIFFIO_TX_T176N DQ60T/DIFFIO_TX_T178P DQ60T/DIFFIO_TX_T178N DQ60T/DIFFIO_TX_T180P DQ60T/DIFFIO_TX_T180N DQ63T/DIFFIO_RX_T187P DQ63T/DIFFIO_RX_T187N DQ63T/DIFFIO_TX_T188P DQ63T/DIFFIO_TX_T188N DQ64T/DIFFIO_TX_T190P DQ64T/DIFFIO_TX_T190N DQ64T/DIFFIO_TX_T192P DQ64T/DIFFIO_TX_T192N DQS59T/DIFFIO_RX_T177P DQSN59T/DIFFIO_RX_T177N DQS60T/DIFFIO_RX_T179P DQSN60T/DIFFIO_RX_T179N DQS63T/DIFFIO_RX_T189P DQSN63T/DIFFIO_RX_T189N DQS64T/DIFFIO_RX_T191P DQSN64T/DIFFIO_RX_T191N N30 M30 R30 R31 L31 L30 K31 J31 DDR3_CLK_P DDR3_CLK_N DDR3_A12 DDR3_CKE DDR3_A11 DDR3_A4 DDR3_A1 DDR3_A13 P31 N31 K30 J30 DDR3_A8 DDR3_A6 DDR3_BA1 DDR3_A10 P25 N25 U25 T25 P26 N26 K25 J25 DDR3_DQS_P5 DDR3_DQS_N5 DDR3_DQ42 R25 R26 M26 L26 DDR3_DQ35 DDR3_DQ33 DDR3_DQ37 DDR3_DQ39 DDR3_DQ36 DDR3_DQ38 DDR3_DQ32 DDR3_DM4 G24 F24 H25 G25 D24 C24 B25 A25 DDR3_DQS_P4 DDR3_DQS_N4 DDR3_DQ34 E24 E25 D25 C25 DDR3_DQ69 DDR3_DQ67 DDR3_DQ64 DDR3_DQ65 DDR3_DM8 DDR3_DQ71 DDR3_DQ70 DDR3_DQ68 K21 J21 M20 L20 M21 L21 N20 N21 DDR3_DQS_P8 DDR3_DQS_N8 K22 J22 P22 N22 DQ49T/DIFFIO_RX_T145P DQ49T/DIFFIO_RX_T145N DQ49T/DIFFIO_TX_T146P DQ49T/DIFFIO_TX_T146N DQ50T/DIFFIO_TX_T148P DQ50T/DIFFIO_TX_T148N DQ50T/DIFFIO_TX_T150P DQ50T/DIFFIO_TX_T150N VCCIO = 1.5V DQS49T/DIFFIO_RX_T147P DQSN49T/DIFFIO_RX_T147N DQS50T/DIFFIO_RX_T149P DQSN50T/DIFFIO_RX_T149N DQ53T/DIFFIO_RX_T157P DQ53T/DIFFIO_RX_T157N DQ53T/DIFFIO_TX_T158P DQ53T/DIFFIO_TX_T158N DQ54T/DIFFIO_TX_T160P DQ54T/DIFFIO_TX_T160N DQ54T/DIFFIO_TX_T162P DQ54T/DIFFIO_TX_T162N DQS53T/DIFFIO_RX_T159P DQSN53T/DIFFIO_RX_T159N DQS54T/DIFFIO_RX_T161P DQSN54T/DIFFIO_RX_T161N DQ51T/DIFFIO_RX_T151P DQ51T/DIFFIO_RX_T151N DQ51T/DIFFIO_TX_T152P DQ51T/DIFFIO_TX_T152N DQ52T/DIFFIO_TX_T154P DQ52T/DIFFIO_TX_T154N DQ52T/DIFFIO_TX_T156P DQ52T/DIFFIO_TX_T156N DQ55T/DIFFIO_RX_T163P DQ55T/DIFFIO_RX_T163N DQ55T/DIFFIO_TX_T164P DQ55T/DIFFIO_TX_T164N DQ56T/DIFFIO_TX_T166P DQ56T/DIFFIO_TX_T166N DQ56T/DIFFIO_TX_T168P DQ56T/DIFFIO_TX_T168N DQS51T/DIFFIO_RX_T153P DQSN51T/DIFFIO_RX_T153N DQS52T/DIFFIO_RX_T155P DQSN52T/DIFFIO_RX_T155N DQS55T/DIFFIO_RX_T165P DQSN55T/DIFFIO_RX_T165N DQS56T/DIFFIO_RX_T167P DQSN56T/DIFFIO_RX_T167N U26 U27 T27 R27 N27 P28 M27 L27 DDR3_DQ28 DDR3_DQ30 DDR3_DQ26 DDR3_DQ31 DDR3_DQ25 DDR3_DQ29 DDR3_DQ27 DDR3_DM3 13,14 DDR3_DQS_N[8:0] 13,14 DDR3_DM[8:0] 13,14 DDR3_BA[2:0] U28 DDR3_DQS_P3 T28 DDR3_DQS_N3 K27 J27 DDR3_DQ24 G26 F26 J26 H26 E27 D27 C26 C27 13,14 DDR3_DQS_P[8:0] DDR3_DQ16 DDR3_DQ18 DDR3_DQ21 DDR3_DQ23 DDR3_DQ22 DDR3_DQ17 DDR3_DQ20 DDR3_DQ19 13,14 DDR3_CSn DDR3_CASn DDR3_CKE DDR3_WEn DDR3_RASn 13,14 13,14 13,14 13,14 13,14 D DDR3_CLK_P DDR3_CLK_N DDR3_ODT 13,14 13,14 13,14 DDR3_RESETn 13,14 MAX V CONTROL G27 DDR3_DQS_P2 F27 DDR3_DQS_N2 B26 DDR3_RASn A26 DDR3_DM2 MAX5_BEn[3:0] 18 MAX5_OEn MAX5_CSn MAX5_WEn 18 18 18 Bank 8D B31 DDR3_CSn A31 DDR3_ODT D30 C30 DDR3_WEn G30 DDR3_RESETn F30 DDR3_A7 H31 DDR3_A2 G31 DDR3_A0 D31 C31 E30 E31 DDR3_DQ44 DDR3_DQ46 DDR3_DQ47 DDR3_DQ45 DDR3_DQ43 DDR3_DQ41 DDR3_DM5 DDR3_DQ40 13,14 DDR3_A[13:0] Bank 8C DDR3_DQ66 DDR3_A3 DDR3_BA0 DDR3_BA2 DDR3_A5 DDR3_DQ58 DDR3_DQ63 DDR3_DQ60 DDR3_DQ62 DDR3_DQ57 DDR3_DQ59 DDR3_DM7 DDR3_DQ56 F20 E20 H20 G20 C20 C21 B20 A20 DDR3_DQS_P7 DDR3_DQS_N7 G21 F21 E21 D21 DDR3_DQ61 5SGXA7KF40 DQ41T/DIFFIO_RX_T121P DQ41T/DIFFIO_RX_T121N DQ41T/DIFFIO_TX_T122P DQ41T/DIFFIO_TX_T122N DQ42T/DIFFIO_TX_T124P DQ42T/DIFFIO_TX_T124N DQ42T/DIFFIO_TX_T126P DQ42T/DIFFIO_TX_T126N VCCIO = 1.5V DQS41T/DIFFIO_RX_T123P DQSN41T/DIFFIO_RX_T123N DQS42T/DIFFIO_RX_T125P DQSN42T/DIFFIO_RX_T125N DQ43T/DIFFIO_RX_T127P DQ43T/DIFFIO_RX_T127N DQ43T/DIFFIO_TX_T128P DQ43T/DIFFIO_TX_T128N DQ44T/DIFFIO_TX_T130P DQ44T/DIFFIO_TX_T130N DQ44T/DIFFIO_TX_T132P DQ44T/DIFFIO_TX_T132N DQS43T/DIFFIO_RX_T129P DQSN43T/DIFFIO_RX_T129N DQS44T/DIFFIO_RX_T131P DQSN44T/DIFFIO_RX_T131N DQ45T/DIFFIO_TX_T134P DQ45T/DIFFIO_TX_T134N DQ46T/DIFFIO_TX_T136P DQ46T/DIFFIO_TX_T136N DQ46T/DIFFIO_TX_T138P DQ46T/DIFFIO_TX_T138N DQS46T/DIFFIO_RX_T137P DQSN46T/DIFFIO_RX_T137N DQ47T/DIFFIO_RX_T139P DQ47T/DIFFIO_RX_T139N DQ47T/DIFFIO_TX_T140P DQ47T/DIFFIO_TX_T140N DQ48T/DIFFIO_TX_T142P DQ48T/DIFFIO_TX_T142N DQ48T/DIFFIO_TX_T144P DQ48T/DIFFIO_TX_T144N DQS47T/DIFFIO_RX_T141P DQSN47T/DIFFIO_RX_T141N DQS48T/DIFFIO_RX_T143P DQSN48T/DIFFIO_RX_T143N L24 K24 C P23 N23 T24 R24 N24 M24 H23 G23 H22 G22 C22 D22 B23 A23 DDR3_DQ53 DDR3_DQ51 DDR3_DQ48 DDR3_DQ50 DDR3_DQ54 DDR3_DQ52 DDR3_DQ49 DDR3_DQ55 F23 E23 B22 A22 DDR3_DQS_P6 DDR3_DQS_N6 DDR3_DM6 B STRATIX V USB INTERFACE USB_DATA[7:0] Version = 1.0 Pin-out 5SGXA7KF40 Version = 1.0 Pin-out USB_ADDR[1:0] USB_SCL USB_SDA USB_RESETn USB_OEn USB_RDn USB_WRn In order to operate DDR3 at 1066MHz Altera requires all DDR3 address and command signals to be in the same sub-bank. With the current DDR3 pin out this board only supports DDR3 up to 800MHz. In order to support DDR3 at 1066MHz in the future DDR3_RASn would need to move to sub-bank 8B, pin U15.D30. A USB_DATA[7:0] 25 USB_ADDR[1:0] 25 USB_SCL USB_SDA USB_RESETn USB_OEn USB_RDn USB_WRn 25 25 25 25 25 25 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 7 of 1 34 D1.1 8 7 6 5 4 3 2 1 Stratix V GX Transceivers and Power U15Q U15R Stratix V GX Transceivers Stratix V GX Transceivers Bank GXB_R0 Bank GXB_L0 0 PCIE_RX_P0 PCIE_RX_N0 PCIE_RX_P1 PCIE_RX_N1 PCIE_RX_P2 PCIE_RX_N2 PCIE_RX_P3 PCIE_RX_N3 3 3 CMU PLL (PCIe) PCIE_RX_P4 PCIE_RX_N4 AV38 AV39 AT38 AT39 AP38 AP39 AM38 AM39 AK38 AK39 AH38 AH39 3 3 10 10 PCIE_REFCLK_P PCIE_REFCLK_N REFCLK1_QL0_P REFCLK1_QL0_N AF34 AF35 AD33 AD34 3 3 3 3 3 3 PCIE_RX_P5 PCIE_RX_N5 PCIE_RX_P6 PCIE_RX_N6 PCIE_RX_P7 PCIE_RX_N7 AF38 AF39 AD38 AD39 AB38 AB39 Y38 Y39 V38 V39 T38 T39 GXB_RX_L0P,GXB_REFCLK_L0P GXB_RX_L0N,GXB_REFCLK_L0N GXB_RX_L1P,GXB_REFCLK_L1P GXB_RX_L1N,GXB_REFCLK_L1N GXB_RX_L2P,GXB_REFCLK_L2P GXB_RX_L2N,GXB_REFCLK_L2N GXB_RX_L3P,GXB_REFCLK_L3P GXB_RX_L3N,GXB_REFCLK_L3N GXB_RX_L4P,GXB_REFCLK_L4P GXB_RX_L4N,GXB_REFCLK_L4N GXB_RX_L5P,GXB_REFCLK_L5P GXB_RX_L5N,GXB_REFCLK_L5N GXB_TX_L0P GXB_TX_L0N GXB_TX_L1P GXB_TX_L1N GXB_TX_L2P GXB_TX_L2N GXB_TX_L3P GXB_TX_L3N GXB_TX_L4P GXB_TX_L4N GXB_TX_L5P GXB_TX_L5N AU36 AU37 AR36 AR37 AN36 AN37 AL36 AL37 AJ36 AJ37 AG36 AG37 PCIE_TX_P0 PCIE_TX_N0 PCIE_TX_P1 PCIE_TX_N1 PCIE_TX_P2 PCIE_TX_N2 PCIE_TX_P3 PCIE_TX_N3 3 3 3 3 3 3 3 3 CMU PLL (PCIe) PCIE_TX_P4 PCIE_TX_N4 R188 0 3 3 REFCLK0LP REFCLK0LN REFCLK1LP REFCLK1LN D 22 22 HSMA_RX_P0 HSMA_RX_N0 22 22 22 22 22 22 22 22 CMU (PCIe Gen 1/2) HSMA_RX_P1 HSMA_RX_N1 HSMA_RX_P2 HSMA_RX_N2 HSMA_RX_P3 HSMA_RX_N3 HSMA_RX_P4 HSMA_RX_N4 AV2 AV1 AT2 AT1 AP2 AP1 AM2 AM1 AK2 AK1 AH2 AH1 10 10 10 10 REFCLK0_QR0_P REFCLK0_QR0_N REFCLK1_QR0_P REFCLK1_QR0_N AF6 AF5 AD7 AD6 22 22 22 22 22 22 22 22 22 22 HSMA_RX_P5 HSMA_RX_N5 HSMA_RX_P6 HSMA_RX_N6 HSMA_RX_P7 HSMA_RX_N7 HSMB_RX_P2 HSMB_RX_N2 HSMB_RX_P3 HSMB_RX_N3 AF2 AF1 AD2 AD1 AB2 AB1 Y2 Y1 V2 V1 T2 T1 10 10 REFCLK2_QR1_P AB6 REFCLK2_QR1_N AB5 Y7 Y6 GXB_RX_R0P,GXB_REFCLK_R0P GXB_RX_R0N,GXB_REFCLK_R0N GXB_RX_R1P,GXB_REFCLK_R1P GXB_RX_R1N,GXB_REFCLK_R1N GXB_RX_R2P,GXB_REFCLK_R2P GXB_RX_R2N,GXB_REFCLK_R2N GXB_RX_R3P,GXB_REFCLK_R3P GXB_RX_R3N,GXB_REFCLK_R3N GXB_RX_R4P,GXB_REFCLK_R4P GXB_RX_R4N,GXB_REFCLK_R4N GXB_RX_R5P,GXB_REFCLK_R5P GXB_RX_R5N,GXB_REFCLK_R5N 0 REFCLK2_QL1_P REFCLK2_QL1_N 10 10 10.0K R298 AB34 AB35 Y33 Y34 C R303 0 B QSFP_RX_P0 QSFP_RX_N0 QSFP_RX_P1 QSFP_RX_N1 QSFP_RX_P2 QSFP_RX_N2 QSFP_RX_P3 QSFP_RX_N3 SDI_RX_P SDI_RX_N P38 P39 M38 M39 K38 K39 H38 H39 F38 F39 D38 D39 10 10 10 10 REFCLK4_QL2_P REFCLK4_QL2_N REFCLK5_QL2_P REFCLK5_QL2_N V34 V35 T33 T34 GXB_RX_L6P,GXB_REFCLK_L6P GXB_RX_L6N,GXB_REFCLK_L6N GXB_RX_L7P,GXB_REFCLK_L7P GXB_RX_L7N,GXB_REFCLK_L7N GXB_RX_L8P,GXB_REFCLK_L8P GXB_RX_L8N,GXB_REFCLK_L8N GXB_RX_L9P,GXB_REFCLK_L9P GXB_RX_L9N,GXB_REFCLK_L9N GXB_RX_L10P,GXB_REFCLK_L10P GXB_RX_L10N,GXB_REFCLK_L10N GXB_RX_L11P,GXB_REFCLK_L11P GXB_RX_L11N,GXB_REFCLK_L11N GXB_TX_L6P GXB_TX_L6N GXB_TX_L7P GXB_TX_L7N GXB_TX_L8P GXB_TX_L8N GXB_TX_L9P GXB_TX_L9N GXB_TX_L10P GXB_TX_L10N GXB_TX_L11P GXB_TX_L11N PCIE_TX_P5 PCIE_TX_N5 PCIE_TX_P6 PCIE_TX_N6 PCIE_TX_P7 PCIE_TX_N7 3 3 3 3 3 3 R187 REFCLK2LP REFCLK2LN REFCLK3LP REFCLK3LN 10.0K 0 R198 GXB_RX_R6P,GXB_REFCLK_R6P GXB_RX_R6N,GXB_REFCLK_R6N GXB_RX_R7P,GXB_REFCLK_R7P GXB_RX_R7N,GXB_REFCLK_R7N GXB_RX_R8P,GXB_REFCLK_R8P GXB_RX_R8N,GXB_REFCLK_R8N GXB_RX_R9P,GXB_REFCLK_R9P GXB_RX_R9N,GXB_REFCLK_R9N GXB_RX_R10P,GXB_REFCLK_R10P GXB_RX_R10N,GXB_REFCLK_R10N GXB_RX_R11P,GXB_REFCLK_R11P GXB_RX_R11N,GXB_REFCLK_R11N R309 R305 RREF_R0 RREF_R1 B39 AW36 22 22 CMU (PCIe Gen 1/2) HSMA_TX_P1 HSMA_TX_N1 HSMA_TX_P2 HSMA_TX_N2 HSMA_TX_P3 HSMA_TX_N3 HSMA_TX_P4 HSMA_TX_N4 22 22 22 22 22 22 22 22 AE4 AE3 AC4 AC3 AA4 AA3 W4 W3 U4 U3 R4 R3 HSMA_TX_P5 HSMA_TX_N5 HSMA_TX_P6 HSMA_TX_N6 HSMA_TX_P7 HSMA_TX_N7 HSMB_TX_P2 HSMB_TX_N2 HSMB_TX_P3 HSMB_TX_N3 SMA_TX_P SMA_TX_N D GXB_TX_R6P GXB_TX_R6N GXB_TX_R7P GXB_TX_R7N GXB_TX_R8P GXB_TX_R8N GXB_TX_R9P GXB_TX_R9N GXB_TX_R10P GXB_TX_R10N GXB_TX_R11P GXB_TX_R11N 22 22 22 22 22 22 22 22 22 22 REFCLK2RP REFCLK2RN REFCLK3RP REFCLK3RN C Bank GXB_R2 GXB_RX_L12P,GXB_REFCLK_L12P GXB_RX_L12N,GXB_REFCLK_L12N GXB_RX_L13P,GXB_REFCLK_L13P GXB_RX_L13N,GXB_REFCLK_L13N GXB_RX_L14P,GXB_REFCLK_L14P GXB_RX_L14N,GXB_REFCLK_L14N GXB_RX_L15P,GXB_REFCLK_L15P GXB_RX_L15N,GXB_REFCLK_L15N GXB_RX_L16P,GXB_REFCLK_L16P GXB_RX_L16N,GXB_REFCLK_L16N GXB_RX_L17P,GXB_REFCLK_L17P GXB_RX_L17N,GXB_REFCLK_L17N GXB_TX_L12P GXB_TX_L12N GXB_TX_L13P GXB_TX_L13N GXB_TX_L14P GXB_TX_L14N GXB_TX_L15P GXB_TX_L15N GXB_TX_L16P GXB_TX_L16N GXB_TX_L17P GXB_TX_L17N N36 N37 L36 L37 J36 J37 G36 G37 E36 E37 C36 C37 QSFP_TX_P0 QSFP_TX_N0 QSFP_TX_P1 QSFP_TX_N1 QSFP_TX_P2 QSFP_TX_N2 QSFP_TX_P3 QSFP_TX_N3 SDI_TX_P SDI_TX_N 22 22 22 22 HSMB_RX_P0 HSMB_RX_N0 HSMB_RX_P1 HSMB_RX_N1 P2 P1 M2 M1 K2 K1 H2 H1 F2 F1 D2 D1 10 10 10 10 REFCLK4_QR2_P REFCLK4_QR2_N REFCLK5_QR2_P REFCLK5_QR2_N V6 V5 T7 T6 R186 19 19 19 19 19 19 19 19 21 21 REFCLK4LP REFCLK4LN REFCLK5LP REFCLK5LN 0 GXB_RX_R12P,GXB_REFCLK_R12P GXB_RX_R12N,GXB_REFCLK_R12N GXB_RX_R13P,GXB_REFCLK_R13P GXB_RX_R13N,GXB_REFCLK_R13N GXB_RX_R14P,GXB_REFCLK_R14P GXB_RX_R14N,GXB_REFCLK_R14N GXB_RX_R15P,GXB_REFCLK_R15P GXB_RX_R15N,GXB_REFCLK_R15N GXB_RX_R16P,GXB_REFCLK_R16P GXB_RX_R16N,GXB_REFCLK_R16N GXB_RX_R17P,GXB_REFCLK_R17P GXB_RX_R17N,GXB_REFCLK_R17N GXB_TX_R12P GXB_TX_R12N GXB_TX_R13P GXB_TX_R13N GXB_TX_R14P GXB_TX_R14N GXB_TX_R15P GXB_TX_R15N GXB_TX_R16P GXB_TX_R16N GXB_TX_R17P GXB_TX_R17N REFCLK4RP REFCLK4RN REFCLK5RP REFCLK5RN Reference Resistor 1.80K 1.80K HSMA_TX_P0 HSMA_TX_N0 Bank GXB_R1 AE36 AE37 AC36 AC37 AA36 AA37 W36 W37 U36 U37 R36 R37 Bank GXB_L2 19 19 19 19 19 19 19 19 21 21 E AU4 AU3 AR4 AR3 AN4 AN3 AL4 AL3 AJ4 AJ3 AG4 AG3 REFCLK0RP REFCLK0RN REFCLK1RP REFCLK1RN Bank GXB_L1 R310 GXB_TX_R0P GXB_TX_R0N GXB_TX_R1P GXB_TX_R1N GXB_TX_R2P GXB_TX_R2N GXB_TX_R3P GXB_TX_R3N GXB_TX_R4P GXB_TX_R4N GXB_TX_R5P GXB_TX_R5N N4 N3 L4 L3 J4 J3 G4 G3 E4 E3 C4 C3 DP_ML_LANE_P0 DP_ML_LANE_N0 DP_ML_LANE_P1 DP_ML_LANE_N1 DP_ML_LANE_P2 DP_ML_LANE_N2 DP_ML_LANE_P3 DP_ML_LANE_N3 HSMB_TX_P0 HSMB_TX_N0 HSMB_TX_P1 HSMB_TX_N1 1 SMA_TX_P R185 R192 RREF_L0 RREF_L1 B1 AW4 RREF_TR RREF_BR 5SGXA7KF40 5SGXA7KF40 Version = 1.0 Pin-out Version = 1.0 Pin-out A J6 B Reference Resistor 1.80K 1.80K RREF_TL RREF_BL 20 20 20 20 20 20 20 20 22 22 22 22 2 3 4 5 R304 3 3 3 3 3 3 3 3 1 SMA_TX_N J3 2 3 4 5 E A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 8 of 1 34 D1.1 8 7 6 5 4 3 2 1 Stratix V GX Clocks STRATIX V CLOCKS CLKINTOP_P[1:0] CLKINTOP_N[1:0] U15I E Stratix V GX Clocks CLKINBOT_P[1:0] HSMA_CLK_IN_P1 HSMA_CLK_IN_P2 HSMB_CLK_IN_P1 HSMB_CLK_IN_P2 R202 R196 R224 R223 100, 1% 100, 1% 100, 1% 100, 1% HSMA_CLK_IN_N1 HSMA_CLK_IN_N2 HSMB_CLK_IN_N1 HSMB_CLK_IN_N2 CLKINBOT_P1 CLKINTOP_P0 CLKINTOP_P1 CLKINBOT_P0 R225 R261 R286 R253 100, 1% 100, 1% 100, 1% 100, 1% CLKINBOT_N1 CLKINTOP_N0 CLKINTOP_N1 CLKINBOT_N0 Bank 3B CLK_125_P CLK_125_N USB_CLK SDI_CLK148_UP HSMB_CLK_IN0 USER_LED_R1 HSMA_CLK_IN0 USER_LED_R0 AV29 AW29 AV28 AW28 AF29 AG30 AG28 AH28 CLK0P/DQS8B/DIFFIO_RX_B22P CLK0N/DQSN8B/DIFFIO_RX_B22N CLK1P/DQ8B/DIFFIO_RX_B24P CLK1N/DQ8B/DIFFIO_RX_B24N CLK2P/DQS10B/DIFFIO_RX_B28P CLK2N/DQSN10B/DIFFIO_RX_B28N CLK3P/DQ10B/DIFFIO_RX_B30P CLK3N/DQ10B/DIFFIO_RX_B30N FPLL_BL_CLKOUTP/DQ9B/DIFFIO_TX_B25P FPLL_BL_CLKOUTN/DQ9B/DIFFIO_TX_B25N FPLL_BL_FB/CLKOUTP/DQS9B/DIFFIO_RX_B26P FPLL_BL_FB/CLKOUTN/DQSN9B/DIFFIO_RX_B26N AH22 AJ22 AK23 AL23 D AL7 AM7 AN6 AN7 AR8 AT8 AV7 AW7 AF17 AG17 AE17 AE16 CLK8P/DQS70B/DIFFIO_RX_B208P CLK8N/DQSN70B/DIFFIO_RX_B208N CLK9P/DQS69B/DIFFIO_RX_B206P CLK9N/DQSN69B/DIFFIO_RX_B206N CLK10P/DQS68B/DIFFIO_RX_B202P CLK10N/DQSN68B/DIFFIO_RX_B202N CLK11P/DQS67B/DIFFIO_RX_B200P CLK11N/DQSN67B/DIFFIO_RX_B200N CLK6P/DQS48B/DIFFIO_RX_B142P CLK6N/DQSN48B/DIFFIO_RX_B142N CLK7P/DQ48B/DIFFIO_RX_B144P CLK7N/DQ48B/DIFFIO_RX_B144N C USER_PB1 USER_PB0 USER_PB2 G7 G6 L6 K6 B7 A7 D7 C7 P16 N16 U15 T16 MAX5_CLK E34 D34 D33 C33 N32 M32 R32 P32 CLKINTOP_P1 CLKINTOP_N1 CLK20P/DQS67T/DIFFIO_RX_T201P CLK20N/DQSN67T/DIFFIO_RX_T201N CLK21P/DQ67T/DIFFIO_RX_T199P CLK21N/DQ67T/DIFFIO_RX_T199N CLK22P/DQS65T/DIFFIO_RX_T195P CLK22N/DQSN65T/DIFFIO_RX_T195N CLK23P/DQ65T/DIFFIO_RX_T193P CLK23N/DQ65T/DIFFIO_RX_T193N J23 J24 M23 L23 VCCIO = 1.8V VCCIO = HSMB VARIABLE FPLL_TR_FB/CLKOUTP/DQ3T/DIFFIO_RX_T7P FPLL_TR_FB/CLKOUTN/DQ3T/DIFFIO_RX_T7N FPLL_TR_CLKOUTP/DQ3T/DIFFIO_TX_T8P FPLL_TR_CLKOUTN/DQ3T/DIFFIO_TX_T8N AT6 AU6 AP7 AR7 10 10,18 10 10 10 18,25 25 25 22 HSMA_CLK_IN_N[2:1] 22 HSMB_CLK_IN_P[2:1] AH16 AJ17 AK17 AL17 22 22 VCCIO = HSMB VARIABLE FPLL_TC_FB/CLKOUTP/DQS24T/DIFFIO_RX_T71P FPLL_TC_FB/CLKOUTN/DQSN24T/DIFFIO_RX_T71N FPLL_TC_CLKOUTP/DQ24T/DIFFIO_TX_T72P FPLL_TC_CLKOUTN/DQ24T/DIFFIO_TX_T72N VCCIO = 1.5V FPLL_TL_FB/CLKOUTP/DQS66T/DIFFIO_RX_T197P FPLL_TL_FB/CLKOUTN/DQSN66T/DIFFIO_RX_T197N FPLL_TL_CLKOUTP/DQ66T/DIFFIO_TX_T198P FPLL_TL_CLKOUTN/DQ66T/DIFFIO_TX_T198N 22 22 HSMB_CLK_OUT0 FM_A24 FM_A26 FM_A21 FM_A20 22 QSFP INTERFACE QSFP_RSTn QSFP_SCL QSFP_SDA A3 A4 A6 A5 J16 J17 L16 K16 L33 L34 P34 N34 19 19 19 QSFP_RSTn QSFP_SCL QSFP_SDA C FLASH INTERFACE FLASH_ADVn 17,18 FLASH_RDYBSYn1 17,18 17,18,4,5 MAX V CONTROL MAX5_CLK HSMB_CLK_OUT0 USER_PB[2:0] 18 24 LCD & USER I/O INTERFACES USER_LED_R[7:0] USB_EMPTY USB_FULL USER_LED_G[7:0] B 24,4 11,24,4,5,6 SDI INTERFACES SDI_RX_BYPASS VCCIO = 1.5V 18,21 SDI_RX_BYPASS RLDRAM II INTERFACE CLK16P/DQS45T/DIFFIO_RX_T135P CLK16N/DQSN45T/DIFFIO_RX_T135N CLK17P/DQ45T/DIFFIO_RX_T133P CLK17N/DQ45T/DIFFIO_RX_T133N 5SGXA7KF40 CLKINBOT_N[1:0] D HSMA_CLK_IN_P[2:1] FM_A19 FM_A18 FLASH_ADVn USER_LED_G6 FM_A[26:0] Bank 8D CLKINTOP_P0 CLKINTOP_N0 10 HSMC INTERFACE VCCIO = 1.8V FPLL_BC_CLKOUTP/DQ47B/DIFFIO_TX_B139P FPLL_BC_CLKOUTN/DQ47B/DIFFIO_TX_B139N FPLL_BC_FB/CLKOUTP/DQS47B/DIFFIO_RX_B140P FPLL_BC_FB/CLKOUTN/DQSN47B/DIFFIO_RX_B140N Bank 8A B CLKINBOT_P[1:0] USB_FULL USB_EMPTY HSMA_CLK_IN0 HSMB_CLK_IN0 CLK12P/DQS1T/DIFFIO_RX_T3P CLK12N/DQSN1T/DIFFIO_RX_T3N CLK13P/DQS2T/DIFFIO_RX_T5P CLK13N/DQSN2T/DIFFIO_RX_T5N CLK14P/DQS3T/DIFFIO_RX_T9P CLK14N/DQSN3T/DIFFIO_RX_T9N CLK15P/DQS4T/DIFFIO_RX_T11P CLK15N/DQSN4T/DIFFIO_RX_T11N CLK18P/DQS23T/DIFFIO_RX_T69P CLK18N/DQSN23T/DIFFIO_RX_T69N CLK19P/DQ23T/DIFFIO_RX_T67P CLK19N/DQ23T/DIFFIO_RX_T67N 10 E USB_CLK HSMB_CLK_IN_N[2:1] Bank 7D HSMB_CLK_IN_P2 HSMB_CLK_IN_N2 HSMB_CLK_IN_P1 HSMB_CLK_IN_N1 CLKINTOP_N[1:0] CLKIN_50 CLK_125_P CLK_125_N SDI_CLK148_UP USB_CLK VCCIO = 1.8V FPLL_BR_CLKOUTP/DQ68B/DIFFIO_TX_B203P FPLL_BR_CLKOUTN/DQ68B/DIFFIO_TX_B203N FPLL_BR_FB/CLKOUTP/DQ68B/DIFFIO_RX_B204P FPLL_BR_FB/CLKOUTN/DQ68B/DIFFIO_RX_B204N Bank 7A HSMA_CLK_IN_P2 HSMA_CLK_IN_N2 CLKIN_50 CLK_125_P CLK_125_N SDI_CLK148_UP USB_FULL USB_EMPTY Bank 4D CLKINBOT_P1 CLKINBOT_N1 FM_A23 FM_A22 CLKINBOT_N[1:0] QSFP_SCL QSFP_RSTn SDI_RX_BYPASS QSFP_SDA CLK4P/DQS26B/DIFFIO_RX_B76P CLK4N/DQSN26B/DIFFIO_RX_B76N CLK5P/DQ26B/DIFFIO_RX_B78P CLK5N/DQ26B/DIFFIO_RX_B78N Bank 4A USER_LED_R2 USER_LED_R4 CLKIN_50 FLASH_RDYBSYn1 HSMA_CLK_IN_P1 HSMA_CLK_IN_N1 USER_LED_R7 USER_LED_R5 AD30 AE30 AB30 AC30 10 STRATIX V USB INTERFACE Bank 3D CLKINBOT_P0 CLKINBOT_N0 RLDC_BA2 USER_LED_R6 VCCIO = 2.5V CLKINTOP_P[1:0] RLDC_BA[2:0] RLDC_BA[2:0] 16,4 Version = 1.0 Pin-out A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 9 of 1 34 D1.1 8 7 6 5 4 3 2 1 PLL 2.5V 2.5V 2.5V 7 18 8 CLOCK_SCL 3 OE VCC SDA CLK+ SCL CLK- GND NC R211 4.7K VDD VDD VDD 4 R210 100, 1% 2.5V 5 R215 BUFFER_EN 4.7K GL 1 R241 4.7K SI570 Si570 Programmable Oscillator Use Clock Control GUI (Default 100MHz) J13 I2C Address 00 HEX 100M_OSC_P 100M_OSC_N 1 CLKIN_SMA_P LTI-SASF546-P26-X1 C365 0.1uF PDn 1 8 21 CLKIN_SMA_CP CLKIN_SMA_CN 16 15 CLK_SEL 28 CLKIN_SMA_CP CLKIN_SMA_CN 124 124 5 4 3 2 100, 1% 100, 1% R264 R263 1 CLKIN_SMA_N LTI-SASF546-P26-X1 J14 R257 R255 18,24 CLK_SEL IDT5T9306 C364 Q5p Q5n CLK2p CLK2n Q6p Q6n C324 C296 0.1uF 0.1uF 2.2uF CLKINTOP_P0 CLKINTOP_N0 9 9 10 11 CLKINBOT_P0 CLKINBOT_N0 9 9 12 13 REFCLK1_QL0_CPC294 0.1uF 0.1uF REFCLK1_QL0_CN C295 REFCLK1_QL0_P REFCLK1_QL0_N 8 8 19 18 0.1uF REFCLK4_QR2_CPC323 REFCLK4_QR2_CN C322 0.1uF REFCLK4_QR2_P REFCLK4_QR2_N 8 8 24 23 26 25 R112 4 5 6 C CLOCK_SCL 12 CLOCK_SDA 19 Si571_EN C52 SI571_EN 18 2 CLOCK_SDA 7 CLOCK_SCL 8 OE VDD SDA CLK+ SCL CLK- GND VC D 6 4 REFCLK5_QL2_CP 5 REFCLK5_QL2_CN 1 SI571_VCONTROL SI571 CLKIN_P CLKIN_N CLKIN I2C_LSB FDBK_P FDBK_N SCL 7 24 11 15 16 20 VDD1 VDD2 VDDO3 VDDO2 VDDO1 VDDO0 2.5V_RPLL C30 0.1uF L6 C29 C211 C238 C239 C212 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF Si571 Programmable Oscillator Use Clock Control GUI (Default 148.5MHz) I2C Address 55 HEX BLM15AG221SN1 SDI_CLK148_UP SDI_CLK148_DN R296 R295 4.70K, 1% 9 10 CLK3B CLK3A SDA CLK0B CLK0A C226 C227 REFCLK5_QR2_CN REFCLK5_QR2_CP 1.0nF R194 0.1uF 0.1uF REFCLK5_QR2_N REFCLK5_QR2_P SDI_CLK148_UP SDI_CLK148_DN 8 8 13 14 REFCLK2_QR1_CN REFCLK2_QR1_CP C256 C257 0.1uF 0.1uF REFCLK2_QR1_N REFCLK2_QR1_P 8 8 17 18 REFCLK1_QR0_CN REFCLK1_QR0_CP C258 C259 0.1uF 0.1uF REFCLK1_QR0_N REFCLK1_QR0_P 8 8 21 22 REFCLK0_QR0_CN REFCLK0_QR0_CP C229 C228 0.1uF 0.1uF REFCLK0_QR0_N REFCLK0_QR0_P 8 8 180K 9 5 C C471 0.1uF 1.8V X3 18 LVDS 23 25 RSVD_GND EPAD 1 CLK50_EN 2 Si5338 Programmable Oscillator Use Clock Control GUI (Defaults 100MHz, 156.25MHz, 625MHz, 270MHz) I2C Address 70 HEX EN VCC GND OUT 4 3 CLKIN_50 50MHz Si5338A-CUSTOM C219 C220 2.2uF 0.1uF 18,9 DNI B 1 2 3 3 2.5V_PLL CLKIN_P CLKIN_N CLKIN 4 5 6 CLOCK_SCL 12 CLOCK_SDA 19 I2C_LSB FDBK_P FDBK_N SCL VDD1 VDD2 VDDO3 VDDO2 VDDO1 VDDO0 INTR CLK3B CLK3A SDA CLK2B CLK2A CLK1B CLK1A A CLK0B CLK0A RSVD_GND EPAD Si5338A-CUSTOM 7 B U46 1 DNI 2.5V Y3 25.00MHz 2 4 8 C434 From FPGA CLK1B CLK1A C354 4.99K 4.99K R302 8 INTR CLK2B CLK2A C371 C49 0.1uF 10uF U38 1 DNI 4.70K, 1% 2.5V 1 2 3 8 8 X6 0.1uF CLK_SEL = HIGH selects (CLK1p/n) Si570 input CLK_SEL = LOW selects (CLK2p/n) SMA input Y2 25.00MHz 2 0.1uFREFCLK5_QL2_N 0.1uFREFCLK5_QL2_P 2.5V 3 4 C180 REFCLK5_QL2_CN C500 REFCLK5_QL2_CPC501 2.5V DNI 3 C195 E 3 4 5 4 3 2 D R254 R256 Q4p Q4n CLK1p CLK1n 3.3V 84.5 84.5 Q3p Q3n PDn 6 7 Q1p Q1n Q2p Q2n Gn GL GND 18 CLOCK_SDA 6 C243 29 18 2 U41 9 5 2 0.1uF 10uF X4 SI570_EN 14 17 20 27 C244 C232 2.5V E VDD VDD VDD VDD Si570_EN CLOCK_SDA CLOCK_SCL NC 4.70K, 1% 4.70K, 1% 4.70K, 1% 22 R203 R204 R226 6 7 24 11 15 16 20 C408 0.1uF 2.5V_PLL C48 C47 0.1uF L9 C406 0.1uF C407 0.1uF X1 C421 0.1uF 0.1uF 18 BLM15AG221SN1 1 CLK125_EN 2 2.5V 6 8 R285 4.70K, 1% C34 C28 EN NC OUT OUTn VCC GND 4 CLK_125_P 9 5 CLK_125_N 9 3 125.0MHz 9 10 CLKINTOP_N1 CLKINTOP_P1 13 14 REFCLK4_QL2_CN REFCLK4_QL2_CP C435 C436 0.1uF 0.1uF REFCLK4_QL2_N REFCLK4_QL2_P 8 8 17 18 REFCLK2_QL1_CN REFCLK2_QL1_CP C437 C438 0.1uF 0.1uF REFCLK2_QL1_N REFCLK2_QL1_P 8 8 21 22 CLKINBOT_N1 CLKINBOT_P1 23 25 0.1uF 9 9 10uF Title LVDS Si5338 Programmable Oscillator Use Clock Control GUI (Defaults 125MHz, 644.53125MHz, 282.5MHz, 125MHz) I2C Address 71 HEX Size B Date: 5 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 9 9 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 10 of 1 34 D1.1 8 7 6 5 R123 DNI C66 3 2 1 Stratix V GX Configuration 2.5V DNI U15J R299 10K R124 DNI 2.5V Stratix V GX Configuration Bank 3A AC31 18 FPGA_nCONFIG AK35 24 3 PCIE_LED_G3 PCIE_SMBCLK AN34 AN33 3 18 AP34 AM34 ENET_RX_P CPU_RESETn 23 18,24 PCIE_SMBDAT FPGA_CONFIG_D[31:0] AL34 D C FPGA_CONFIG_D0 FPGA_CONFIG_D1 FPGA_CONFIG_D2 FPGA_CONFIG_D3 FPGA_CONFIG_D4 FPGA_CONFIG_D5 FPGA_CONFIG_D6 FPGA_CONFIG_D7 FPGA_CONFIG_D8 FPGA_CONFIG_D9 FPGA_CONFIG_D10 FPGA_CONFIG_D11 FPGA_CONFIG_D12 FPGA_CONFIG_D13 FPGA_CONFIG_D14 FPGA_CONFIG_D15 FPGA_CONFIG_D16 FPGA_CONFIG_D17 FPGA_CONFIG_D18 FPGA_CONFIG_D19 FPGA_CONFIG_D20 FPGA_CONFIG_D21 FPGA_CONFIG_D22 FPGA_CONFIG_D23 FPGA_CONFIG_D24 FPGA_CONFIG_D25 FPGA_CONFIG_D26 FPGA_CONFIG_D27 FPGA_CONFIG_D28 AP33 AT33 AR33 AU34 AU33 AN31 AM31 AU32 AT32 AR31 AP31 AW34 AV34 AW31 AV31 AW32 AV32 AJ33 AH33 AL33 AK33 AK32 AJ32 AH31 AG31 AF31 AE31 AJ30 AH30 FPGA_CONFIG_D29 FPGA_CONFIG_D30 FPGA_CONFIG_D31 AR30 AP30 AU30 DCLK TCK TMS TDO TDI TRST NCONFIG CLKUSR/DQ1B/DIFFIO_TX_B1N CRC_ERROR/DQ1B/DIFFIO_TX_B1P AS_DATA0,ASDO AS_DATA1 AS_DATA2 AS_DATA3 DEV_OE/DQS1B/DIFFIO_RX_B2P DEV_CLRN/DQ1B/DIFFIO_TX_B3N INIT_DONE/DQ1B/DIFFIO_TX_B3P NCSO DATA0/DQS2B/DIFFIO_RX_B4P DATA1/DQ2B/DIFFIO_TX_B5N DATA2/DQ2B/DIFFIO_TX_B5P DATA3/DQ2B/DIFFIO_RX_B6N DATA4/DQ2B/DIFFIO_RX_B6P DATA5/DQ3B/DIFFIO_TX_B7N DATA6/DQ3B/DIFFIO_TX_B7P DATA7/DQSN3B/DIFFIO_RX_B8N DATA8/DQS3B/DIFFIO_RX_B8P DATA9/DQ3B/DIFFIO_TX_B9N DATA10/DQ3B/DIFFIO_TX_B9P DATA11/DQSN4B/DIFFIO_RX_B10N DATA12/DQS4B/DIFFIO_RX_B10P DATA13/DQ4B/DIFFIO_TX_B11N DATA14/DQ4B/DIFFIO_TX_B11P DATA15/DQ4B/DIFFIO_RX_B12N DATA16/DQ4B/DIFFIO_RX_B12P DATA17/DQ5B/DIFFIO_TX_B13N DATA18/DQ5B/DIFFIO_TX_B13P DATA19/DQSN5B/DIFFIO_RX_B14N DATA20/DQS5B/DIFFIO_RX_B14P DATA21/DQ5B/DIFFIO_TX_B15N DATA22/DQ5B/DIFFIO_TX_B15P DATA23/DQSN6B/DIFFIO_RX_B16N DATA24/DQS6B/DIFFIO_RX_B16P DATA25/DQ6B/DIFFIO_TX_B17N DATA26/DQ6B/DIFFIO_TX_B17P DATA27/DQ6B/DIFFIO_RX_B18N DATA28/DQ6B/DIFFIO_RX_B18P NCEO/DQSN2B/DIFFIO_RX_B4N AA31 AT35 AH34 AJ34 AM35 10K E JTAG_TCK JTAG_TMS JTAG_FPGA_TDO JTAG_BLASTER_TDO R306 12,18,22,25 12,25 25 12,25 AB31 Y31 AC32 AG32 FPGA_AS_DATA0 FPGA_AS_DATA1 FPGA_AS_DATA2 FPGA_AS_DATA3 17 17 17 17 AD32 FPGA_nCSO 17 AN32 PCIE_WAKEn 3 USER I/O INTERFACES USER_LED_G[7:0] 24,4,5,6,9 D S5_VCCPD_PGM_2.5V C R272 FPGA_DCLK R276 17,18 R271 E R287 FPGA_DCLK 4 10K 10K 10K 10K Bank 3B DATA29/DQ7B/DIFFIO_TX_B19N DATA30/DQ7B/DIFFIO_TX_B19P DATA31/DQSN7B/DIFFIO_RX_B20N PR_DONE/DQS7B/DIFFIO_RX_B20P PR_REQUEST/DQ7B/DIFFIO_TX_B21N PR_READY/DQ7B/DIFFIO_TX_B21P PR_ERROR/DQ8B/DIFFIO_TX_B23N CVP_CONFDONE/DQ8B/DIFFIO_TX_B23P NPERSTL0/DQ9B/DIFFIO_TX_B27N NPERSTL1/DQ9B/DIFFIO_TX_B27P NPERSTR0/DQ10B/DIFFIO_TX_B29P NPERSTR1/DQ10B/DIFFIO_TX_B29N 2.5V B R201 10K R193 10K AT30 AN30 AN29 AU29 FPGA_PR_DONE FPGA_PR_REQUEST FPGA_PR_READY FPGA_PR_ERROR 18 18 18 18 AT29 FPGA_CvP_CONFDONE 18 AC28 AB28 AF28 AE29 PCIE_PERSTn SDI_RX_EN 3 18,21 USER_LED_G4 USER_LED_G5 B Bank 4A 18 18 AH6 AM5 AC8 CONF_DONE NSTATUS MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 NCE NIO_PULLUP Temperature Sense TEMPDIODE_P TEMPDIODE_N 31 31 R6 P5 AA30 AL19 J19 AA9 AA10 AD8 AG8 AH7 MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 18 18 18 18 18 2.5V AK5 SW4 1 2 3 4 5 6 Do Not Use TEMPDIODEP TEMPDIODEN DNU_4 DNU_5 DNU_6 DNU_7 DNU_8 DNU_9 DNU_1 DNU_2 DNU_3 Y20 AV35 AV5 AW35 AW5 R7 12 11 10 9 8 7 MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 Size B Date: 7 6 5 1.00k 1.00k 1.00k 1.00k 1.00k A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Version = 1.0 Pin-out Title 8 R135 R136 R137 R138 R139 TDA06H0SB1 A 5SGXA7KF40 OPEN FPGA_CONF_DONE FPGA_nSTATUS 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 11 of 1 34 D1.1 8 7 6 2.5V 0.1uF 5 0.1uF JTAG_TCK JTAG_BLASTER_TDO JTAG_BLASTER_TDI JTAG_TMS PCIE_JTAG_EN 18 VL C1 C2 C3 C4 IO_VL4 IO_VL3 IO_VL2 IO_VL1 B3 EN VCC IO_VCC1 IO_VCC2 IO_VCC3 IO_VCC4 GND B1 SW3 A4 A3 A2 A1 PCIE_JTAG_TCK PCIE_JTAG_TDI PCIE_JTAG_TDO PCIE_JTAG_TMS 1 2 3 4 3 3 3 3 B4 OPEN E 8 7 6 5 5M2210_JTAG_EN HSMA_JTAG_EN HSMB_JTAG_EN PCIE_JTAG_EN ON = not-in-chain OFF = in-chain DNI R110 JTAG_TCK R131 R132 R133 R134 E 1.00k 1.00k 1.00k 1.00k TS5A23157 Switch Functions When Pins 1 & 5 are: LOW --> NC to/from COM = ON and NO to/from COM = OFF HIGH --> NC to/from COM = OFF and NO to/from COM = ON DNI C53 DNI Logic 0 = pin 10 <--> pin 9 (5M2210 Bypass) Logic 1 = pin 10 <--> pin 2 (5M2210 Enable) U55 1 5M2210_JTAG_EN R107 1.00k 18 2.5V 2.5V J10 D USB_DISABLEn 25 2.5V R105 1.00k 2 4 6 8 10 1 3 5 7 9 JTAG_TCK JTAG_BLASTER_TDI JTAG_TMS 11,25 11,25 3 JTAG_TMS 4 5 5M2210_JTAG_EN R113 1.00k R122 1.00k R117 DNI IN1 COM1 NO1 NC1 GND V+ NO2 NC2 IN2 10 JTAG_BLASTER_TDI 9 JTAG_5M2210_TDI 2.5V 8 C565 25 0.1uF 2.5V COM2 7 R379 6 5M2210_JTAG_TMS 18 10 HSMB_JTAG_TDI 22 1.00k D TS5A23157 70247-1051 JTAG_BLASTER_TDO 2 JTAG_5M2210_TDO Logic 0 = pin 6 <--> pin 7 (5M2210 Bypass) Logic 1 = pin 6 <--> pin 4 (5M2210 Enable) 11,18,22,25 JTAG_BLASTER_TDO 1 2.5V JTAG Chain Control TDA04H0SB1 USB Blaster Programming Header (uses JTAG mode only) 2 C51 U22 B2 3 JTAG 3.3V C50 4 JTAG_BLASTER_TDI Logic 0 = pin 10 <--> pin 9 (HSMA Bypass) Logic 1 = pin 10 <--> pin 2 (HSMA Enable) Populate R117 if you would like to Master the JTAG chain through HSMC Port A or HSMC Port B. 22 U51 HSMA_JTAG_EN 1 HSMA_JTAG_TDO 2 Logic 0 = pin 6 <--> pin 7 (HSMA Bypass) Logic 1 = pin 6 <--> pin 4 (HSMA Enable) 3 JTAG_TMS 4 HSMA_JTAG_EN 5 C IN1 COM1 NO1 NC1 GND V+ NO2 NC2 IN2 9 8 COM2 JTAG_FPGA_TDO_RETIMER 22,25 2.5V HSMA TDI = JTAG_FPGA_TDO_RETIMER C533 0.1uF 2.5V 7 R355 6 HSMA_JTAG_TMS 1.00k 22 C TS5A23157 Logic 0 = pin 10 <--> pin 9 (HSMB Bypass) Logic 1 = pin 10 <--> pin 2 (HSMB Enable) 22 U54 HSMB_JTAG_EN 1 HSMB_JTAG_TDO 2 Logic 0 = pin 6 <--> pin 7 (HSMBBypass) Logic 1 = pin 6 <--> pin 4 (HSMB Enable) 3 JTAG_TMS 4 HSMB_JTAG_EN 5 IN1 10 COM1 NO1 NC1 GND V+ NO2 NC2 IN2 9 8 18 HSMB_JTAG_TDI 2.5V C554 0.1uF 2.5V 7 6 COM2 B JTAG_5M2210_TDI R374 1.00k HSMB_JTAG_TMS 22 B TS5A23157 A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 12 of 1 34 D1.1 8 7 DDR3_CLK_P 100, 1% 6 E VTT_DDR3 1 2 3 4 DDR3_DQS_P[8:0] 14,7 VTT_DDR3 CN1 DDR3_DQS_N[8:0] 14,7 2 8 7 6 5 1 2 3 4 VTT_DDR3 0.1uF 8 7 6 5 1 2 3 4 0.1uF 8 7 6 5 0.1uF 7 5 8 6 7 3 1 2 RN2G RN3E RN3H RN3F RN3G RN4C RN4A RN4B DDR3_A0 DDR3_A1 DDR3_A2 DDR3_A3 DDR3_A4 DDR3_A5 DDR3_A6 DDR3_A7 CN3 CN2 10 51 12 51 9 51 11 51 10 51 14 51 16 51 15 51 1 VTT_DDR3 DDR3_A8 DDR3_A9 DDR3_RESETn DDR3_A11 DDR3_A12 DDR3_A13 DDR3_A10 DDR3_CKE RN4F RN4D RN4G RN4E RN3D RN4H RN3B RN2B 6 4 7 5 4 8 2 2 11 51 13 51 10 51 12 51 13 51 9 51 15 51 15 51 VTT_DDR3 DDR3_CSn DDR3_WEn DDR3_RASn DDR3_BA0 DDR3_BA1 DDR3_BA2 DDR3_CASn DDR3_ODT RN2D RN3A RN2A RN2F RN3C RN2E RN2H RN2C 4 1 1 6 3 5 8 3 13 51 16 51 16 51 11 51 14 51 12 51 9 51 14 51 E DDR3_DQ[71:0] 14,7 DDR3_A[13:0] 14,7 U17 U21 DDR3 Device N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 DDR3_A0 DDR3_A1 DDR3_A2 DDR3_A3 DDR3_A4 DDR3_A5 DDR3_A6 DDR3_A7 DDR3_A8 DDR3_A9 DDR3_A10 DDR3_A11 DDR3_A12 DDR3_A13 D DDR3_CKE DDR3_CLK_P DDR3_CLK_N K9 J7 K7 DDR3_DM6 DDR3_DM7 E7 D3 DDR3_CSn DDR3_WEn DDR3_RASn DDR3_CASn L2 L3 J3 K3 DDR3_BA0 DDR3_BA1 DDR3_BA2 DDR3_RESETn DDR3_ODT DDR3_ZQ04 VREF_DDR3 M2 N8 M3 T2 K1 L8 C H1 M8 R270 C521 0.1uF 240 B B2 D9 G7 K2 K8 N1 N9 R1 R9 1.5V A1 A8 C1 C9 D2 E9 F1 H2 H9 1.5V A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BCn A13 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CKE CK_P CK_N DQS_P0 DQS_N0 DQS_P1 DQS_N1 DM0 DM1 CS WE RAS CAS NC1 NC2 NC3 NC4 NC5 NC6 BA0 BA1 BA2 RESETn ODT ZQ VREFDQ VREFCA VDD VDD VDD VDD VDD VDD VDD VDD VDD VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ U23 DDR3 Device E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DDR3_DQ48 DDR3_DQ49 DDR3_DQ50 DDR3_DQ51 DDR3_DQ52 DDR3_DQ53 DDR3_DQ54 DDR3_DQ55 DDR3_DQ56 DDR3_DQ57 DDR3_DQ58 DDR3_DQ59 DDR3_DQ60 DDR3_DQ61 DDR3_DQ62 DDR3_DQ63 F3 G3 C7 B7 DDR3_DQS_P6 DDR3_DQS_N6 DDR3_DQS_P7 DDR3_DQS_N7 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 DDR3_A0 DDR3_A1 DDR3_A2 DDR3_A3 DDR3_A4 DDR3_A5 DDR3_A6 DDR3_A7 DDR3_A8 DDR3_A9 DDR3_A10 DDR3_A11 DDR3_A12 DDR3_A13 J1 J9 L1 L9 M7 T7 B1 B9 D1 D8 E2 E8 F9 G1 G9 DDR3_CKE DDR3_CLK_P DDR3_CLK_N K9 J7 K7 DDR3_DM4 DDR3_DM5 E7 D3 DDR3_CSn DDR3_WEn DDR3_RASn DDR3_CASn L2 L3 J3 K3 DDR3_BA0 DDR3_BA1 DDR3_BA2 DDR3_RESETn DDR3_ODT DDR3_ZQ03 VREF_DDR3 M2 N8 M3 T2 K1 L8 H1 M8 R301 C351 B2 D9 G7 K2 K8 N1 N9 R1 R9 0.1uF 240 J2 J8 A9 M1 M9 B3 P1 P9 E1 T1 T9 G8 1.5V A1 A8 C1 C9 D2 E9 F1 H2 H9 MT41J128M16HA A 3 VTT_DDR3 DDR3_DM[8:0] 14,7 4 512MB DDR3 (x72 devices) - Part 1 of 2 DDR3_CLK_N R207 DDR3_BA[2:0] 14,7 5 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BCn A13 CKE CK_P CK_N DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS_P0 DQS_N0 DQS_P1 DQS_N1 DM0 DM1 CS WE RAS CAS BA0 BA1 BA2 RESETn ODT ZQ VREFDQ VREFCA VDD VDD VDD VDD VDD VDD VDD VDD VDD NC1 NC2 NC3 NC4 NC5 NC6 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ U28 DDR3 Device E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DDR3_DQ32 DDR3_DQ33 DDR3_DQ34 DDR3_DQ35 DDR3_DQ36 DDR3_DQ37 DDR3_DQ38 DDR3_DQ39 DDR3_DQ40 DDR3_DQ41 DDR3_DQ42 DDR3_DQ43 DDR3_DQ44 DDR3_DQ45 DDR3_DQ46 DDR3_DQ47 F3 G3 C7 B7 DDR3_DQS_P4 DDR3_DQS_N4 DDR3_DQS_P5 DDR3_DQS_N5 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 DDR3_A0 DDR3_A1 DDR3_A2 DDR3_A3 DDR3_A4 DDR3_A5 DDR3_A6 DDR3_A7 DDR3_A8 DDR3_A9 DDR3_A10 DDR3_A11 DDR3_A12 DDR3_A13 J1 J9 L1 L9 M7 T7 B1 B9 D1 D8 E2 E8 F9 G1 G9 DDR3_CKE DDR3_CLK_P DDR3_CLK_N K9 J7 K7 DDR3_DM2 DDR3_DM3 E7 D3 DDR3_CSn DDR3_WEn DDR3_RASn DDR3_CASn L2 L3 J3 K3 DDR3_BA0 DDR3_BA1 DDR3_BA2 DDR3_RESETn DDR3_ODT DDR3_ZQ02 VREF_DDR3 M2 N8 M3 T2 K1 L8 H1 M8 R340 C468 0.1uF 240 J2 J8 A9 M1 M9 B3 P1 P9 E1 T1 T9 G8 B2 D9 G7 K2 K8 N1 N9 R1 R9 1.5V A1 A8 C1 C9 D2 E9 F1 H2 H9 MT41J128M16HA A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BCn A13 CKE CK_P CK_N DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS_P0 DQS_N0 DQS_P1 DQS_N1 DM0 DM1 CS WE RAS CAS BA0 BA1 BA2 RESETn ODT ZQ VREFDQ VREFCA VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ NC1 NC2 NC3 NC4 NC5 NC6 DDR3 Device E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DDR3_DQ16 DDR3_DQ17 DDR3_DQ18 DDR3_DQ19 DDR3_DQ20 DDR3_DQ21 DDR3_DQ22 DDR3_DQ23 DDR3_DQ24 DDR3_DQ25 DDR3_DQ26 DDR3_DQ27 DDR3_DQ28 DDR3_DQ29 DDR3_DQ30 DDR3_DQ31 F3 G3 C7 B7 DDR3_DQS_P2 DDR3_DQS_N2 DDR3_DQS_P3 DDR3_DQS_N3 DDR3_A0 DDR3_A1 DDR3_A2 DDR3_A3 DDR3_A4 DDR3_A5 DDR3_A6 DDR3_A7 DDR3_A8 DDR3_A9 DDR3_A10 DDR3_A11 DDR3_A12 DDR3_A13 14,7 14,7 14,7 14,7 14,7 14,7 14,7 J1 J9 L1 L9 M7 T7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DDR3_CKE DDR3_CLK_P DDR3_CLK_N K9 J7 K7 DDR3_DM0 DDR3_DM1 E7 D3 DDR3_CSn DDR3_WEn DDR3_RASn DDR3_CASn L2 L3 J3 K3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BCn A13 CKE CK_P CK_N DM0 DM1 CS WE RAS CAS M2 DDR3_BA0 N8 DDR3_BA1 M3 DDR3_BA2 DDR3_RESETn T2 DDR3_ODT K1 L8 DDR3_ZQ01 VREF_DDR3 H1 R376 M8 C563 B2 0.1uF D9 G7 240 K2 K8 N1 N9 R1 R9 1.5V A1 A8 C1 C9 D2 E9 F1 H2 H9 14,7 14,7 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 B1 B9 D1 D8 E2 E8 F9 G1 G9 J2 J8 A9 M1 M9 B3 P1 P9 E1 T1 T9 G8 MT41J128M16HA BA0 BA1 BA2 RESETn ODT ZQ VREFDQ VREFCA VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS_P0 DQS_N0 DQS_P1 DQS_N1 NC1 NC2 NC3 NC4 NC5 NC6 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DDR3_DQ0 DDR3_DQ1 DDR3_DQ2 DDR3_DQ3 DDR3_DQ4 DDR3_DQ5 DDR3_DQ6 DDR3_DQ7 DDR3_DQ8 DDR3_DQ9 DDR3_DQ10 DDR3_DQ11 DDR3_DQ12 DDR3_DQ13 DDR3_DQ14 DDR3_DQ15 F3 G3 C7 B7 DDR3_DQS_P0 DDR3_DQS_N0 DDR3_DQS_P1 DDR3_DQS_N1 D J1 J9 L1 L9 M7 T7 C B1 B9 D1 D8 E2 E8 F9 G1 G9 B J2 J8 A9 M1 M9 B3 P1 P9 E1 T1 T9 G8 MT41J128M16HA C418 C420 C467 C469 C466 C562 C561 C551 C545 C350 C369 C312 C310 C494 C520 C528 C498 C479 C370 C496 C419 C522 C499 C519 C281 C352 C559 C543 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 2.2nF 3.3nF 3.3nF 4.7nF 4.7nF 4.7nF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 1.5V Title C400 C464 C470 C401 C465 C527 C493 C349 C308 C547 C564 C404 C402 C405 C495 C529 C309 C368 C560 C544 Size 0.01uF 0.01uF 0.01uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.47uF 0.47uF 0.47uF 0.47uF 0.47uF 0.47uF 0.47uF 0.47uF B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 13 of 1 34 D1.1 8 7 6 5 4 3 2 1 1152MB DDR3 - Part 2 of 2 DDR3_BA[2:0] 13,7 DDR3_DM[8:0] E DDR3 Device DDR3_A0 DDR3_A1 DDR3_A2 DDR3_A3 DDR3_A4 DDR3_A5 DDR3_A6 DDR3_A7 DDR3_A8 DDR3_A9 DDR3_A10 DDR3_A11 DDR3_A12 DDR3_A13 K3 L7 L3 K2 L8 L2 M8 M2 N8 M3 H7 M7 K7 N3 DDR3_CKE DDR3_CLK_P DDR3_CLK_N G9 F7 G7 DDR3_DM8 DDR3_DQS_P8 DDR3_DQS_N8 B7 A7 C3 D3 13,7 13,7 13,7 13,7 DDR3_CSn DDR3_WEn DDR3_RASn DDR3_CASn H2 H3 F3 G3 13,7 13,7 DDR3_BA0 DDR3_BA1 DDR3_BA2 DDR3_RESETn DDR3_ODT J2 K8 J3 N2 G1 DDR3_ZQ05 1.5V R214 H8 13,7 13,7 13,7 D C 13,7 DDR3_DQS_P[8:0] U12 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BCn A13 DQ0 DQ1 DQ2 DQ3 NF/DQ4 NF/DQ5 NF/DQ6 NF/DQ7 NC1 NC2 NC3 NC4 NC5 NC6 NC7 CKE CK_P CK_N B3 C7 C2 C8 E3 E8 D2 E7 13,7 DDR3_DQS_N[8:0] DDR3_DQ64 DDR3_DQ65 DDR3_DQ66 DDR3_DQ67 DDR3_DQ68 DDR3_DQ69 DDR3_DQ70 DDR3_DQ71 E 13,7 DDR3_DQ[71:0] 13,7 DDR3_A[13:0] 13,7 A3 F1 F9 H1 H9 J7 N7 D DM/TDQS_P NF/TDQS_N DQS_P DQS_N CS WE RAS CAS BA0 BA1 BA2 RESETn ODT ZQ E9 E2 B9 C1 VDDQ VDDQ VDDQ VDDQ 240 M9 M1 K9 K1 G8 G2 D7 A9 A2 VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9 B2 B8 C9 D1 D9 C VREF_DDR3 VREFCA VREFDQ J8 E1 C253 MT41J128M8JP 0.1uF B B Place near DDR3 (U?) 1.5V C237 C252 C250 C330 C251 C254 C224 C208 C225 C210 C255 C209 0.47uF 0.47uF 0.47uF 0.47uF 0.47uF 0.47uF 0.1uF 0.01uF 0.1uF 0.01uF 0.01uF 4.7nF A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 14 of 1 34 D1.1 8 7 6 5 3 QDRII+ QDRII_A[20:0] 5 4 QDRII_Q[17:0] QDRII_D[17:0] 5 U5A P10 N11 M11 K10 J11 G11 E10 D11 C11 B3 C3 D2 F3 G2 J3 L3 M3 N2 N10 M9 L9 J9 G10 F9 D10 C9 B9 C1 D1 E2 G1 J1 K2 M1 N1 P2 P9 QDRII_D0 QDRII_D1 QDRII_D2 QDRII_D3 QDRII_D4 QDRII_D5 QDRII_D6 QDRII_D7 QDRII_D8 QDRII_D9 QDRII_D10 QDRII_D11 QDRII_D12 QDRII_D13 QDRII_D14 QDRII_D15 QDRII_D16 QDRII_D17 D C QDRII+ QVLD = QDRII C_P QDRII+ ODT = QDRII C_N B 1 Altera recommends to use external termination for QDRII/+ address and command signals. In this case external termination was not used, because simulations showed that with the short trace length and a point to point connection the external termination was not necessary. As a result since there is limited board space external termination is not used. 5 E 2 5 5 QDRII_BWSn0 QDRII_BWSn1 B7 A5 5 5 QDRII_WPSn QDRII_RPSn A4 A8 5 5 QDRII_K_P QDRII_K_N B6 A6 5 5 QDRII_C_P QDRII_C_N P6 R6 5 5 QDRII_CQ_P QDRII_CQ_N A11 A1 5 QDRII_DOFFn H1 10.0K R181 R180 249 H11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 NC20 NC21 NC22 NC23 NC24 NC25 NC26 NC27 NC28 NC29 NC30 NC31 NC32 NC33 NC34 NC35 NC36 NC37 NC38 BWS0 BWS1 WPS RPS K_P K_N QVLD ODT CQ_P CQ_N DOFF TMS TDI TDO TCK JTAG R10 R11 R1 R2 1.8V 1.8V A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 NC/72M NC/144M NC/288M VREF VREF ZQ P11 M10 L11 K11 J10 F11 E11 C10 B11 B2 D3 E3 F2 G3 K3 L2 N3 P3 N9 L10 K9 F10 E9 D9 B10 B1 C2 E1 F1 J2 K1 L1 M2 P1 C6 B5 G9 E U5B F5 F7 G5 G7 H5 H7 J5 J7 K5 K7 QDRII_Q0 QDRII_Q1 QDRII_Q2 QDRII_Q3 QDRII_Q4 QDRII_Q5 QDRII_Q6 QDRII_Q7 QDRII_Q8 QDRII_Q9 QDRII_Q10 QDRII_Q11 QDRII_Q12 QDRII_Q13 QDRII_Q14 QDRII_Q15 QDRII_Q16 QDRII_Q17 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 1.8V E4 E8 F4 F8 L8 G4 G8 H3 H4 H8 H9 J4 J8 K4 K8 L4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ C4 C8 D4 D5 D6 D7 D8 E5 E6 E7 F6 G6 H6 J6 K6 L5 L6 L7 M4 M5 M6 M7 M8 N4 N8 D CY7C2263KV18 Place Near QDRII+ GND QDRII A21 NC PIN ON QDRII+ QDRII_C_N R9 R8 B4 B8 C5 C7 N5 N6 N7 P4 P5 P7 P8 R3 R4 R5 R7 A9 A3 A10 A2 A7 QDRII_A0 QDRII_A1 QDRII_A2 QDRII_A3 QDRII_A4 QDRII_A5 QDRII_A6 QDRII_A7 QDRII_A8 QDRII_A9 QDRII_A10 QDRII_A11 QDRII_A12 QDRII_A13 QDRII_A14 QDRII_A15 QDRII_A16 QDRII_A17 QDRII_A18 QDRII_A19 QDRII_A20 C 49.9 VDDQ DECOUPLING 1.8V C218 C217 C164 C163 C141 0.1uF 0.01uF 2.2nF 3.3nF 1.0nF B 1.8V H2 H10 R200 VDD DECOUPLING VREF_QDRII_RLD C140 C120 C138 C139 C161 C121 C162 C185 C122 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF 1.0uF C184 C186 C187 C189 C159 C199 C123 C183 2.2nF 3.3nF 4.7nF 4.7nF 4.7nF 22nF 22nF 2.2uF CY7C2263KV18 C104 C160 0.1uF 0.1uF A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 15 of 1 34 D1.1 8 7 6 5 4 3 2 1 RLDRAM II, CIO E J12 K12 RLDC_CK_P RLDC_CK_N K1 K2 RLDC_DK_P RLDC_DK_N D11 D10 RLDC_QK_P0 RLDC_QK_N0 D RLDC_QK_P1 RLDC_QK_N1 R2 R3 RLDC_CSn RLDC_WEn RLDC_REFn L2 M1 L1 RLDC_DM RLDC_QVLD P12 F12 J11 K11 H1 RLDC_BA0 RLDC_BA1 RLDC_BA2 A11 A12 V11 V12 V2 RLDC_ZQ C G12 G11 G10 H12 H11 F1 G2 G3 G1 H2 M12 M11 M10 L12 L11 P1 M2 M3 N1 N12 RLDC_A0 RLDC_A1 RLDC_A2 RLDC_A3 RLDC_A4 RLDC_A5 RLDC_A6 RLDC_A7 RLDC_A8 RLDC_A9 RLDC_A10 RLDC_A11 RLDC_A12 RLDC_A13 RLDC_A14 RLDC_A15 RLDC_A16 RLDC_A17 RLDC_A18 RLDC_A19 U20A RLDRAM II CIO, x18 CK DQ0 CK DQ1 DQ2 DK0 DQ3 DK0 DQ4 DQ5 QK0 DQ6 QK0 DQ7 DQ8 QK1 DQ9 QK1 DQ10 DQ11 CS DQ12 WE DQ13 REF DQ14 DQ15 DM DQ16 QVLD DQ17 B0 B1 B2 DNU1 DNU2 DNU3 DNU4 DNU5 DNU6 DNU7 DNU8 DNU9 DNU10 DNU11 DNU12 DNU13 DNU14 DNU15 DNU16 DNU17 DNU18 DNU19/A20 DNU20/A21 DNU21/A22 TMS TCK TDO TDI ZQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 RLDRAM II INTERFACE 1.8V B10 C10 E10 F10 B3 C3 D3 E3 F3 N10 P10 R10 T10 U10 N3 P3 T3 U3 B11 B2 C2 C11 D2 E2 E11 F2 F11 U2 N2 N11 P2 P11 R11 T2 T11 U11 E12 E1 D1 U20B RLDC_DQ0 RLDC_DQ1 RLDC_DQ2 RLDC_DQ3 RLDC_DQ4 RLDC_DQ5 RLDC_DQ6 RLDC_DQ7 RLDC_DQ8 RLDC_DQ9 RLDC_DQ10 RLDC_DQ11 RLDC_DQ12 RLDC_DQ13 RLDC_DQ14 RLDC_DQ15 RLDC_DQ16 RLDC_DQ17 RLDRAM II CIO, x18 VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS B1 B12 G4 G9 J3 J4 J9 J10 K3 K4 K9 K10 M4 M9 U1 U12 C4 C9 E4 E9 P4 P9 T4 T9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 2.5V A3 A10 V3 V10 VEXT VEXT VEXT VEXT VTT_QDRII_RLD C1 C12 T1 T12 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VTT VTT VTT VTT RLDC_DQ[17:0] A2 A4 A9 D12 H3 H4 H9 H10 L3 L4 L9 L10 R1 R12 V4 V9 RLDC_DQ[17:0] 4 E RLDC_QK_P[1:0] RLDC_QK_P[1:0] 4 RLDC_QK_N[1:0] RLDC_QK_N[1:0] 4 RLDC_A[22:0] RLDC_A[22:0] 4 RLDC_BA[2:0] Altera recommends to use external termination for RLDRAM II address and command signals. In this case external termination was not used, because simulations showed that with the short trace length and a point to point connection the external termination was not necessary. As a result since there is limited board space external termination is not used. B4 B9 D4 D9 F4 F9 N4 N9 R4 R9 U4 U9 RLDC_BA[2:0]4,9 RLDC_CK_P RLDC_CK_N RLDC_CK_P4 RLDC_CK_N 4 RLDC_DK_P RLDC_DK_N RLDC_DK_P4 RLDC_DK_N 4 RLDC_CSn RLDC_WEn RLDC_REFn RLDC_CSn RLDC_DM RLDC_QVLD On-die termination (ODT) is enabled by setting A9 to “1” during an MRS command. RLDC_CSn RLDC_WEn RLDC_REFn RLDC_CSn RLDC_DM RLDC_QVLD 16,4 4 4 16,4 4 4 D VREF_QDRII_RLD VREF VREF A1 V1 MT49H32M18BM RLDC_A20 RLDC_A21 RLDC_A22 C PLACE THESE CAPACITORS AS CLOSE AS POSSIBLE TO THE RLDRAM II VTT_QDRII_RLD NF1 NF2 VREF_QDRII_RLD J1 J2 C474 0.1uF C477 0.1uF C383 0.1uF C472 0.1uF C476 0.1uF C385 0.1uF MT49H32M18BM B B HSTL1 1.8V BYPASS CAPS FOR RLDRAM II CIO 2.5V R289 R288 VTT_QDRII_RLD 1.8V C386 C384 C446 DNI 301 RLDC_ZQ C427 0.1uF 0.1uF 0.1uF R273 R300 RLDC_CK_P RLDC_DK_P C444 C448 PLACE THESE RESISTORS AS CLOSE AS POSSIBLE TO THE RLDRAM II 100, 1% 100, 1% RLDC_CK_N RLDC_DK_N 0.1uF 1uF 100uF Output Impedence Setting MAX Drive 60 Ohms 50 Ohms 1.8V 1.8V A C428 C414 C445 C426 0.33uF 0.33uF 100uF RLDC_ZQ 1.8V 301 Ohm to GND 250 Ohm to GND 1.8V 1uF 1.8V C443 C447 C382 C387 0.1uF 0.1uF 0.1uF 0.1uF Title Size B Date: 8 7 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 16 of 1 34 D1.1 8 7 6 5 4 3 2 1 FLASH FM BUS FM_D[31:0] 18,4 FM_A[26:0] 18,4,5,9 E E 3.3V FLASH 512Mb (32M X 16) R125 R120 R126 R118 R347 R119 D DNI DNI DNI DNI DNI DNI FPGA_AS_DATA0 FPGA_AS_DATA1 FPGA_AS_DATA2 FPGA_AS_DATA3 FPGA_DCLK FPGA_nCSO U11 FM_A1 FM_A2 FM_A3 FM_A4 FM_A5 FM_A6 FM_A7 FM_A8 FM_A9 FM_A10 FM_A11 FM_A12 FM_A13 FM_A14 FM_A15 FM_A16 FM_A17 FM_A18 FM_A19 FM_A20 FM_A21 FM_A22 FM_A23 FM_A24 FM_A25 FM_A26 U53 FPGA_DCLK FPGA_nCSO 11,18 11 6 1 4 VCC DQ0 CLK DQ1 CSn W#/VPP/DQ2 HOLD#/DQ3 GND TAB_DNC 5 2 3 7 9 FPGA_AS_DATA0 FPGA_AS_DATA1 FPGA_AS_DATA2 FPGA_AS_DATA3 11 11 11 11 N25Q256A 3.3V C C63 C62 0.1uF 0.1uF 1.8V PC28FxxxP30B85 FLASH 3.3V 8 FLASH 512Mb (32M X 16) A1 B1 C1 D1 D2 A2 C2 A3 B3 C3 D3 C4 A5 B5 C5 D7 D8 A7 B7 C7 C8 A8 G1 H8 B6 B8 E6 FLASH_CLK FLASH_RESETn FLASH_CEn1 FLASH_OEn FLASH_WEn FLASH_ADVn FLASH_WPn 18,5 D4 B4 F8 G8 F6 C6 VPP A1 A2 VCC A3 VCC A4 A5 VCCQ A6 VCCQ A7 VCCQ A8 A9 D0 A10 D1 A11 D2 A12 D3 A13 D4 A14 D5 A15 D6 A16 D7 A17 A18 D8 A19 D9 A20 D10 A21 D11 A22 D12 NC(64M)/A23 D13 NC(64M,128M)/A24 D14 NC/A25(512M) D15 NC/A26(1G) WAIT CLK GND RESET# GND CE# GND OE# GND WE# ADV# RFU0 WP# RFU1 RFU2 RFU3 U10 A4 A6 H3 FM_A1 FM_A2 FM_A3 FM_A4 FM_A5 FM_A6 FM_A7 FM_A8 FM_A9 FM_A10 FM_A11 FM_A12 FM_A13 FM_A14 FM_A15 FM_A16 FM_A17 FM_A18 FM_A19 FM_A20 FM_A21 FM_A22 FM_A23 FM_A24 FM_A25 FM_A26 1.8V D5 D6 G4 F2 E2 G3 E4 E5 G5 G6 H7 FM_D16 FM_D17 FM_D18 FM_D19 FM_D20 FM_D21 FM_D22 FM_D23 E1 E3 F3 F4 F5 H5 G7 E7 FM_D24 FM_D25 FM_D26 FM_D27 FM_D28 FM_D29 FM_D30 FM_D31 F7 FLASH_RDYBSYn1 18,9 B2 H2 H4 H6 H1 G2 F1 E8 A1 B1 C1 D1 D2 A2 C2 A3 B3 C3 D3 C4 A5 B5 C5 D7 D8 A7 B7 C7 C8 A8 G1 H8 B6 B8 E6 18,5 FLASH_CLK 18,5 18,5 18,5 18,5 18,9 FLASH_RESETn FLASH_CEn0 FLASH_OEn FLASH_WEn FLASH_ADVn FLASH_WPn D4 B4 F8 G8 F6 C6 PC28F512P30BF 1.8V B 1.8V PC28FxxxP30B85 FLASH VPP A1 A2 VCC A3 VCC A4 A5 VCCQ A6 VCCQ A7 VCCQ A8 A9 D0 A10 D1 A11 D2 A12 D3 A13 D4 A14 D5 A15 D6 A16 D7 A17 A18 D8 A19 D9 A20 D10 A21 D11 A22 D12 NC(64M)/A23 D13 NC(64M,128M)/A24 D14 NC/A25(512M) D15 NC/A26(1G) WAIT CLK GND RESET# GND CE# GND OE# GND WE# ADV# RFU0 WP# RFU1 RFU2 RFU3 A4 A6 H3 1.8V D5 D6 G4 F2 E2 G3 E4 E5 G5 G6 H7 FM_D0 FM_D1 FM_D2 FM_D3 FM_D4 FM_D5 FM_D6 FM_D7 E1 E3 F3 F4 F5 H5 G7 E7 FM_D8 FM_D9 FM_D10 FM_D11 FM_D12 FM_D13 FM_D14 FM_D15 F7 D FLASH_RDYBSYn0 18,5 C B2 H2 H4 H6 H1 G2 F1 E8 PC28F512P30BF 1.8V 1.8V 1.8V C233 C300 C299 C298 C297 C245 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R216 R227 R228 R217 10K 10K 10K 10K FLASH_WPn FLASH_WEn FLASH_RDYBSYn0 FLASH_RDYBSYn1 R212 10K FLASH_RESETn 1.8V B C234 C304 C302 C301 C303 C246 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF - When using a single x16 flash device a word consists of 16 data bits so addressing starts with FM_A1 mapped to address bit 1 in software. - When using dual x16 flash devices for an equivalent x32 (x16||x16) flash device a word consists of 32 data bits so addressing starts with FM_A1 mapped to address bit 2 in software. A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 17 of 1 34 D1.1 8 7 6 5 4 3 5M2210 System Controller U4A E D FPGA_CONFIG_D0 FPGA_CONFIG_D1 FPGA_CONFIG_D2 FPGA_CONFIG_D3 FPGA_CONFIG_D4 FPGA_CONFIG_D5 FPGA_CONFIG_D6 FPGA_CONFIG_D7 D3 C2 C3 E3 D2 E4 D1 E5 FPGA_CONFIG_D8 FPGA_CONFIG_D9 FPGA_CONFIG_D10 FPGA_CONFIG_D11 FPGA_CONFIG_D12 FPGA_CONFIG_D13 FPGA_CONFIG_D14 FPGA_CONFIG_D15 F3 E1 F4 F2 F1 F6 G2 G3 FPGA_CONFIG_D16 FPGA_CONFIG_D17 FPGA_CONFIG_D18 FPGA_CONFIG_D19 FPGA_CONFIG_D20 FPGA_CONFIG_D21 FPGA_CONFIG_D23 FPGA_CONFIG_D22 G1 G4 H2 G5 H3 J1 H4 J2 H5 J5 USB_CLK CLK_CONFIG 2 FM_D[31:0] FPGA_CONFIG_D[31:0] 11 U4B MAX V BANK1 DIFFIO_L1P DIFFIO_L1N DIFFIO_L2P DIFFIO_L2N DIFFIO_L3P DIFFIO_L3N DIFFIO_L4P DIFFIO_L4N DIFFIO_L13P DIFFIO_L13N DIFFIO_L14P DIFFIO_L14N DIFFIO_L15P DIFFIO_L15N DIFFIO_L16P DIFFIO_L16N DIFFIO_L5P DIFFIO_L5N DIFFIO_L6P DIFFIO_L6N DIFFIO_L7P DIFFIO_L7N DIFFIO_L8P DIFFIO_L8N DIFFIO_L17P DIFFIO_L17N DIFFIO_L18P DIFFIO_L18N DIFFIO_L19P DIFFIO_L19N DIFFIO_L20P DIFFIO_L20N DIFFIO_L9P DIFFIO_L21P DIFFIO_L9N DIFFIO_L21N DIFFIO_L10P DIFFIO_L10N IOB1_1 DIFFIO_L11P IOB1_2 DIFFIO_L11N IOB1_3 DIFFIO_L12P IOB1_4 DIFFIO_L12N IOB1_5 IOB1/CLK0 IOB1/CLK1 J4 K1 J3 K2 K5 L1 L2 K3 FPGA_nSTATUS FPGA_CONF_DONE FPGA_DCLK FPGA_CONFIG_D24 FPGA_CONFIG_D25 FPGA_CONFIG_D26 FPGA_CONFIG_D27 FPGA_CONFIG_D28 SI571_EN TSENSE_ALERTn D4 B1 C5 C4 B4 D6 E6 B5 M1 M2 L4 L3 N1 M4 N2 M3 EXTRA_SIG0 FPGA_CONFIG_D29 FPGA_CONFIG_D30 FPGA_CONFIG_D31 FPGA_nCONFIG SENSE_SCK SENSE_SDI SENSE_SDO SENSE_CS0n OVERTEMPn OVERTEMP SENSE_SMB_CLK SENSE_SMB_DATA A5 D7 B6 E7 C8 B7 D8 A7 B8 A8 A9 E9 B9 D9 A10 C9 VCCINT_SCL VCCINT_SDA N3 P2 FPGA_CvP_CONFDONE FPGA_PR_ERROR HSMA_PRSNTn HSMB_PRSNTn E2 F5 H1 K4 L5 FPGA_PR_READY FPGA_PR_REQUEST FPGA_PR_DONE CLK50_EN CLK125_EN CLOCK_SDA Si570_EN CLOCK_SCL P3 L6 M5 N4 TCK TDI TDO TMS JTAG_TCK JTAG_5M2210_TDI JTAG_5M2210_TDO 5M2210_JTAG_TMS MAX V BANK2 DIFFIO_T1P DIFFIO_T1N DIFFIO_T2P DIFFIO_T2N DIFFIO_T3P DIFFIO_T3N DIFFIO_T4P DIFFIO_T4N DIFFIO_T13P DIFFIO_T13N DIFFIO_T14P DIFFIO_T14N DIFFIO_T15P DIFFIO_T15N DIFFIO_T16P DIFFIO_T16N DIFFIO_T5P DIFFIO_T5N DIFFIO_T6P DIFFIO_T6N DIFFIO_T7P DIFFIO_T7N DIFFIO_T8P DIFFIO_T8N DIFFIO_T17P DIFFIO_T17N DIFFIO_T18P DIFFIO_T18N IOB2_6 IOB2_7 DIFFIO_T9P DIFFIO_T9N DIFFIO_T10P DIFFIO_T10N DIFFIO_T11P DIFFIO_T11N DIFFIO_T12P DIFFIO_T12N IOB2_8 IOB2_9 IOB2_10 IOB2_11 IOB2_12 IOB2_13 IOB2_14 IOB2_15 IOB2_16 IOB2_17 IOB2_18 IOB2_19 IOB2_20 11,12,22,25 12 12 12 E10 A11 B11 A12 E11 B12 C11 B13 D12 B14 C13 B16 MAX_CONF_DONE PGM_SEL FPGA_nSTATUS FPGA_CONF_DONE FPGA_DCLK FPGA_nCONFIG 11 11 11,17 11 FPGA_PR_DONE FPGA_PR_REQUEST FPGA_PR_READY FPGA_PR_ERROR FPGA_CvP_CONFDONE 11 11 11 11 11 SENSE_SDO SENSE_SDI SENSE_SCK SENSE_CS0n 31 31 31 31 TSENSE_ALERTn OVERTEMPn OVERTEMP SENSE_SMB_CLK SENSE_SMB_DATA 31 24,31 31 31 31 PGM_CONFIG PGM_LED0 PGM_LED1 PGM_LED2 A13 CLK_SEL A15 CLK_ENABLE A2 FACTORY_LOAD A4 MAX_ERROR A6 MAX_LOAD B10 MSEL0 B3 MSEL1 C10 MSEL2 C12 MSEL3 C6 MSEL4 SDI_TX_EN SDI_RX_BYPASS SDI_RX_EN 21,4 21,9 11,21 C E14 C14 C15 E13 E12 D15 F14 D16 FM_A0 FM_A1 FM_A2 FM_A3 FM_A4 FM_A5 FM_A6 FM_A7 VCCINT_SCL VCCINT_SDA PCIE_JTAG_EN CPU_RESETn SDI_TX_EN SDI_RX_BYPASS SDI_RX_EN 27 27 B FM_A8 FM_A9 FM_A10 FM_A11 FM_A12 FM_A13 FM_A14 FM_A15 F13 E15 E16 F15 G14 F16 G13 G15 FM_A16 FM_A17 FM_A18 FM_A19 FM_A20 FM_A21 FM_A22 FM_D23 G12 G16 H14 H15 H13 H16 J13 J16 J12 H12 CLKIN_50 DIFFIO_R1P DIFFIO_R1N DIFFIO_R2P DIFFIO_R2N DIFFIO_R3P DIFFIO_R3N DIFFIO_R4P DIFFIO_R4N DIFFIO_R13P DIFFIO_R13N DIFFIO_R14P DIFFIO_R14N DIFFIO_R15P DIFFIO_R15N DIFFIO_R16P DIFFIO_R16N DIFFIO_R5P DIFFIO_R5N DIFFIO_R6P DIFFIO_R6N DIFFIO_R7P DIFFIO_R7N DIFFIO_R8P DIFFIO_R8N DIFFIO_R17P DIFFIO_R17N DIFFIO_R18P DIFFIO_R18N DIFFIO_R19P DIFFIO_R19N DIFFIO_R20P DIFFIO_R20N DIFFIO_R9P DIFFIO_R9N DIFFIO_R10P DIFFIO_R10N DIFFIO_R11P DIFFIO_R11N DIFFIO_R12P DIFFIO_R12N IOB3/CLK2 IOB3/CLK3 U4E MAX V BANK4 DIFFIO_R21P DIFFIO_R21N DIFFIO_R22P DIFFIO_R22N IOB3_21 IOB3_22 IOB3_23 IOB3_24 IOB3_25 IOB3_26 IOB3_27 FM_D0 FM_D1 FM_D2 FM_D3 FM_D4 FM_D5 FM_D6 FM_D7 FM_D28 FM_D29 FM_A25 FM_A24 FM_A23 FM_D30 FM_D31 FLASH_WEn L15 L12 M16 L13 M15 L14 N16 M13 FM_D8 FM_D9 FM_D10 FM_D11 FM_D12 FM_D13 FM_D14 FM_D15 N15 N14 P15 P14 FM_D16 FM_D17 FM_D18 FM_D19 D13 D14 F11 FM_D20 FM_D21 FM_D22 F12 K12 M14 N13 FM_D24 FM_D25 FM_D26 FM_D27 FLASH_CEn0 FLASH_OEn FLASH_RDYBSYn0 FLASH_RESETn FLASH_CLK FLASH_ADVn FLASH_CEn1 FLASH_RDYBSYn1 USB_CFG2 USB_CFG3 USB_CFG4 USB_CFG5 USB_CFG6 USB_CFG7 USB_CFG8 USB_CFG9 MAX_RESETn USB_CFG10 R1 P4 T2 P5 R3 N5 P6 N6 R5 M6 T5 P7 R6 N7 M7 R7 P8 T7 N8 R8 T8 T9 R9 P9 M9 M8 DIFFIO_B1P DIFFIO_B1N DIFFIO_B2P DIFFIO_B2N DIFFIO_B3P DIFFIO_B3N DIFFIO_B4P DIFFIO_B4N DIFFIO_B14P DIFFIO_B14N DIFFIO_B15P DIFFIO_B15N DIFFIO_B16P DIFFIO_B16N DIFFIO_B17P DIFFIO_B17N DIFFIO_B5P DIFFIO_B5N DIFFIO_B6P DIFFIO_B6N DIFFIO_B7P DIFFIO_B7N DIFFIO_B8P DIFFIO_B8N DIFFIO_B19P DIFFIO_B19N DIFFIO_B18P DIFFIO_B18N DIFFIO_B20P DIFFIO_B20N DIFFIO_B21P DIFFIO_B21N DIFFIO_B9P DIFFIO_B22P DIFFIO_B9N DIFFIO_B22N DIFFIO_B10P IOB4_28 DIFFIO_B10N IOB4_29 DIFFIO_B11P IOB4_30 DIFFIO_B11N IOB4_31 DIFFIO_B12P IOB4_32 DIFFIO_B12N IOB4_33 M10 R10 N10 T11 P10 R11 T12 N11 T13 R13 R12 P11 N12 R14 P12 T15 R16 P13 M11 M12 N9 R4 T10 T4 DIFFIO_B13N/DEV_CLRn DIFFIO_B13P/DEV_OE F7 G6 H7 H9 J10 J8 K11 L10 MAX5_OEn MAX5_CSn MAX5_WEn MAX5_CLK MAX5_BEn0 MAX5_BEn1 MAX5_BEn2 MAX5_BEn3 SECURITY_MODE M570_CLOCK FACTORY_STATUS FACTORY_REQUEST M570_PCIE_JTAG_EN EXTRA_SIG2 USB_CFG0 USB_CFG11 USB_CFG1 2 1.8V 2.5V VCCIO C200 C190 C107 C147 C142 C165 C168 C146 C126 C108 C191 C109 C125 C167 C166 C143 C124 C144 C145 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF GNDINT GNDINT GNDINT GNDINT GNDINT GNDINT GNDINT GNDINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 F10 G11 H10 H8 J7 J9 K6 L7 7 7 7 7 9 22,24,5 22,24,5 11,24 10,9 USB_CFG[11:0] USB_CFG[11:0] EXTRA_SIG[2:0] EN GND VCC USB_CLK PCIE_JTAG_EN M570_PCIE_JTAG_EN M570_CLOCK FACTORY_STATUS FACTORY_REQUEST 25,9 12 25 25 25 25 MAXV DIPSWITCH CLK_SEL CLK_ENABLE FACTORY_LOAD SECURITY_MODE 1.8V C16 H11 J11 P16 10,24 24 24 24 OUT B PUSH BUTTON INTERFACE PGM_SEL PGM_CONFIG MAX_RESETn L8 L9 T14 T3 PGM_SEL PGM_CONFIG MAX_RESETn 24 24 24 PGM_LED[2:0] 24 LED INTERFACE PGM_LED[2:0] MAX_ERROR MAX_LOAD MAX_CONF_DONE 4 3 25 EXTRA_SIG[2:0] 25 2.5V C1 H6 J6 P1 A14 A3 F8 F9 D ON-BOARD USB BLASTER II 24 MAX_ERROR 24 MAX_LOAD MAX_CONF_DONE 24 CLK_CONFIG C96 C92 2.2uF 0.1uF Title Date: 5 4 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 B 6 11 11 11 11 11 C Size 7 MSEL0 MSEL1 MSEL2 MSEL3 MSEL4 E 1.8V VCCIO C201 8 10 10 10 10 10 10 CPU_RESETn CLKIN_50 1.8V MAX V Power X2 2.5V CLK125_EN CLK50_EN Si570_EN SI571_EN CLOCK_SDA CLOCK_SCL MAX5_OEn MAX5_CSn MAX5_WEn MAX5_CLK 2.5V 1 5M2210ZF256 VCCINT 17,5 17,5 17,5 17,5 17,5 17,9 17,5 17,5 17,9 5M2210ZF256 2.5V 100MHz 1.8V A1 A16 B15 B2 G10 G7 G8 G9 K10 K7 K8 K9 R15 R2 T1 T16 T6 EXTRA_SIG1 5M2210ZF256 A FLASH_WEn FLASH_CEn0 FLASH_CEn1 FLASH_OEn FLASH_RDYBSYn0 FLASH_RDYBSYn1 FLASH_RESETn FLASH_CLK FLASH_ADVn HSMA_PRSNTn HSMB_PRSNTn U4D J14 J15 K16 K13 K15 K14 L16 L11 17,4,5,9 MAX5_BEn[3:0] C7 D10 D11 D5 E8 5M2210ZF256 MAX V BANK3 17,4 FM_A[26:0] 5M2210ZF256 U4C 1 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 18 of 1 34 D1.1 5 4 3 2 1 Quad Small Form-factor Pluggable (QSFP) Interface 3.3V QSFP INTERFACE QSFP_VCCT D L15 1.0uH QSFP_RX_P[3..0] QSFP_RX_P[3..0] 8 QSFP_RX_N[3..0] QSFP_RX_N[3..0] 8 QSFP_TX_P[3..0] QSFP_TX_P[3..0] 8 QSFP_TX_N[3..0] QSFP_TX_N[3..0] 8 QSFP_VCCT C553 C557 C507 C558 0.1uF 22uF 0.1uF D 22uF L14 QSFP_VCCR 1.0uH QSFP_VCCR C552 C550 0.1uF 22uF QSFP_VCC QSFP_VCCR QSFP_VCCT QSFP_VCC L10 1.0uH C525 0.1uF 22uF C QSFP_TX_P0 QSFP_TX_N0 36 37 QSFP_TX_P1 QSFP_TX_N1 3 2 QSFP_TX_P2 QSFP_TX_N2 33 34 QSFP_TX_P3 QSFP_TX_N3 6 5 QSFP_MOD_SELn 8 QSFP_LP_MODE 31 QSFP_RSTn 9 QSFP_SCL QSFP_SDA 11 12 39 40 41 42 43 44 2.5V B QSFP_MOD_SELn QSFP_RSTn QSFP_SCL QSFP_SDA QSFP_LP_MODE QSFP_INTERRUPTn QSFP_MOD_PRSn R353 R354 R368 R372 R336 R367 R373 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K QSFP_INTERRUPTn QSFP_MOD_PRSn VCC VCCR VCCT TD1_P TD1_N RD1_P RD1_N TD2_P TD2_N RD2_P RD2_N TD3_P TD3_N RD3_P RD3_N TD4_P TD4_N RD4_P RD4_N MOD_SELn INTn MOD_PRSn LP_MODE GND GND GND GND GND GND GND GND GND GND GND GND RSTn SCL SDA CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND CAGE_GND 17 18 QSFP_RX_P0 QSFP_RX_N0 22 21 QSFP_RX_P1 QSFP_RX_N1 14 15 QSFP_RX_P2 QSFP_RX_N2 25 24 QSFP_RX_P3 QSFP_RX_N3 28 27 QSFP_LP_MODE 4 9 9 9 QSFP_MOD_SELn QSFP_RSTn QSFP_SCL QSFP_SDA J12 30 10 29 QSFP_VCC C532 QSFP_MOD_SELn QSFP_RSTn QSFP_SCL QSFP_SDA QSFP_INTERRUPTn 4 4 QSFP_MOD_PRSn 4 QSFP_LP_MODE C QSFP_CAGE1 QSFP_INTERRUPTn QSFP_MOD_PRSn 1 4 7 13 16 19 20 23 26 32 35 38 45 46 47 48 49 50 B QSFP_AND_CAGE GND_CAGE GND_CAGE 10K R111 GND_CAGE A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 5 4 3 2 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 Rev (6XX-44143R) Sheet 1 19 of 34 D1.1 8 7 6 5 4 3 2 1 Display Port (x4) UNTESTED AND UNPOPULATED. DISPLAYPORT INTERFACE DP_ML_LANE_P[3:0] E DP_ML_LANE_N[3:0] 3.3V 3.3V 5 IO5 IO1 IO2 IO3 IO4 IO1 IO2 IO3 IO4 4 6 IO6 3 7 GND 2 8 VDD 1 5 IO5 4 6 IO6 DNI 3 7 GND DNI 2 3.3V VDD C148 0.1uF 1 D43 8 C110 0.1uF D40 DP_ML_LANE_P[3:0]8 E DP_ML_LANE_N[3:0]8 DP_HOT_PLUG DP_RETURN DP_AUX_P DP_AUX_N DP_HOT_PLUG6 DP_RETURN 6 DP_AUX_P 6 DP_AUX_N 6 DP_DIRECTION DP_DIRECTION6 DP_AUX_TX_P DP_AUX_TX_N DP_AUX_TX_P 6 DP_AUX_TX_N 6 J5 D 20 R161 R182 R173 DNI 18 19 DP_HOT_PLUG DP_RETURN 13 14 DNI DNI 2 5 8 11 16 21 22 DP_PWR ML_LANE_0P ML_LANE_0N HP_DETECT RTN ML_LANE_1P ML_LANE_1N CONFIG1 CONFIG2 ML_LANE_2P ML_LANE_2N GND GND GND GND GND ML_LANE_3P ML_LANE_3N MH1 MH2 MH3 MH4 AUX_CH_P AUX_CH_N 1 3 DP_ML_LANE_CP0 DP_ML_LANE_CN0 C91 4 6 DP_ML_LANE_CP1 DP_ML_LANE_CN1 C89 7 9 DP_ML_LANE_CP2 DP_ML_LANE_CN2 C87 10 12 DP_ML_LANE_CP3 DP_ML_LANE_CN3 C85 DNI C90 DNI DNI C88 DP_ML_LANE_P1 DP_ML_LANE_N1 DNI DNI C86 DP_ML_LANE_P2 DP_ML_LANE_N2 DNI DNI C82 15 17 D DP_ML_LANE_P0 DP_ML_LANE_N0 DP_ML_LANE_P3 DP_ML_LANE_N3 DNI DP_AUX_CP DP_AUX_CN 23 24 DNI C C 3.3V DP_AUX_CP C6 DNI 3.3V C115 0.1uF R154 DNI R55 DNI R54 DNI U34 VBIAS_DP C102 DNI C103 DNI 6 7 DP_AUX_CH_P DP_AUX_CH_N VCC A B 3.3V R153 DNI R56 5 R57 DNI DNI GND DE D RE R 8 3 4 DP_DIRECTION DP_AUX_P 2 1 DP_DIRECTION DP_AUX_N DNI B DP_AUX_CN C7 B DNI Used to bypass m-LVDS transceiver DP_AUX_CH_P DP_AUX_CH_N R58 R59 DNI DNI DP_AUX_P DP_AUX_N R209 DNI R208 DNI DP_AUX_TX_N DP_AUX_TX_P A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 20 of 1 34 D1.1 8 7 6 5 4 3 2 1 SDI Cable Driver, Equalizer, and SMB 75 Ohm Impedance 3.3V_SDI E R332 750 L11 1 2 R342 3.3V_SDI SDI_TX_P C510 8 SDI_TX_N 4 SDI_TX_SD_HDn 4.7uF C511 4.7uF SDI_TXCAP_P SDI_TXCAP_N 1 2 SDI_TX_RSET 10 4 SDI_TX_EN D SDO SDO RSTO FAULT RSTI ENABLE SDA SCL R333 49.9 VCC SD/HD RREF 14 15 49.9 Cable Driver SDI SDI 5 6 7 8 R334 C548 4.7uF SDI_TXBNC_P 1 U25 3.3V_SDI 18,4 75 NC5 NC6 9 R341 12 11 75 SDI_TXDRV_P SDI_TXDRV_N 16 13 R344 VEE CENTERPAD J17 BNC 3.3V_SDI 2 3 4 5 8 E 5.6nH 75 3 17 D R343 LMH0303 L12 1 75 C549 4.7uF SDI_TXBNC_N 5.6nH 2 R365 75 C523 3.3V 3.3V_SDI 0.01uF L5 120 Ohm FB C69 C64 C67 C70 0.1uF 0.1uF 220nF 220nF C68 22uF 75 Ohm Impedance C C L13 3.9nH 1 1 J16 BNC 2 C531 SDI_IN_P1 75 5 4 3 2 R366 1uF R346 75 3.3V_SDI U24 C530 2 3 SDI_EQIN_P1 SDI_EQIN_N1 1uF R345 7 15 4 12 3.3V_SDI SDI_RX_CDn B 37.4 R335 10K 18,9 SDI_RX_BYPASS 11,18 SDI_RX_EN 3.3V_SDI 5 6 AEC 1uF C65 R121 14 8 R324 SDI SDI BYPASS CD SPI_EN AUTO_SLEEP VCC1 VCC2 SDO SDO AEC+ AECMUTE MUTEref VEE1 VEE2 DAP 13 16 11 10 SDO_P SDO_N C59 C58 4.7uF 4.7uF SDI_RX_P SDI_RX_N 8 8 B 1 9 17 LMH0384 3.3V_SDI D38 75 0 0 R127 Green_LED A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 21 of 1 34 D1.1 6 5 HSMA_D0 HSMA_D2 HSMA_TX_D_P0 HSMA_TX_D_N0 D HSMA_TX_D_P1 HSMA_TX_D_N1 HSMA_TX_D_P2 HSMA_TX_D_N2 HSMA_TX_D_P3 HSMA_TX_D_N3 HSMA_TX_D_P4 HSMA_TX_D_N4 HSMA_TX_D_P5 HSMA_TX_D_N5 HSMA_TX_D_P6 HSMA_TX_D_N6 C HSMA_TX_D_P7 HSMA_TX_D_N7 HSMA_CLK_OUT_P1 HSMA_CLK_OUT_N1 HSMA_TX_D_P8 HSMA_TX_D_N8 HSMA_TX_D_P9 HSMA_TX_D_N9 HSMA_TX_D_P10 HSMA_TX_D_N10 HSMA_TX_D_P11 HSMA_TX_D_N11 B HSMA_TX_D_P12 HSMA_TX_D_N12 HSMA_TX_D_P13 HSMA_TX_D_N13 HSMA_TX_D_P14 HSMA_TX_D_N14 HSMA_TX_D_P15 HSMA_TX_D_N15 HSMA_TX_D_P16 HSMA_TX_D_N16 12V HSMA_CLK_OUT_P2 HSMA_CLK_OUT_N2 3.3V A C81 C80 10uF 10uF 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 3.3V 47 49 3.3V 53 55 3.3V 59 61 3.3V 65 67 3.3V 71 73 3.3V 77 79 3.3V 83 85 3.3V 89 91 3.3V 95 97 3.3V 101 103 3.3V 107 109 3.3V 113 115 3.3V 119 121 3.3V 125 127 3.3V 131 133 3.3V 137 139 3.3V 143 145 3.3V 149 151 3.3V 155 157 3.3V 3.3V ASP-122953-01 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 BANK 1 42 44 12V 48 50 12V 54 56 12V 60 62 12V 66 68 12V 72 74 12V 78 80 12V 84 86 12V 90 92 12V 96 98 12V BANK 2 A BANK 3 102 104 12V 108 110 12V 114 116 12V 120 122 12V 126 128 12V 132 134 12V 138 140 12V 144 146 12V 150 152 12V 156 158 PSNTn GND_1_1 GND_1_2 GND_1_3 GND_1_4 GND_2_1 GND_2_2 GND_2_3 GND_2_4 GND_3_1 GND_3_2 GND_3_3 GND_3_4 4 11,12,18,25 12 5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 HSMA_RX_P7 4 HSMA_RX_N7 6 HSMA_RX_P6 8 HSMA_RX_N6 10 HSMA_RX_P5 12 HSMA_RX_N5 14 HSMA_RX_P4 16 HSMA_RX_N4 18 HSMA_RX_P3 20 HSMA_RX_N3 22 HSMA_RX_P2 24 HSMA_RX_N2 26 HSMA_RX_P1 28 HSMA_RX_N1 30 HSMA_RX_P0 32 HSMA_RX_N0 34 HSMA_SCL 36 HSMA_JTAG_TMS 38 JTAG_FPGA_TDO_RETIMER 40 HSMA_CLK_IN0 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 HSMA_D1 HSMA_D3 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 HSMA_RX_D_P8 HSMA_RX_D_N8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 4 4 12 12,25 9 12 9 HSMB_WEn HSMB_ADDR_CMD0 HSMB_DQ0 HSMB_DQ1 HSMA_RX_D_P0 HSMA_RX_D_N0 HSMB_DQ2 HSMB_DQ3 HSMA_RX_D_P1 HSMA_RX_D_N1 HSMB_DQ4 HSMB_DQ5 HSMA_RX_D_P2 HSMA_RX_D_N2 HSMB_DQ6 HSMB_DQ7 HSMA_RX_D_P3 HSMA_RX_D_N3 HSMB_DQ8 HSMB_DQ9 HSMA_RX_D_P4 HSMA_RX_D_N4 HSMB_DQ10 HSMB_DQ11 HSMA_RX_D_P5 HSMA_RX_D_N5 HSMB_DQ12 HSMB_DQ13 HSMA_RX_D_P6 HSMA_RX_D_N6 HSMB_DQ14 HSMB_DQ15 HSMA_RX_D_P7 HSMA_RX_D_N7 HSMB_CLK_OUT_P1 HSMB_CLK_OUT_N1 HSMA_CLK_IN_P1 HSMA_CLK_IN_N1 HSMB_DQ16 HSMB_DQ17 HSMB_DQ18 HSMB_DQ19 HSMA_RX_D_P9 HSMA_RX_D_N9 HSMB_DQ20 HSMB_DQ21 HSMA_RX_D_P10 HSMA_RX_D_N10 HSMB_DQ22 HSMB_DQ23 HSMA_RX_D_P11 HSMA_RX_D_N11 HSMB_DQ24 HSMB_DQ25 HSMA_RX_D_P12 HSMA_RX_D_N12 HSMB_DQ26 HSMB_DQ27 HSMA_RX_D_P13 HSMA_RX_D_N13 HSMB_DQ28 HSMB_DQ29 HSMA_RX_D_P14 HSMA_RX_D_N14 HSMB_DQ30 HSMB_DQ31 HSMA_RX_D_P15 HSMA_RX_D_N15 HSMB_C_P DDR ODT HSMB_C_N HSMA_RX_D_P16 HSMA_RX_D_N16 HSMB_CLK_OUT_P2 HSMB_CLK_OUT_N2 HSMA_CLK_IN_P2 HSMA_CLK_IN_N2 HSMA_PRSNTn 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 3.3V 47 49 3.3V 53 55 3.3V 59 61 3.3V 65 67 3.3V 71 73 3.3V 77 79 3.3V 83 85 3.3V 89 91 3.3V 95 97 3.3V 101 103 3.3V 107 109 3.3V 113 115 3.3V 119 121 3.3V 125 127 3.3V 131 133 3.3V 137 139 3.3V 143 145 3.3V 149 151 3.3V 155 157 3.3V 3.3V 12V 2 ASP-122953-01 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 BANK 1 42 44 12V 48 50 12V 54 56 12V 60 62 12V 66 68 12V 72 74 12V 78 80 12V 84 86 12V 90 92 12V 96 98 12V BANK 2 B BANK 3 102 104 12V 108 110 12V 114 116 12V 120 122 12V 126 128 12V 132 134 12V 138 140 12V 144 146 12V 150 152 12V 156 158 PSNTn 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 Title B Date: 7 6 5 4 3 E HSMB_RX_P3 HSMB_RX_N3 HSMB_RX_P2 HSMB_RX_N2 HSMB_RX_P1 HSMB_RX_N1 HSMB_RX_P0 HSMB_RX_N0 HSMB_SCL HSMB_JTAG_TMS HSMB_JTAG_TDI HSMB_CLK_IN0 HSMB_RASn HSMB_CASn HSMB_DM0 HSMB_A0 HSMB_A1 HSMB_A2 HSMB_A3 HSMB_A4 HSMB_DQS_P0 HSMB_DQS_N0 8 8 8 8 8 8 8 8 4 HSMC PORT A 12 HSMA_D[3:0] 12 9 HSMA_TX_D_P[16:0] 4 5,6 HSMA_TX_D_N[16:0] 5,6 HSMA_RX_D_P[16:0] 5,6 D HSMA_RX_D_N[16:0] 5,6 HSMA_CLK_OUT_P[2:1] 5,6 HSMA_CLK_OUT_N[2:1] 5,6 HSMA_CLK_IN_P[2:1] 9 HSMA_CLK_IN_N[2:1] 9 HSMB_DM1 HSMB_A5 HSMA_PRSNTn HSMB_A6 HSMB_A7 HSMC PORT B INTERFACE HSMB_A8 HSMB_A9 HSMB_BA[3:0] HSMB_DQS_P1 HSMB_DQS_N1 HSMB_CLK_IN_P1 HSMB_CLK_IN_N1 18,24,5 HSMB_A[15:0] 6 6 C HSMB_DM[3:0] 6 HSMB_DQ[31:0] 6 HSMB_DQS_P[3:0] 6 HSMB_DQS_N[3:0] HSMB_DM2 HSMB_A10 HSMB_A11 HSMB_A12 HSMB_A13 HSMB_A14 HSMB_DQS_P2 HSMB_DQS_N2 HSMB_DM3 HSMB_A15 HSMB_BA0 HSMB_BA1 6 HSMB_CLK_IN_P[2:1] 9 HSMB_CLK_IN_N[2:1] 9 HSMB_CLK_OUT_P[2:1] 6 HSMB_CLK_OUT_N[2:1] 6 HSMB_WEn HSMB_CSn HSMB_CKE HSMB_CASn HSMB_RASn HSMB_PRSNTn HSMB_C_P HSMB_C_N HSMB_ADDR_CMD0 6 6 6 6 6 18,24,5 6 6 6 HSMB_BA2 HSMB_BA3 HSMB_DQS_P3 HSMB_DQS_N3 HSMB_CKE HSMB_CSn 12V B 3.3V C79 C78 10uF 10uF 12V HSMB_CLK_IN_P2 HSMB_CLK_IN_N2 HSMB_PRSNTn A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Size 8 1 J2 HSMB_TX_P3 HSMB_TX_N3 HSMB_TX_P2 HSMB_TX_N2 HSMB_TX_P1 HSMB_TX_N1 HSMB_TX_P0 HSMB_TX_N0 HSMB_SDA JTAG_TCK HSMB_JTAG_TDO HSMB_CLK_OUT0 161 162 163 164 165 166 167 168 169 170 171 172 E HSMA_TX_P7 HSMA_TX_N7 HSMA_TX_P6 HSMA_TX_N6 HSMA_TX_P5 HSMA_TX_N5 HSMA_TX_P4 HSMA_TX_N4 HSMA_TX_P3 HSMA_TX_N3 HSMA_TX_P2 HSMA_TX_N2 HSMA_TX_P1 HSMA_TX_N1 HSMA_TX_P0 HSMA_TX_N0 HSMA_SDA JTAG_TCK HSMA_JTAG_TDO HSMA_CLK_OUT0 3 HSMC Port A & Port B J1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 4 GND_1_1 GND_1_2 GND_1_3 GND_1_4 GND_2_1 GND_2_2 GND_2_3 GND_2_4 GND_3_1 GND_3_2 GND_3_3 GND_3_4 7 161 162 163 164 165 166 167 168 169 170 171 172 8 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 22 of 1 34 D1.1 8 7 6 5 4 3 2 1 10/100/1000 Ethernet U19A ENET_RESETn R93 R100 R94 R102 4.7K 4.7K 4.7K 4.7K C432 0.01uF C417 0.01uF C451 0.01uF R280 R281 R278 R279 R277 R291 R292 R293 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 2.5V J9 2.5V VCC MDI_P0 MDI_N0 MDI_P1 MDI_N1 MDI_P2 MDI_N2 MDI_P3 MDI_N3 TD0_P TD0_N TD1_P TD1_N TD2_P TD2_N GND_TAB GND_TAB D R290 10.0K 1 2 GND 1 2 3 6 4 5 7 8 10 MDI_P0 MDI_N0 MDI_P1 MDI_N1 MDI_P2 MDI_N2 MDI_P3 MDI_N3 29 31 33 34 39 41 42 43 ENET_MDIO ENET_MDC ENET_INTn 24 25 23 37 38 HFJ11-1G02E 30 56 ENET_RSET 2.5V X5 EN VCC GND OUT 3 22 55 54 53 ENET_XTAL_25MHZ C431 13 51 B 97 NC1 NC2 HSDAC_P HSDAC_N R106 4.7K TRST_N TCK TDI TDO TMS 2 94 3 RXCLK RX_DV RX_ER 95 92 93 91 90 89 87 86 RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 D 84 83 CRS COL RSET SEL_FREQ 125CLK XTAL1 XTAL2 VSSC 11 12 14 16 17 18 19 20 TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 79 80 82 81 77 75 S_CLK_P S_CLK_N S_IN_P S_IN_N S_OUT_P S_OUT_N 68 69 70 73 74 76 LED_TX LED_RX LED_DUPLEX LED_LINK1000 LED_LINK100 LED_LINK10 SGMII Mode (default) ENET_TX_P ENET_TX_N ENET_RX_P ENET_RX_N 4 4 11 4 ENET_LED_TX ENET_LED_RX C ENET_LED_LINK1000 ENET_LED_LINK100 ENET_LED_LINK10 88E1111 72 66 52 VDDOH VDDOH VDDOH VDDO VDDO VDDO VDDO VDDOX VDDOX 5 21 88 96 R103 4.99K 26 48 2.5V AVDD AVDD AVDD AVDD AVDD AVDD MDIO MDC INT_N JTAG 47 49 44 50 46 0.01uF C 32 36 35 40 45 78 MDI0_P MDI0_N MDI1_P MDI1_N MDI2_P MDI2_N MDI3_P MDI3_N 4 25.00MHz U19B CONFIG0 CONFIG1 CONFIG2 CONFIG3 CONFIG4 CONFIG5 CONFIG6 TEST 12 11 2.5V TD3_P TD3_N ENET_LED_LINK1000 ENET_LED_LINK10 ENET_LED_RX 9 65 64 63 61 60 59 58 MGMT 0.01uF 4 4 4 4 E 8 4 9 7 GTX_CLK TX_CLK TX_EN TX_ER MDI INTERFACE C393 ENET_MDIO ENET_MDC ENET_INTn ENET_RESETn COMA RESET_N GMII/MII/TBI INTERFACE 2.5V 27 28 SGMII INTERFACE E ENET_DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD 1 6 10 15 57 62 67 71 85 2.5V D29 Green_LED ENET_LED_TX R316 220 D30 Green_LED R315 ENET_LED_RX 220 B D32 Green_LED VSS 88E1111 ENET_LED_LINK1000 R313 220 D31 Green_LED ENET_LED_LINK100 Place near 88E1111 PHY 2.5V R314 220 ENET_DVDD C449 C450 C416 C390 C392 C478 C415 C389 C430 C388 C391 C367 C429 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 23 of 1 34 D1.1 8 7 6 5 4 3 2 1 User I/O 2.5V D16 Red_LED MAX_ERROR E RES_MAX_ERROR D15 MAX_LOAD D17 MAX_CONF_DONE Green_LED RES_MAX_LOAD R146 100, 1% 2.5V R49 75 1 4 R48 USER_LED_R0 75 R47 75 1 USER_LED_R1 75 4 R46 D21 LED_GR G 3 2.5V USER_LED_G0 D6 R147 56.2 Green_LED RES_CONF_DONEn R145 56.2 2.5V R 2 D20 LED_GR G 3 R PGM_LED0 D5 USER_LED_G1 PGM_LED1 HSMA_RX_LED RESn_HSMA_RX_LED R148 56.2 D4 D19 LED_GR 1 G 3 Green_LED D3 RESn_HSMA_TX_LED R143 HSMA_TX_LED D 75 R44 USER_LED_R2 75 R43 RESn_HSMB_RX_LED R144 56.2 USER_LED_R3 75 Green_LED D11 RESn_HSMB_TX_LED R130 56.2 Green_LED HSMA_PRSNTn R1 R2 4 PCIE_LED_X1 75 4 R26 USER_LED_R4 75 R25 75 1 USER_LED_R5 75 4 R24 R23 75 1 4 R22 USER_LED_R6 75 56.2 R350 YELLOW LED R142 56.2 CPU_RESETn R R USER_LED_G3 R349 YELLOW LED R348 R 1 2 USER_LED_G4 S1 1 2 2 3 PGM_CONFIG 4 PB Switch 3 PGM_SEL 4 PB Switch 3 MAX_RESETn 4 PB Switch R36 10.0K R37 10.0K R19 10.0K 3 CPU_RESETn 4 PB Switch R38 10.0K S4 1 2 USER_LED_G5 2 D8 LED_GR G 3 R 1 2 2 1 2 1 4 R20 USER_LED_R7 75 D7 LED_GR G 3 USER_LED_G7 S5 1 2 56.2 D37 YELLOW LED R351 56.2 YELLOW LED R352 56.2 R 2 3 USER_PB0 4 PB Switch 3 USER_PB1 4 PB Switch 3 USER_PB2 4 PB Switch R41 10.0K R40 10.0K R39 10.0K 18,31 18,24 18,24 18,24 HSMA_RX_LED HSMA_TX_LED HSMB_RX_LED HSMB_TX_LED 5 5 5 5 2.5V HSMA_PRSNTn HSMB_PRSNTn 18,22,5 18,22,5 PCIE_LED_X1 PCIE_LED_X4 PCIE_LED_X8 PCIE_LED_G2 PCIE_LED_G3 4 4 4 4 11 USER_DIPSW[7:0] 6 CLK_SEL CLK_ENABLE FACTORY_LOAD SECURITY_MODE 10,18 CLK_SEL CLK_ENABLE 18 FACTORY_LOAD18 18 SECURITY_MODE D33 D12 2.5V Red_LED OVERTEMPn RESn_LED_FAN R149 PUSH BUTTON INTERFACE 56.2 B2 SW1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 USER_DIPSW0 USER_DIPSW1 USER_DIPSW2 USER_DIPSW3 USER_DIPSW4 USER_DIPSW5 USER_DIPSW6 USER_DIPSW7 RN1H RN1G RN1F RN1E RN1D RN1C RN1B RN1A 8 7 6 5 4 3 2 1 S5_VCCIO_HSMB 9 10K 10 10K 11 10K 12 10K 13 10K 14 10K 15 10K 16 10K PGM_SEL PGM_CONFIG MAX_RESETn B3 PGM_SEL PGM_CONFIG MAX_RESETn 18 18 18 B LED INTERFACE PGM_LED[2:0] PGM_LED[2:0] 2.5V SW5 8 7 6 5 OPEN B D C D34 PCIE_LED_G3 4,9 2.5V S7 S6 75 11,4,5,6,9 OVERTEMPn MAX_ERROR MAX_LOAD MAX_CONF_DONE S5_VCCIO_HSMB USER_LED_G6 56.2 R21 9 USER_LED_G[7:0] S2 1 2 2 D9 LED_GR G 3 11,18 USER_PB[2:0] USER_LED_R[7:0] 56.2 D36 PCIE_LED_G2 Green_LED RESn_PGM_LED2 2.5V Green_LED YELLOW LED PCIE_LED_X8 56.2 Green_LED D35 PCIE_LED_X4 R141 2 D10 LED_GR 1 G 3 2.5V C Green_LED RESn_PGM_LED1 USER_LED_G2 S3 56.2 D2 HSMB_PRSNTn R27 3.3V D1 R D18 LED_GR 1 G 3 75 R42 HSMB_TX_LED 4 56.2 56.2 Green_LED D14 HSMB_RX_LED R45 R140 2 PGM_LED2 D13 E Green_LED RESn_PGM_LED0 1 2 3 4 CLK_SEL CLK_ENABLE FACTORY_LOAD SECURITY_MODE R362 R361 R360 R359 10.0K 10.0K 10.0K 10.0K 1.8V 2x16 LCD 2x7 HDR 5.0V LCD_WEn LCD_DATA0 LCD_DATA2 LCD_DATA4 LCD_DATA6 1 3 5 7 9 11 13 1 3 5 7 9 11 13 2 4 6 8 10 12 14 2 4 6 8 10 12 14 LCD_D_Cn LCD_CSn LCD_DATA1 LCD_DATA3 LCD_DATA5 LCD_DATA7 18 MAX_ERROR 18,24 MAX_LOAD 18,24 MAX_CONF_DONE 18,24 J15 TDA04H0SB1 TDA08H0SB1 MAX_ERROR MAX_LOAD MAX_CONF_DONE LCD_DATA[7:0] 5 LCD_CSn LCD_D_Cn LCD_WEn 5 5 5 HDR2X7 A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 24 of 1 34 D1.1 8 7 6 5 4 3 2 On-Board USB Blaster II 1 STRATIX V USB INTERFACE USB_DATA[7:0] R72 FX2_SDA VBUS_5V FX2_D_N FX2_D_P R246 C247 USB_ADDR[1:0] 0.1uF 1 100K R205 FX2_RESETn 2 GND VCC RESET MR 4 U14A U43 1M R260 GND D+ D- 1 2 3.3V U8 TPD2EUSB30 D1 D2 4.7nF G1 A5 B5 C5 E7 E8 C346 D E1 E2 4 Y1 3 2 1 C205 12pF G2 C1 C2 USB_CLK 24M_XTALIN 24M_XTALOUT 24.00MHz C204 12pF G8 G6 F8 F7 F6 C8 C7 C6 FX2_PA1 FX2_PA2 FX2_PA3 FX2_PA4 FX2_PA5 FX2_PA6 FX2_PA7 C H2 F1 F2 H1 A4 B4 C4 D7 D8 3.3V AVCC AVCC RESET SCL SDA VCC VCC VCC VCC VCC VCC WAKEUP CTL0 CTL1 CTL2 DMINUS DPLUS RDY0 RDY1 IFCLK XTALIN XTALOUT CLKOUT PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 RESERVED PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 AGND AGND GND GND GND GND GND GND B8 F3 G3 FX2_RESETn FX2_SCL R206 FX2_SDA R71 B7 FX2_WAKEUP H7 G7 H8 FX2_FLAGA FX2_FLAGB FX2_FLAGC A1 B1 FX2_SLRDn FX2_SLWRn 2.00K 2.00K FX2_PA6 FX2_PB2 FX2_FLAGB FX2_PB0 FX2_PA1 FX2_PB5 USB_DISABLEn JTAG_FPGA_TDO B2 H3 F4 H4 G4 H5 G5 F5 H6 FX2_PB0 FX2_PB1 FX2_PB2 FX2_PB3 FX2_PB4 FX2_PB5 FX2_PB6 FX2_PB7 A8 A7 B6 A6 B3 A3 C3 A2 FX2_PD0 FX2_PD1 FX2_PD2 FX2_PD3 FX2_PD4 FX2_PD5 FX2_PD6 FX2_PD7 10.0K JTAG_FPGA_TDO_RETIMER C192 20.0K 0.1uF F2 E1 FX2_RESETn MAX_SDA K8 L8 0 R259 A7 USB_RDn A8 USB_WRn A9 FACTORY_STATUS B10 USB_CFG3 M570_PCIE_JTAG_EN B11 B2 USB_CFG4 B3 EXTRA_SIG1 B4 USB_CFG6 C221 C193 C222 C203 C202 C326 C235 C248 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF F10 G11 USB_CFG7 M570_CLOCK 1.8V R242 TCK TDI TDO TMS IOB1/DEV_CLRn IOB1/DEV_OE K1 J2 K2 J1 M570_PCIE_JTAG_EN M570_PCIE_JTAG_EN 18 JTAG_FPGA_TDO_RETIMER 12,22 MAX V USB INTERFACE JTAG_FPGA_TDO_RETIMER FX2_SLRDn FX2_PD7 FX2_PD5 FX2_PA5 C_JTAG_TDO C_JTAG_TMS C_JTAG_TDI USB_CFG[11:0] EXTRA_SIG[2:0]18 D USB_DISABLEn M570_CLOCK FACTORY_STATUS FACTORY_REQUEST R86 R87 R88 R85 C_USB_MAX_TCK C_USB_MAX_TDI C_USB_MAX_TDO C_USB_MAX_TMS USB_CFG[11:0] 18 EXTRA_SIG[2:0] 0 0 0 0 USB_DISABLEn 12 M570_CLOCK 18 FACTORY_STATUS 18 18 FACTORY_REQUEST FX2_PD0 FX2_PD2 FX2_PD3 FX2_PD1 JTAG INTERFACE JTAG_TCK JTAG_TMS JTAG_BLASTER_TDI JTAG_BLASTER_TDO 11 JTAG_FPGA_TDO MAX II BANK2 IOB2_1 IOB2_2 IOB2_3 IOB2_4 IOB2_5 IOB2_6 IOB2_7 IOB2_8 IOB2_17 IOB2_18 IOB2_19 IOB2_20 IOB2_21 IOB2_22 IOB2_23 IOB2_24 IOB2_9 IOB2_10 IOB2_11 IOB2_12 IOB2_13 IOB2_14 IOB2_15 IOB2_16 IOB2_25 IOB2_26 IOB2_27 IOB2_28 IOB2_29 IOB2_30 IOB2_31 IOB2_32 IOB2/GCLK2 IOB2/GCLK3 IOB2_33 IOB2_34 IOB2_35 IOB2_36 IOB2_37 IOB2_38 B5 B6 B7 B8 B9 C10 C11 C6 USB_DATA0 USB_DATA1 USB_DATA2 USB_DATA3 USB_DATA4 USB_DATA5 USB_DATA6 USB_DATA7 D10 D11 D9 E10 E11 F11 F9 G10 USB_CFG8 USB_ADDR0 USB_ADDR1 USB_FULL USB_EMPTY USB_SCL USB_CFG11 USB_SDA H10 H11 H9 J10 J11 K11 USB_CFG10 USB_CFG0 EXTRA_SIG2 USB_CFG1 USB_CFG2 USB_CFG9 JTAG_TCK11,12,18,22 JTAG_TMS 11,12 JTAG_BLASTER_TDI JTAG_BLASTER_TDO 12 11,12 C U14C C5 E8 G4 J5 D5 D7 E4 G8 H5 H7 V13 1.8V MAX II Power GNDINT GNDINT GNDINT GNDINT VCCINT VCCINT VCCINT VCCINT GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 C7 E9 G3 J7 3.3V E3 J4 J8 1.5V C4 C8 G9 EPM570GM100 B V15 V14 PLACE NEAR MAX II (U14) 3.3V 1.5V 56.2 Green_LED D27 RESn_JTAG_TX R243 56.2 1.8V C_JTAG_TCK C_JTAG_TMS C_JTAG_TDI C_JTAG_TDO R77 R80 R75 R76 1.00k 1.00k 1.00k 1.00k USB_SCL USB_SDA USB_FULL USB_EMPTY R73 1.00k FACTORY_REQUEST 0 0 0 0 R266 R275 R265 R274 JTAG_TCK JTAG_TMS JTAG_BLASTER_TDI JTAG_BLASTER_TDO DNI JTAG_BLASTER_TDI C327 C306 C269 C268 C305 C270 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 2.5V Green_LED D26 SC_RX IOB1/GCLK0 IOB1/GCLK1 L11 L2 L3 L4 L5 L6 L7 L9 FX2_PB6 FX2_PB1 FX2_PB3 FX2_SCL FX2_PD6 FX2_PD4 FX2_SLWRn C_JTAG_TCK E 1.5V RESn_JTAG_RX JTAG_TX IOB1_25 IOB1_26 IOB1_27 IOB1_28 IOB1_29 IOB1_30 IOB1_31 IOB1_32 K3 K4 K5 K6 K7 K9 L1 L10 USB_FULL 9 USB_EMPTY 9 USB_SCL 7 USB_SDA 7 USB_CLK 18,9 USB_RESETn7 USB_OEn 7 USB_RDn 7 USB_WRn 7 EPM570GM100 D28 JTAG_RX IOB1_9 IOB1_10 IOB1_11 IOB1_12 IOB1_13 IOB1_14 IOB1_15 IOB1_16 JTAG_FPGA_TDO A1 JTAG_TX A10 SC_RX A11 SC_TX A2 JTAG_RX FACTORY_REQUEST A3 A4 USB_CFG5 A5 USB_RESETn A6 USB_OEn FX2_WAKEUP R189 USB_CLK FX2_PB7 IOB1_17 IOB1_18 IOB1_19 IOB1_20 IOB1_21 IOB1_22 IOB1_23 IOB1_24 U14B PLACE NEAR CY7C68013A 3.3V B F3 G1 G2 H1 H2 H3 J6 K10 IOB1_1 IOB1_2 IOB1_3 IOB1_4 IOB1_5 IOB1_6 IOB1_7 IOB1_8 EPM570GM100 CY7C68013A_VFBGA VBUS_5V R190 B1 C1 C2 D1 D2 D3 E2 F1 FX2_PA2 FX2_FLAGC FX2_PA7 FX2_FLAGA FX2_PA3 FX2_PA4 EXTRA_SIG0 FX2_PB4 MAX811 3 MAX II BANK1 3 USB_ADDR[1:0]7 USB_FULL USB_EMPTY USB_SCL USB_SDA USB_CLK USB_RESETn USB_OEn USB_RDn USB_WRn U9 DNI USB_DATA[7:0] 7 MAX_SDA 3.3V 9 8 7 6 E J7 MICRO_USB_CONN 1 VBUS 2 DD+ 3 4 ID 5 0 RESn_SC_RX R244 56.2 3.3V 3.3V R308 J19 R155 Green_LED D25 A SC_TX RESn_SC_TX R245 56.2 R172 Green_LED 1.00K C_USB_MAX_TCK 1 C_USB_MAX_TDO 3 1.00K C_USB_MAX_TMS 5 7 C_USB_MAX_TDI 9 1 3 5 7 9 2 4 6 8 10 2 4 6 8 10 Title DNI Size B Date: 8 7 6 5 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 25 of 1 34 D1.1 8 7 6 5 4 3 2 1 Power 1 - DC Input & 12V, 3.3V Output 12V 12V_OUT R62 19V DC Input 4 U30 4 3 2 U7 5 D39 NC 1 6 4 7 C4 C2 47uF 35V 47uF 35V C1 22uF 25V DC_IN C3 22uF 25V INTVCC_1 LTC4357 LTC4357 U37 FDMC8878 D 1 2 3 12V_MUX D42 CMDSH-3 U3 drain-tab 5.0V 8 7 6 5 INTVCC_1 MMBD1205 C97 26 25 24 VIN INTVCC EXTVCC TG1 BOOST1 4.7uF 3.3V_SHDNn 4 U6 3 2 5 GATE IN NC RJK0305DPB OUT VDD GND EP_GND 1 6 4 7 C83 22uF 25V Q4 R158 20.0K 12V_SHDNn LTC4357 38 37 14 2 1 13 36 15 6 7 SW1 RUN1 ITEMP1 ILIM1 ITH1 TK/SS1 BG1 VFB1 RUN2 ITEMP2 ILIM2 ITH2 TK/SS2 SENSE1+ SENSE1PGOOD1 30 4 C10 L2 0.1uF 29 1 2 3 NC 1 6 4 7 OUT VDD GND EP_GND DC_IN OUT VDD GND EP_GND 31 Q7 5 5 GATE IN GATE IN RJK0301DPB 4 27 3.3V_MUX 2 3 2uH V3 drain-tab 2 SNS RSNS 1 SENSE_PAD 39 40 R50 LTC3855_S1P LTC3855_S1N 3.4K R60 100K C18 16 V4 C9 100uF 6.3v 0.1uF R166 DIFFOUT 11.5K 10 12 11 8 1 2 3 VIN 3 4 LTC4352CDD 2 VCC R165 49.9K R168 100K C132 47pF C133 SGND1 SGND2 PGND1 PGND2 NC TG2 BOOST2 SW2 gnd-pad CPO SOURCE GATE OUT REV EP GND 7 13 9 0.1uF 82pF C131 18pF R176 66.5K 5 6 4 C35 B C129 10pF Q5 R175 121.0K BG2 VFB2 20 4 21 C11 drain-tab 0.1uF RJK0305DPB 4 1 19 RJK0301DPB V1 4 5 VFB2 2 2.0uH Q6 drain-tab 23 12V_MUX L1 2 SNS RSNS 1 SENSE_PAD DIFFOUT 12 10 11 3.3V_MUX U40 FDMC8878 SENSE2+ SENSE2- DIFFOUT DIFFP DIFFN PGOOD2 8 9 LTC3855_S2P LTC3855_S2N R150 C23 8.2K DNI R61 17 PG_12V 0.1uF 1 1 UV OV D22 STATUS FAULT R69 DNI Q3 drain-tab 4 41 28 22 18 3.3V_PCIE RJK0305DPB 2 R167 20.0K C R177 2.55K C84 22uF 25V R174 215.0K V2 RSNS SNS R156 169.0K 3.3V_MUXVCCP 5 1000pF DC_IN 1 2 3 1000pF CMDSH-3 D41 5 C128 1 2 3 C130 FREQ MODE/PLLIN PHSASMD CLKOUT 5 3.3V_REG R66 0.003 35 34 33 32 1 2 3 3.3V_OUT C R163 100K C16 330uF 4V SENSE_PAD INTVCC_1 R157 49.9K D 1 1 2 3 3 2 E 2 8 7 6 5 8 7 6 5 1 2 3 RSNS SNS 1 2 3 12V_PCIE U29 FDMC8878 J4 CONN JACK PWR 2 1 3 1 U36 FDMC8878 E DC_INPUT 5 0.003 C127 C111 47uF 20V C17 47uF 20V 220uF 16V VFB2 R164 11.3K SENSE_PAD B LTC3855EUJ R162 100K 8 7 6 5 8 7 6 5 FDMC8878 U39 3.3V_MUX D23 10 3.3V_MUX 1 LTC4352CDD GND EP REV 9 13 7 R79 1.00k VIN VCC DC_IN DC_IN 100K POWER LED CPO 3 4 A R70 DNI OUT GATE SOURCE UV OV 1 2 3 8 11 12 STATUS FAULT 4 5 6 5.0V 12V_SHDNn 2 D24 BLUE LED C36 0.1uF R99 20.0K R101 7 1 8 9 2 3 10 4 11 12 5 6 R104 100K 3.3V_SHDNn R98 20.0K SW2 SW SLIDE-4P2T Title Size B 3.3V_MUXVCC Date: 8 7 6 5 4 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 26 of 1 34 D1.1 8 7 6 5 4 3 2 1 Power 2 - 0.90V 28 SV_VCCINT_PG 18 18 VCCINT_SCL VCCINT_SDA E E 12V 5.0V_LTC3880 12V 22uF 25V CMDSH-3 D44 D45 CMDSH-3 VIN INTVCC BG0 RUN0 15 2 0.01uF 3 C277 C275 C276 3.3nF 680pF 680pF R229 3.01K VSENSE0+ VSENSE0- R240 R238 R239 R237 R230 GPIO0 GPIO1 1 2 12 PG_VCCINT 10K 13 10K R236 R235 18 19 SYNC SDA SCL ALERT SHARE_CLK WP R219 R231 DNI DNI 20 21 VOUT0_CFG VOUT1_CFG VDD25 TG1 BOOST1 SW1 R233 R234 30 4 16 R247 R248 10K 23.2K 2.2K 22uF 4V C176 100uF 6.3V C173 100uF 6.3V 330uF 2.5V D C174 330uF 2.5V SENSE_PAD C33 0.1uF 31 29 Q2 ASEL PGND GND_PAD R65 0.0015 0.33uH Q10 4 C 1 V10 drain-tab 4 3 4 L4 2 drain-tab RJK0301DPB 32 0.9V RJK0305DPB 2 RJK0301DPB SNS RSNS C22 1 SENSE_PAD R74 LTC3880_IS1P LTC3880_IS1N 2.2K R68 301K C31 27 0.1uF FREQ_CFG VDD25 22uF 4V C175 C206 22uF 25V Q8 S5_VCCINT VSENSE1 17 16.2K 17.4K ISENSE1+ ISENSE1- VTRIM0_CFG VTRIM1_CFG VDD25 V7 C20 12V 1 2 3 30.1K 3.57K 1 0.1uF VDD25 R220 R232 SNS RSNS R83 301K C38 drain-tab 8 4.99K 10K VCCINT_SDA 10 10K VCCINT_SCL 9 10K 11 10K 24 23 C19 VDD33 ITH1 BG1 B R67 VDD33 C 2 LTC3880_IS0P LTC3880_IS0N S5_VCCINT ITH0 26 6 7 5 3 0.01uF TSNS0 TSNS1 5 C274 ISENSE0+ ISENSE0- R64 0.001 V8 RJK0301DPB SENSE_PAD RUN1 40 28 0.85V_TSNS0 0.85V_TSNS1 Q12 MMBT3906 1 2 Q13 MMBT3906 C280 1 4 S5_VCCINT R63 0.0015 2 14 1 0.33uH Q1 drain-tab 4 0.9V C21 22uF 4V V9 RSNS SNS R249 3880_RUN drain-tab RJK0301DPB 36 5 4.7uF 3.3V_REG 10K 39 2 Q11 1 2 3 10uF C32 0.1uF 1 2 3 1uF SW0 L3 1 C223 37 RJK0305DPB 5 1uF BOOST0 4 2 33 C278 C279 D VDD33 38 RSNS SNS 25 5.0V_LTC3880 TG0 1 VDD33 drain-tab VDD25 5 22 Q9 1 2 3 VDD25 C307 5 U13 35 C207 22uF 25V 1 2 3 47uF 20V C24 1 2 3 C27 22uF 25V 5 C194 22uF 4V C169 100uF 6.3V C170 100uF 6.3V C172 C171 330uF 2.5V 330uF 2.5V SENSE_PAD 34 41 B LTC3880 S5_VCCINT 3.3V R251 R252 12.0K 15.0K U44 5 3.3V VM_0P5V R250 R222 0 MANUAL_RESETn DNI RT A 4 2 7 3 6 3.3V VCC RST 8 SV_VCCINT_PG R221 10K VM TOL/MR RT SEL1 SEL2 3.3V GND EPAD 1 9 Title 0.1uF Size B Date: 8 7 6 5 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 C329 LTC2915 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 27 of 1 34 D1.1 8 7 6 5 4 3 2 1 Power 3 - 5.0V, 1.5V, 1.8V and 3.3V SV_VCCINT_PG 27 12V U27C 5.0V E C398 5.0V 5.0V VOUTS2_1P5 U27A C5 C8 H8 J7 C516 4.7uF RUN_LTM4628 F5 F9 J6 E5 D8 C6 G4 C509 0.1uF R318 150K D U27B F4 5.0V VOUTS1 VOUTS2 PGOOD1 PGOOD2 INTVCC EXTVCC SW1 VFB1 RUN1 RUN2 SW2 TEMP VFB2 TRACK1 TRACK2 CLKOUT DIFFOUT FSET PHASMD COMP1 COMP2 MODE-PLLIN DIFFP DIFFN G9 G8 PG_5.0V PG_1.5V R327 R326 10K 10K 47uF 20V C541 C542 C540 C539 10uF 35V 10uF 35V 10uF 35V 10uF 35V J9 J10 J11 K2 K3 K4 K9 K10 K11 M2 M3 M4 L8 L7 L6 L5 L4 L3 L2 M11 M10 M9 M8 M7 M6 M5 J4 J3 J2 L11 L10 L9 G2 D5 R317 8.25K G11 D7 G5 F8 R319 40.2K VOUTS2_1P5 E6 E7 1.5V E8 E9 LTM4628 SV_VCCINT_PG PG_3.3V R109 R108 0 DNI VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 C3 C4 C452 22uF 6.3V C453 22uF 6.3V C454 C486 22uF 6.3V 100uF 6.3V C485 470uF 6.3V 1.5V VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 C12 C11 C10 C9 B12 B11 B10 B9 B8 A8 A9 A10 A11 A12 C455 22uF 4V C457 22uF 4V C456 C487 22uF 4V 100uF 6.3V C488 470uF 6.3V A6 A7 B6 B7 D1 D2 D3 D4 D9 D10 D11 D12 E1 E2 E3 E4 E10 E11 E12 F1 F2 F3 F10 C7 F6 F7 G6 G7 D6 F11 F12 G1 G10 G12 H1 H2 H3 H4 H5 H6 H7 H9 H10 H11 H12 J1 J5 J8 J12 K1 K5 K6 G3 M12 M1 L12 L1 K12 K8 K7 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND SGND SGND SGND SGND SGND SGND E D LTM4628 RUN_LTM4628 LTM4628 U26C 12V U26B 1.8V C U26A 5.0V 3.3V VOUTS1_1P8 C5 C8 H8 J7 C518 3.3V_REG 10K 4.7uF R328 LTM4628_RUN1 F5 F9 J6 E5 D8 C517 0.1uF R321 150K B C6 G4 F4 VOUTS1 VOUTS2 PGOOD1 PGOOD2 INTVCC EXTVCC SW1 VFB1 RUN1 RUN2 SW2 TEMP VFB2 TRACK1 TRACK2 J9 J10 J11 K2 K3 K4 K9 K10 K11 M2 M3 M4 L8 L7 L6 L5 L4 L3 L2 M11 M10 M9 M8 M7 M6 M5 J4 J3 J2 L11 L10 L9 3.3V CLKOUT DIFFOUT FSET PHASMD COMP1 COMP2 MODE-PLLIN DIFFP DIFFN G9 G8 PG_1.8V PG_3.3V R323 R329 G2 10K 10K C399 47uF 20V D5 C537 C536 C538 C535 10uF 35V 10uF 35V 10uF 35V 10uF 35V R320 30.1K G11 D7 G5 F8 R322 13.3K VOUTS1_1P8 E6 E7 1.8V E8 E9 LTM4628 VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VIN VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 VOUT1 A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 C3 C4 C459 22uF 4V C458 22uF 4V C460 C490 22uF 4V 100uF 6.3V C489 470uF 6.3V 3.3V VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 VOUT2 C12 C11 C10 C9 B12 B11 B10 B9 B8 A8 A9 A10 A11 A12 C463 22uF 4V C462 22uF 4V C461 C491 22uF 4V 100uF 6.3V C492 470uF 6.3V A6 A7 B6 B7 D1 D2 D3 D4 D9 D10 D11 D12 E1 E2 E3 E4 E10 E11 E12 F1 F2 F3 F10 C7 F6 F7 G6 G7 D6 F11 F12 G1 G10 G12 H1 H2 H3 H4 H5 H6 H7 H9 H10 H11 H12 J1 J5 J8 J12 K1 K5 K6 G3 M12 M1 L12 L1 K12 K8 K7 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND SGND SGND SGND SGND SGND SGND C B LTM4628 LTM4628 A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 28 of 1 34 D1.1 8 7 6 5 4 3 2 1 Power 3 - 1.0V (GXB), 1.5V (VCCD_FPLL, VCCH_GXB, VCCPT) E E PG_1.0V_FPGA 5.0V 30 U18A 5.0V C347 47uF 6.3V D S5_VCCPD_PGM_2.5V R294 1.0V_FPGA_RUN J1 J2 J3 J4 J5 J6 K1 K2 K3 K4 K5 K6 L2 L5 10.0K C433 1.0V_SW 0.01uF H2 H3 H4 H5 H6 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H7 H8 H9 H10 C U18B R282 10.0K LTM4614 - CHANNEL 1 VIN1_0 VIN1_1 VIN1_2 VIN1_3 VIN1_4 VIN1_5 VIN1_6 VIN1_7 VIN1_8 VIN1_9 VIN1_10 VIN1_11 PGOOD1 VOUT1_0 VOUT1_1 VOUT1_2 VOUT1_3 VOUT1_4 VOUT1_5 VOUT1_6 VOUT1_7 VOUT1_8 VOUT1_9 VOUT1_10 VOUT1_11 VOUT1_12 VOUT1_13 VOUT1_14 VOUT1_15 RUN/SS1 COMP1 SW1_0 SW1_1 SW1_2 SW1_3 SW1_4 TRACK1 FB1 L4 PG_1.0V_FPGA 5.0V S5_XCVR_GXB_1.0V J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 C395 R284 GND1_17 GND1_18 GND1_19 GND1_20 GND1_21 GND1_22 GND1_23 GND1_24 GND1_25 GND1_26 GND1_27 GND1_28 GND1_29 GND1_30 GND1_31 GND1_32 GND1_33 C394 47uF 6.3V 330uF 2.5V C397 0.1uF S5_VCCA_GXB R51 S5_VCCT_GXB L8 5.0V 1.5V_RUN E2 E5 10.0K 1.5V_SW L3 L6 H11 H12 J7 J8 K7 K8 L1 L7 L8 M1 M2 M3 M4 M5 M6 M7 M8 VIN2_0 VIN2_1 VIN2_2 VIN2_3 VIN2_4 VIN2_5 VIN2_6 VIN2_7 VIN2_8 VIN2_9 VIN2_10 VIN2_11 PGOOD2 VOUT2_0 VOUT2_1 VOUT2_2 VOUT2_3 VOUT2_4 VOUT2_5 VOUT2_6 VOUT2_7 VOUT2_8 VOUT2_9 VOUT2_10 VOUT2_11 VOUT2_12 VOUT2_13 VOUT2_14 VOUT2_15 RUN/SS2 COMP2 3A, 30 Ohm FB C396 0.1uF 1.0V_FB R283 GND1_0 GND1_1 GND1_2 GND1_3 GND1_4 GND1_5 GND1_6 GND1_7 GND1_8 GND1_9 GND1_10 GND1_11 GND1_12 GND1_13 GND1_14 GND1_15 GND1_16 C1 C2 C3 C4 C5 C6 D1 D2 D3 D4 D5 D6 S5_VCCR_GXB 0.003 R267 10.0K LTM4614 - CHANNEL 2 1.0V @ 2.625A B2 B3 B4 B5 B6 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B7 B8 B9 B10 20.0K LTM4614 SW2_0 SW2_1 SW2_2 SW2_3 SW2_4 TRACK2 FB2 E4 PG_1.5V_FPGA 1.5V_VCC R269 C9 C10 C11 C12 D9 D10 D11 D12 E9 E10 E11 E12 F9 F10 F11 F12 E3 E6 C328 S5_VCC_1.5V 0.003 1.5V @ 1.5A 330uF 2.5V C348 0.1uF D 5.0V 1.5V_FB R268 GND2_0 GND2_1 GND2_2 GND2_3 GND2_4 GND2_5 GND2_6 GND2_7 GND2_8 GND2_9 GND2_10 GND2_11 GND2_12 GND2_13 GND2_14 GND2_15 GND2_16 GND2_17 GND2_18 GND2_19 GND2_20 GND2_21 GND2_22 GND2_23 GND2_24 GND2_25 GND2_26 GND2_27 GND2_28 GND2_29 GND2_30 GND2_31 GND2_32 GND2_33 5.76K B11 B12 C7 C8 D7 D8 E1 E7 E8 F1 F2 F3 F4 F5 F6 F7 F8 C LTM4614 B B A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 29 of 1 34 D1.1 8 7 6 5 10.0K 10.0K S5_VCCIO_2.5V U57 E C73 15 VCCIO_2.5V_SHDn SHDN1 10uF 11 12 VIN2 VIN2 10 VCCIO_1.5V_SHDn C556 0.01uF R330 R378 C100 10uF 5.0V 5 S5_VCCIO_1.5V S5_1.5V 1.5V/0.426A C555 0.01uF R331 R377 5.0V VCONT 7 8 6 10.2K 43.2K C98 5.0V 5 10.0K S5_VCCIO_1.8V U50 IN IN NC OUT OUT OUT EP VCONT SET 5 ADJ 9 R116 R114 SHDN 1 2 8 15 16 NC1 NC2 NC3 NC4 NC5 C 10uF 5.0V 8 7 C514 5.0V 1 2 3 9 4 4 2.5V_SET OUT OUT OUT EP IN IN NC SET VCONT 7 8 6 5 LT3080-1/1.1A LDO LT3080-1/1.1A LDO D 82.5K 12V U49 6 7 10 11 17 AGND AGND PGND PGND EP_GND 1.5V 10uF R184 C473 10uF R311 10.0K 10 7 9 VIN EN PGOOD R115 VREF_DDR3 C150 6 49.9K REFOUT C181 TPS51200 LT3083EDF C57 6 7 R338 4.70M R337 590K C515 LT3009xDC 10uF VLDOIN REFIN 2.49K 1uF 6 GND GND_TAB 2 3 1 10uF U35 2.5V/1.279A 1 2 3 4 5 13 OUT1 OUT2 ADJ/NC SHDN C149 DDR3 VTT, VREF 5.37V_MONITOR VIN C508 4 3.3V U48 C54 1 2 3 9 1.50K 187 2.5V VOUT VOUT VOUT VOUT VOUT VOUT_EPAD VCTL VCTL SET 2.5V_SET R179 2.2uF C55 LT3022EDHC VIN VIN VIN VIN E L7 S5_VCCA_PLL_2.5V BLM21PG331SN1 5 3.3V_REG 9 10 11 12 2.2uF 10uF 10uF VCCIO_1.8V_SHDn R325 0.003 GND_PAD PGND GND C60 22uF C99 3 4 VOUT VOUT C114 U33 0.1uF XJ1 0.1uF 2 1 10.0K R183 VTT_DDR3 VO VOSNS R178 10.0K C134 3 5 10uF 11 4 8 D S5_1.8V VIN VIN VIN 4 SET C95 S5_VCCPD_PGM_2.5V 10uF 1.8V/0.601A 12 13 14 1 2 3 9 OUT OUT OUT EP 10uF VCCIO_1.8V_SHDn R160 R170 0.003 LT3080-1/1.1A LDO U31 2.2uF C72 LT3029EDE S5_VCCPD_PGM 3.3V_REG 1 C101 R363 0.003 8 9 IN IN NC 10uF 11.3K 10.7K 6 7 GND BYP2 EP_GND ADJ2 7 8 6 C71 2 NC SHDN2 VOUT2 VOUT2 5 17 R364 0.003 1 16 BYP1 ADJ1 U32 S5_VCCPD_PGM 3 4 VOUT1 VOUT1 5.0V S5_2.5V 2.5V/0.299A VIN1 VIN1 2 S5VCCPD_PGM = 2.5V/1.5A 3.3V_REG 13 14 3 Power 4 - Linear Regulators S5_VCCPD_PGM VCCIO_2.5V_SHDn R171 VCCIO_1.5V_SHDn R159 4 C25 C177 C179 C26 C178 10uF 10uF 10uF 10uF 10uF C135 C 1.0nF 2.2uF 1.8V 2mm Shunt S5_VCCIO_HSMB J8 C344 2 4 6 R84 R92 R97 2.00K 1.07K 604 QDRII+ and RLDRAM II VTT, VREF 3.3V 10uF U16 C272 S5_VAR U42 1uF 1 3.3V_REG B 3 C273 HSMB_SHDn 6 OUT IN ADJ 10uF LTC3025-1 R258 GND EP_GND 4 5 R78 0.003 10.0K 2 7 10.0K 5.0V VIN EN PGOOD VREF_QDRII_RLD C345 6 R218 C271 10 7 9 976 1uF S5_VCCPD_PGM R152 R213 S5_VCCIO_HSMB_SEL 187 HSMB_SHDn S5_VCCIO_HSMB 2.5V/0.337A BIAS SHDN 2x3_2mm REFOUT C325 HSMB Voltage VCCIO HSMB SELECT 0.1uF Setting NO JUMPER 2.5V JUMPER 1-2 1.8V JUMPER 3-4 1.5V JUMPER 5-6 1.2V C236 C249 22uF 2.2uF TPS51200 0.1uF 5.0V U2 14 12 C475 ENET_DVDD 1uF U47 1 3.3V_REG 3 A 6 C56 10uF ENET_DVDD = 1.0V/0.253A BIAS OUT IN ADJ SHDN GND EP_GND C94 C93 10uF 0.1uF 4 5 2 7 PG_1.0V_FPGA R312 15.0K R307 C484 C483 22uF 2.2uF 29 PG_1.0V_FPGA LTC3025-1 10.0K VLDOIN REFIN GND_PAD PGND GND 1 3 5 S5_VCCIO_HSMB_SEL R151 10.0K 9 1 2 5 6 11 16 15 13 2 1 VIN VIN R91 ADJ R96 10.0K C366 3 5 10uF C41 C342 C42 C343 C40 10uF 10uF 10uF 10uF 10uF S5VCCA_GXB = 3.0V/0.308A S5_VCCA_GXB_OUT 4 VOUT 3 VOUT SHDN NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 10.0K VTT_QDRII_RLD VO VOSNS 11 4 8 5.0V 7 R169 0.003 R53 255K R52 C113 C136 22uF 2.2uF 6 5 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 PGND AGND EP_GND 10 8 17 18.0K Title Size B Date: 7 B 1.0nF S5_VCCA_GXB LT3021EDH 8 C43 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 30 of 1 34 D1.1 8 7 6 5 4 3 2 1 Power 6 - Power & Temperature Monitor 5.37V_MONITOR V6 SENSE_PAD 2 RSNS SNS S5_VCCINT_P V5 1 SENSE_PAD V19 1 RSNS SNS S5_VCCPD_PGM_2.5V S5_VCCPD_PGM SENSE_PAD V23 1 RSNS SNS S5_XCVR_GXB_1.0V 1 S5_VCCINT_N 2 S5_VCC_1.5V 1.5V_VCC 2 V22 SENSE_PAD 2 RSNS SNS SENSE_PAD V21 1 RSNS SNS S5_VCCIO_2.5V 2 SENSE_PAD V24 1 RSNS SNS S5_VCCIO_1.8V S5_1.8V 1 C S5_VCCIO_1.5V S5_1.5V 1 S5_VAR 1 V12 SENSE_PAD 2 RSNS SNS S5_VCCPD_PGM_N S5_VCCIO_1.8V_P S5_VCCIO_1.8V_N 25 26 S5_VCCPD_PGM_P S5_VCCPD_PGM_N 27 28 S5_XCVR_GXB_1.0V_P S5_VCCINT_P S5_VCCINT_N 1 2 S5_VCC_1.5V_P S5_VCC_1.5V_N 3 4 S5_VCC_1.5V_P S5_VCCIO_2.5V_P S5_VCCIO_2.5V_N 5 6 7 8 S5_VCCIO_1.5V_P S5_VCCIO_1.5V_N S5_VCCIO_2.5V_P CH0 CH1 VCC REF+ CH2 CH3 REF- CH4 CH5 F0 C526 10uF 11 12 R357 DNI 19 R369 0 CH6 CH7 SDO SDI SCK CSn CH8 CH9 17 20 18 16 SENSE5_SDO SENSE5_SDI SENSE5_SCK SENSE5_CS0n CH10 CH11 D 5.0V CH12 CH13 2.5V U56 CH14 CH15 NC1 NC2 COM GND 13 14 SENSE5_CS0n SENSE5_SDO SENSE5_SDI SENSE5_SCK 15 2.5V R375 10.0K 14 13 12 11 10 9 8 VCC IO VCC1 IO VCC2 IO VCC3 IO VCC4 NC2 /TS VL IO VL1 IO VL2 IO VL3 IO VL4 NC1 GND 1 2 3 4 5 6 7 SENSE_CS0n SENSE_SDO SENSE_SDI SENSE_SCK 18 18 18 18 MAX3378 S5_VCCIO_2.5V_N 2 E R356 0 9 LTC2418 S5_VCCIO_1.8V_P S5_VCCIO_1.8V_N 2 V28 SENSE_PAD 2 RSNS SNS SENSE_PAD V11 1 RSNS SNS S5_VCCIO_HSMB S5_VCCPD_PGM_P 10 2 V25 SENSE_PAD 2 RSNS SNS SENSE_PAD V26 1 RSNS SNS 21 22 S5_XCVR_GXB_1.0V_P 23 S5_XCVR_GXB_1.0V_N 24 S5_VCC_1.5V_N V29 SENSE_PAD 1 2 RSNS SNS S5_2.5V S5_VCCIO_HSMB_P S5_VCCIO_HSMB_N S5_XCVR_GXB_1.0V_N V20 SENSE_PAD 1 2 RSNS SNS SENSE_PAD V27 1 RSNS SNS C534 0.1uF U52 V17 SENSE_PAD 1 2 RSNS SNS S5_VCCR_GXB D 5.0V 2 C S5_VCCIO_1.5V_P S5_VCCIO_1.5V_N 3.3V 2 S5_VCCIO_HSMB_P R95 R90 R81 R89 0.9V RSNS SNS R370 R339 R358 R371 1 10K 10K 10K 10K S5_VCCINT E S5_VCCIO_HSMB_N 10K 10K 10K 10K SENSE_PAD 3.3V U45 B 6 10 12V J11 1 2 TEMPDIODE_P TEMPDIODE_N 11 11 3 4 DXP DXN OVERTn ALERTn SMBCLK SMBDATA 3.3V R82 TSENSE_FAN_CNTL 15 1 200 22_23_2021 Q14 OVERTEMP B1 A ADD1 ADD0 FDV305N 18 C39 0.1uF 5 13 16 STBYn VCC GND1 GND2 GND3 B 9 11 OVERTEMPn TSENSE_ALERTn 18,24 18 14 12 SENSE_SMB_CLK SENSE_SMB_DATA 18 18 2 7 8 3.3V S5_VCCA_GXB V18 10 9 8 NC1 NC2 NC3 1 U1 C5 0.1uF SENSE_SMB_CLK SENSE_SMB_DATA 7 6 VCC ADR1 ADR0 SCL SDA V1 V2 V3 V4 GND MAX1619 LTC2990 ADDR = 01 ADDR = 10 1 2 3 4 S5_VCCA_GXB_P S5_VCCA_GXB_N 1 RSNS SNS V16 SENSE_PAD 2 RSNS SNS 2 S5_VCCA_GXB_OUT SENSE_PAD 5 FAN_2pin_Conn A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 31 of 1 34 D1.1 8 7 6 5 4 3 2 1 Power 7 - Stratix V GX Power U15K Stratix V GX Power AC17 AC19 AC21 AC23 R17 R19 R21 R23 AA18 AA19 AB19 AA22 AA23 AB17 AB18 AB20 AB21 AB22 T18 T19 T20 T22 T23 U17 U18 U20 U21 U22 V17 V18 V19 V21 V22 V23 W18 W19 W20 W21 W22 Y17 Y18 Y21 Y22 Y23 Y19 E D C VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Auxiliary Supply VCC_AUX VCC_AUX 2.5V VCC_AUX VCC_AUX VCC_AUX VCC_AUX Programmable Power Technology 1.5V VCCPT VCCPT VCCPT VCCPT VCCPT VCCPT S5_VCCA_PLL_2.5V TP1 S5_VCCIO_2.5V AU31 AW33 AJ31 S5_VCC_1.5V AU28 AW30 AJ28 AD19 AE13 AE28 P19 R13 R28 S5_VCCIO_1.8V 0.85V VREF_QDRII_RLD AU22 AW21 AJ23 AW6 AJ8 (2.5V) AW12 AW9 AJ11 AU13 AW15 AJ14 AU19 AW18 AJ16 S5_VCC_1.5V PLL Digital 1.5V VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCD_FPLL VCCD_FPLL AM32 AF20 AL8 H8 P21 H32 AC29 Y29 AC11 Y11 (2.5V) VCCPGM VCCPGM 2.5V 3V/ 2.5V/ 1.8V S5_VCC_1.5V AK9 B Battery Back-up VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL VCCA_FPLL AL32 AG20 AK8 J8 P20 J32 AD29 W29 AD11 W11 VCCIO3B VCCIO3B VREFB3BN0 VCCIO7B VCCIO7B VREFB7BN0 VCCIO3C VCCIO3C VREFB3CN0 VCCIO7C VCCIO7C VREFB7CN0 VCCIO3D VCCIO3D VREFB3DN0 VCCIO7D VCCIO7D VREFB7DN0 VCCIO4A VREFB4AN0 VCCIO8A VCCIO8A VREFB8AN0 VCCIO4B VCCIO4B VREFB4BN0 VCCIO8B VCCIO8B VREFB8BN0 VCCIO4C VCCIO4C VREFB4CN0 VCCIO8C VCCIO8C VREFB8CN0 VCCIO4D VCCIO4D VREFB4DN0 VCCIO8D VCCIO8D VREFB8DN0 S5_VCCIO_HSMB C6 L7 VREF_HSMB R195 10.0K HSMB VREF S5_VCCIO_2.5V A9 C11 L10 VREF_HSMB S5_VCCIO_HSMB A12 A15 L14 R191 10.0K C214 C262 C196 C286 0.1uF 0.1uF 0.1uF 1uF VREF_HSMB A18 C17 L17 S5_VCCIO_1.5V A33 C32 L32 D VREF_DDR3 A30 C29 L29 A24 A27 L25 A21 C23 L22 Version = 1.0 Pin-out C U15P Stratix V GX Transceiver Power S5_VCCR_GXB S5_VCC_1.5V AE35 AA35 U35 AE5 AA5 U5 PLL Analog Configuration 3V/2.5V/1.8V/1.5V/ 1.35V/1.25V/1.2V VCCIO3A VCCIO7A VCCIO3A VREFB7AN0 VREFB3AN0 5SGXA7KF40 S5_VCCA_PLL_2.5V S5_VCCPD_PGM_2.5V AJ9 AL31 AW24 AW27 AJ25 S5_VCCPD_PGM_2.5V AR29 AR32 AR23 AR26 AR10 AR13 AR16 E10 E13 E16 E22 E26 E29 E Stratix V GX I/O Power I/O Pre-Driver VCCPD3AB VCCPD3AB VCCPD3CD VCCPD3CD VCCPD4 3V/ VCCPD4 2.5V VCCPD4 VCCPD7 VCCPD7 VCCPD7 VCCPD8 VCCPD8 VCCPD8 S5_VCCIO_HSMB U15L AG11 AG29 AK20 J20 N11 N29 S5_VCCINT (2.5V) AA24 U24 V24 W24 W25 Y24 AA16 U16 V16 W15 W16 Y16 VCCBAT 1.2V-3V 5SGXA7KF40 Version = 1.0 Pin-out S5_VCCINT V26 V27 W26 W27 Y26 V14 W13 W14 Y13 Y14 A Analog Power TX Buffer Block VCCH_GXBL0 VCCH_GXBL1 VCCH_GXBL2 VCCH_GXBR0 VCCH_GXBR1 VCCH_GXBR2 PCIe Hard IP Digital Power 1.5V 1V/0.85V Core and Periphery S5_VCCINT Analog Power RX VCCR_GXBL0 VCCR_GXBL1 VCCR_GXBL2 VCCR_GXBR0 VCCR_GXBR1 VCCR_GXBR2 Analog Power TX VCCHIP_L VCCT_GXBL0 VCCHIP_L VCCT_GXBL0 VCCHIP_L VCCT_GXBL1 VCCHIP_L0.85V VCCT_GXBL1 VCCHIP_L VCCT_GXBL2 VCCHIP_L 1V/ VCCT_GXBL2 VCCHIP_R 0.85VVCCT_GXBR0 VCCHIP_R VCCT_GXBR0 VCCHIP_R VCCT_GXBR1 VCCHIP_R VCCT_GXBR1 VCCHIP_R VCCT_GXBR2 VCCHIP_R VCCT_GXBR2 Analog Power PCS Power TX Driver, RX Receiver, VCCHSSI_L CDR VCCHSSI_L 0.85V VCCHSSI_L VCCA_GXBL0 VCCHSSI_L VCCA_GXBL1 VCCHSSI_L 3V/VCCA_GXBL2 VCCHSSI_R 2.5V VCCA_GXBR0 VCCHSSI_R VCCA_GXBR1 VCCHSSI_R VCCA_GXBR2 VCCHSSI_R VCCHSSI_R AG34 AC34 W34 AG6 AC6 W6 S5_VCCT_GXB AE33 AF33 AA33 AB33 U33 V33 AE7 AF7 AA7 AB7 U7 V7 B S5_VCCA_GXB AD35 Y35 T35 AD5 Y5 T5 Title 5SGXA7KF40 Version = 1.0 Pin-out Size B Date: 8 7 6 5 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 32 of 1 34 D1.1 8 7 6 5 4 3 2 1 Power 8 - Stratix V GX Ground E U15M U15N Stratix V GX Power A38 AA34 AA38 AA39 AB36 AB37 AC33 AC35 AC38 AC39 AD36 AD37 AE34 AE38 AE39 AF36 AF37 AG33 AG35 AG38 AG39 AH36 AH37 AJ38 AJ39 AK36 AK37 AL38 AL39 AM36 AM37 AN38 AN39 AP36 AP37 AR38 AR39 AT36 AT37 AU38 AU39 AV36 AV37 AW37 AW38 B36 B37 B38 C38 C39 D36 D37 E38 E39 F36 F37 G38 G39 H36 H37 D C B GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND J38 J39 K36 K37 L38 L39 M36 M37 N38 N39 P36 P37 R38 R39 T36 T37 U34 U38 U39 V36 V37 W33 W35 W38 W39 Y36 Y37 A2 AA1 AA2 AA6 AB3 AB4 AC1 AC2 AC5 AC7 AD3 AD4 AE1 AE2 AE6 AF3 AF4 AG1 AG2 AG5 AG7 AH3 AH4 AJ1 AJ2 AK3 AK4 AL1 AL2 AM3 AM4 AN1 AN2 AP3 AP4 AR1 AR2 AT3 AT4 AU1 AU2 AV3 AV4 AW2 AW3 B2 B3 B4 C1 C2 D3 D4 E1 E2 F3 F4 G1 G2 H3 H4 J1 J2 K3 K4 L1 L2 M3 M4 N1 N2 P3 P4 R1 R2 T3 T4 U1 U2 U6 V3 V4 W1 W2 W5 W7 Y3 Y4 AA17 AA21 AB11 AB14 AB23 AB26 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND E U15O Stratix V GX Power GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Stratix V GX Power N5 AB29 AC16 AC18 AC20 AC22 AD10 AD13 AD25 AD28 AD31 AF12 AF15 AF18 AF21 AF24 AF27 AF30 AF9 AH11 AH14 AH17 AH20 AH23 AH26 AH29 AH32 AH35 AH5 AH8 AK10 AK13 AK16 AK19 AK22 AK25 AK28 AK31 AK34 AK7 AM12 AM15 AM18 AM21 AM24 AM27 AM30 AM33 AM6 AM9 AP11 AP14 AP17 AP20 AP23 AP26 AP29 AP32 AP35 AP5 AP8 AT10 AT13 AT16 AT19 AT22 AT25 AT28 AT31 AT34 AT7 AV12 AV15 AV18 AV21 AV24 AV27 AV30 AV33 AV6 AV9 B12 B15 B18 B21 B24 B27 B30 B33 B6 B9 D11 D14 D17 D20 D23 D26 D29 D32 D35 D5 D8 F10 F13 F16 F19 F22 F25 F28 F31 F34 F7 H12 H15 H18 H21 H24 H27 H30 H33 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND H6 H9 K11 K14 K17 K20 K23 K26 K29 K32 K35 K5 K8 M10 M13 M16 M19 M22 M25 M28 M31 M34 M7 P12 P15 P18 P24 P27 P30 P33 P6 P9 R18 R20 R22 T11 T14 T17 T21 T26 T29 T32 T8 U19 U23 V10 V13 V15 V20 V25 V28 V31 W17 W23 Y12 Y15 Y25 Y27 Y30 Y9 D U15S Stratix V GX Power AA11 AA20 AA32 AA8 AB32 AB8 AE32 AE8 AF32 AF8 AJ35 AJ5 AL35 AL5 AL9 AN35 AN5 AR35 AR5 AT5 AU35 AU5 B35 B5 C35 C5 E35 E5 F35 F5 G35 G5 H35 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND H5 J35 J5 L35 L5 M35 M5 N35 P35 R33 R34 R35 R5 U32 U8 V11 V12 V30 V32 V8 V9 W10 W12 W28 W30 W31 W32 W8 W9 Y10 Y28 Y32 Y8 C B 5SGXA7KF40 5SGXA7KF40 5SGXA7KF40 5SGXA7KF40 Version = 1.0 Pin-out Version = 1.0 Pin-out Version = 1.0 Pin-out Version = 1.0 Pin-out A A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 Title Size B Date: 8 7 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 33 of 1 34 D1.1 8 7 6 5 4 3 2 1 Decoupling Place 6 vias minimum on each X2Y cap. E E S5_VCCINT C156 C506 C331 C340 C363 C442 C513 C12 C118 C116 C15 C283 C502 C216 C512 C117 C14 C524 C61 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF S5_VCC_1.5V FPGA VCCD PLL & VCCPT S5_VCCA_PLL_2.5V C260 C376 C317 C359 C335 C315 C316 C336 C360 C287 C319 C153 C480 C482 C154 C481 C313 C231 C377 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF C151 D C241 C341 0.1uF 100uF C503 C152 C158 22nF 47nF D 10nF 0.1uF S5_VCC_1.5V C318 4.7uF C378 4.7uF C357 4.7uF C358 4.7uF C333 4.7uF C320 4.7uF C337 4.7uF C361 C334 4.7uF C314 4.7uF 4.7uF C288 C290 4.7uF 4.7uF C291 4.7uF C289 C263 4.7uF 4.7uF C266 C264 4.7uF C265 4.7uF 4.7uF C409 4.7uF C413 C112 C338 C8 4.7uF 330uF 4.7uF 1uF S5_VCC_1.5V S5_VCCR_GXB C S5_VCCIO_1.5V FPGA 1.5V VCCIO S5_VCCIO_1.8V FPGA 1.8V VCCIO S5_VCCIO_2.5V FPGA 2.5V VCCIO C356 C355 0.1uF 0.47uF 100uF C374 C439 C380 C215 C381 22nF 47nF 0.1uF 0.47uF 22uF S5_VCCA_GXB S5_VCCIO_HSMB C157 C505 1uF C410 S5_VCCT_GXB C293 C339 C182 C424 C213 C284 1uF 47nF 22uF 22nF 0.22uF 0.1uF C155 1uF C441 C45 4.7uF 330uF C353 1uF 47nF C504 22nF C282 C44 1uF C440 C46 4.7uF 330uF 47nF C198 C197 4.7uF 0.1uF C C37 22nF S5_VCCR_GXB S5_VCCT_GXB S5_VCCPD_PGM_2.5V B C13 C375 C332 C240 C425 C372 C242 C230 C267 C292 C362 C379 C412 C422 C423 C373 C321 C261 C411 C285 100uF 0.22uF 0.22uF 0.1uF 47nF 47nF 0.01uF 0.01uF 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF 4.7nF 22nF 0.01uF 2.2uF A SCREW1 SCREW3 STANDOFF1 SPACER1 SCREW2 SCREW4 STANDOFF2 SPACER2 SCREW5 STANDOFF3 SCREW6 STANDOFF4 B VREF_QDRII_RLD VREF_DDR3 C106 C137 C105 C119 C188 C403 C311 C497 C546 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF PCB1 Title Size B Date: 8 7 A Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121 6 5 4 3 Stratix V GX FPGA Development Kit Board Copyright (c) 2011, Altera Corporation. All Rights Reserved. Document Number 150-0320202-D1 Monday, June 03, 2013 2 Rev (6XX-44143R) Sheet 34 of 1 34 D1.1