View detail for WC130901

Product Change Notification
Product Change Notification Number: WC130901
Notification Date: March 14, 2013
Title: Die Revision Change for ATxmega16D4 / ATxmega32D4
Product Identification:
ATxmega16D4-MH
ATxmega16D4-MHR
ATxmega32D4-MH
ATxmega32D4-MHR
Reason for
Change:
Material / Composition
Design / Firmware
Manufacturing Location
Processing / Manufacturing
Logistics
Quality / Reliability
Change Description:
This notification is to advice our customers that Atmel will introduce new revisions of the AVR microcontroller
products listed above. The new revisions are package and pin compatible to the existing revisions. They are
introduced in order to remove errata and enhance the product. Actual devices changes are minimal, but for
your reference they are listed here together with enhancements that are a pure superset of existing functions.
Samples are only available in bulk and can be ordered through Atmel Sample Centre by logging on to
https://samples.atmel.com/scripts/samplecenter.dll?atmel?cmd=menu
Specific ordering codes for new die revision samples only are shown in the table below, and are available for
sample orders only until the proposed first shipment date. For all production orders, only standard existing
ordering codes will be accepted.
Part number
Ordering code for samples
ATxmega16D4-MH
ATxmega16D4-MHK
ATxmega32D4-MH
ATxmega32D4-MHK
Note that the K in sample ordering codes will not be marked on the package.
Changes
The new revision change the following:
•
•
•
•
•
•
•
•
•
Reduced current consumption in Active and Idle modes
Increased typical current consumption in Power-down and Power-save modes
Increased maximum ADC sample rate
Brown-Out Detection (BOD) levels.
The BOD is forced on only during selected NVM programming commands
Chip erase time during programming
Access to unused registers removed
32kHz internal ULP oscillator frequency
Bonding wire material has changed from gold to copper
• The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level
input and output voltage limits reflect or exceed this specification.
Atmel Norway • Vestre Rosten 79 7075 Tiller • NORWAY
QF-8004 Rev. 09
09/03/2012
Page 1 of 6
PCN NO. WC130901
Page 2 of 6
New configuration options and functions
The new revision includes new configuration options and functions that are a superset of existing functions.
This means that existing software for the existing device revisions will work on the new revision without
changing existing configuration or enabling new functions.
See Appendix 1 for more details on changes.
See Appendix 2 for more details on added functions.
Identification Method to Distinguish Change:
For packages where space allows for die ID to be part of marking, new revision material is identified to
359P5I.
Qualification Data:
Available
Will be available (mm/dd/yr):
Not Applicable
Samples:
Available
Will be available (mm/dd/yr):
Not Applicable
Quantifiable Impact on Quality & Reliability:
None
Proposed First Ship Date*: June 14, 2013
*The Proposed First Ship Date is the forecasted date that a customer may expect to receive changed product. This is determined by
the estimated date of inventory depletion on the PCN issue date. This may be affected by fluctuations in supply and demand.
Consequently, although customers should be prepared to receive changed product on this date, Atmel will continue to ship pre-changed
product until a time in which inventory has been depleted. This may result in pre-changed product being shipped to customers after this
forecasted date.
Atmel Contact: Please contact your Atmel Sales Representative or Distributor for additional information
(when replying via e-mail please include PCN number in subject line).
Information provided herein is in connection with Atmel products and this information is provided “AS IS”. Atmel assumes no
responsibility for any errors that may appear in this document. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Atmel’s Terms and Conditions of Sale for such products,
Atmel assumes no liability whatsoever, and Atmel disclaims any express or implied warranty, including liability or warranties relating to
fitness for a particular purpose, merchantability, or non-infringement of any patent, copyright or other intellectual property right. Atmel
products are not intended for use in a product or system intended to support or sustain life which, if it fails, can be reasonably expected
to result in significant personal injury. Atmel may make changes to specifications and product descriptions at any time, without notice.
CUSTOMER ACKNOWLEDGEMENT OF RECEIPT: Atmel requests you acknowledge receipt of this PCN.
Please complete and email to [email protected] and the Atmel Contact listed above. In your
acknowledgement, you can grant approval or request additional information. Atmel will deem this change
accepted unless specific conditions of acceptance are provided in writing within 30 days from the
date of this notice.
Company:
Name:
Title:
Date:
Email Address:
Location:
Comments:
Atmel Norway • Vestre Rosten 79 7075 Tiller • NORWAY
QF-8004 Rev. 09
09/03/2012
PCN NO. WC130901
Page 3 of 6
Appendix 1: Change Description Details
Reduced current consumption Active and Idle mode
The table below lists the typical and maximum current consumption in the existing and new revision.
Existing revisions
Parameter
Units
Min
32kHz, Ext. Clk
Active power
consumption
1MHz, Ext. Clk
2MHz, Ext. Clk
32MHz, Ext. Clk
32kHz, Ext. Clk
1MHz, Ext. Clk
Idle power
consumption
2MHz, Ext. Clk
Max
Min
Max
68
40
VCC = 3.0V
145
80
VCC = 1.8V
260
200
VCC = 3.0V
540
410
VCC = 1.8V
460
600
350
600
0.96
1.4
0.75
1.4
9.8
12
7.5
12
VCC = 3.0V
μA
VCC = 1.8V
2.4
2.0
VCC = 3.0V
3.9
2.8
VCC = 1.8V
62
42
VCC = 3.0V
118
85
VCC = 1.8V
125
225
85
225
240
350
170
350
3.8
5.5
2.7
5.5
T = 25°C
0.1
1.0
0.1
1.0
1.2
4.5
2.0
4.5
1.3
3.0
1.4
3.0
2.4
6.0
3.0
6.0
RTC from ULP clock,
WDT and sampled BOD
enabled, T = 25°C
RTC from 1.024kHz low
power 32.768kHz TOSC,
T = 25°C
RTC from low power
32.768kHz TOSC, T = 25°C
VCC = 3.0V
Current through RESET pin
substracted
VCC = 1.8V
1.2
1.5
VCC = 3.0V
1.3
1.5
VCC = 1.8V
0.6
2.0
0.6
2.0
VCC = 3.0V
0.7
2.0
0.7
2.0
VCC = 1.8V
0.8
3.0
0.8
3.0
VCC = 3.0V
1.0
3.0
1.0
3.0
VCC = 3.0V
320
Atmel Norway • Vestre Rosten 79 7075 Tiller • NORWAY
QF-8004 Rev. 09
09/03/2012
Typ
VCC = 1.8V
WDT and sampled BOD
enabled, T = 85°C
Reset power
consumption
Typ
32MHz, Ext. Clk
T = 85°C
Power-down power
WDT and sampled BOD
consumption
enabled, T = 25°C
Power-save power
consumption
New revision
Condition
300
mA
μA
PCN NO. WC130901
Page 4 of 6
Increased ADC maximum samples rate
The maximum ADC clock frequency and sample rate is increased, as shown in the table below.
Existing revisions
New revision
Parameter
Units
Min
Typ
Max
Min
Typ
Max
ADC clock frequency
100
1400
100
1800
kHz
ADC samples rate
14
200
16
300
kSPS
Reduced Analog Comparator propagation delay
The Analog Comparator propagation delay is reduced, as shown in the table below.
Condition
Existing revisions
New revision
Parameter
Units
Min
Typ
Max
90
Propagation delay
VCC = 3.0V, T=85°C
30
Propagation delay
VCC = 1.6V-3.6V,
T=25°C
30
Min
Typ
Max
16
90
16
ns
ns
Brown-Out Detection (BOD) levels.
The table below lists the BOD levels in the existing revisions, and the expected BOD levels in the new revision.
Existing revisions
New revision
Parameter
BOD level 0 falling Vcc
Min
Typ
Max
Min
Typ
Max
Units
1.60
1.62
1.72
1.50
1.62
1.75
V
BOD level 1 falling Vcc
1.8
1.8
BOD level 2 falling Vcc
2.0
2.0
BOD level 3 falling Vcc
2.2
2.2
BOD level 4 falling Vcc
2.4
2.4
BOD level 5 falling Vcc
2.6
2.6
BOD level 6 falling Vcc
2.8
2.8
BOD level 7 falling Vcc
3.0
3.0
The BOD forced on only during selected NVM programming commands
For existing revisions the BOD is forced on for all Non-Volatile Memory (NVM) programming. For the new revision, the
BOD is only forced on during chip erase and when the PDI is enabled. For other NVM programming operations, the
POR threshold voltage (VPOT+) is the limit for aborting.
Atmel Norway • Vestre Rosten 79 7075 Tiller • NORWAY
QF-8004 Rev. 09
09/03/2012
PCN NO. WC130901
Page 5 of 6
Chip erase time during programming
For the existing revisions the chip erase time is about 40ms, while in the new revision this is increased to 45ms for
ATxmega16D4 and 50ms for ATxmega32D4.
Device
Existing revision
Chip erase time
New revision
Chip erase time
ATxmega16D4
40 ms
45 ms
ATxmega32D4
45 ms
50ms
32kHz internal ULP oscillator frequency
The frequency of the 32kHz internal ULP oscillator is increased to match its nominal frequency with guaranteed accuracy.
Existing revisions
Parameter
New revision
Condition
Units
Min
Factory calibrated frequency
Factory calibration accuracy
Typ
Max
Min
26
VCC = 3.0V, T= 85°C
Accuracy
Typ
32
kHz
na
na
-12
12
na
na
-30
30
Removed registers
The below register bits have been removed as they are unused.
Register Name
Register Bit
Function
COMP0
COMP[7:0]
Oscillator Compare Register 0
Atmel Norway • Vestre Rosten 79 7075 Tiller • NORWAY
QF-8004 Rev. 09
09/03/2012
Max
%
PCN NO. WC130901
Page 6 of 6
Appendix 2: Added Functions
Clock System
• Alternate pin location for TOSC1 and TOSC2 pins for 32.768 kHz crystal connection on devices with shared TOSC and
XTAL location today.
• A divide by two option for the PLL output.
• PLL lock failure detection with optional non maskable interrupt for improved safety and robustness.
• Non-prescaled Real Time Counter clock source options: External clock from TOSC1, 32.768 kHz from TOSC, and the
32.768 kHz from the 32.768 kHz Internal Oscillator.
• Higher drive option for external crystal oscillator to support higher load crystals.
• The 32 MHz internal oscillator can be tuned to run at any frequency between 30 MHz and 55 MHz.
•
•
•
•
I/O Ports
Alternate pin locations for Timer/Counter 0 Compare Channels, USART0 and SPI.
Alternate pin locations for the Peripheral Clock and Event output functions.
The Real Time Counter clock can be output to a port pin.
Any Event Channel can be output to a port pin.
Two Wire Interface
• The SDA Hold time can be increased and configured in order to be SMBus compliant.
•
•
•
•
•
Analog to Digital Converter
Automatic input channel scan.
VCC/2 voltage reference option.
1/2x (divide by two) gain stage setting.
Internal Ground can be used as negative input in differential mode with and without gain.
Sample time is configurable
Analog Comparator
• Analog Comparator 1 can be output on a port pin.
• Added constant current source.
CRC16/CRC32 Generator
• A CRC16/CRC32 Module that supports CRC16 (RC-CCITT) and CRC-32 (IEEE 802.3).
16-bit Timer / Counter 0
• Split mode that enable a system of two 8-bit Timer/Counters with 4 PWM channels each.
AWeX
• Hi-Res+ option to allow PWM resolution to be increased with 8x (3-bit)
Power Management
• Possibility to enable sequential start of the internal modules used for ADC and Analog Comparator in order to reduce the
peak start-up current.
Atmel Norway • Vestre Rosten 79 7075 Tiller • NORWAY
QF-8004 Rev. 09
09/03/2012