KeyStone Training Network Coprocessor (NETCP) Overview Agenda • • • • • What is NETCP? Purpose of the NETCP NETCP Block Diagram Internet Protocol Classification Levels Communication with the NETCP NETCP Subsystem Overview • • • • • What is NETCP? Purpose of the NETCP NETCP Block Diagram Internet Protocol Classification Levels Communication with the NETCP What is the Network Coprocessor (NETCP)? Application-Specific Coprocessors Memory Subsystem MSM SRAM 64-Bit DDR3 EMIF MSMC Debug & Trace Boot ROM Semaphore C66x™ CorePac Power Management PLL L1 P-Cache x3 L1 D-Cache L2 Cache EDMA 1 to 8 Cores @ up to 1.25 GHz x3 TeraNet HyperLink Multicore Navigator S w it c h E t he r ne t S w itc h S GM I I x2 x4 SR I O Ap pli ca tio nSpe ci fic I/ O S PI U AR T x2 PC I e I2 C O t he r s Queue Manager Packet DMA Security Accelerator Packet Accelerator Network Coprocessor Network Coprocessor consists of the following modules: • Packet Accelerator (PA) • Security Accelerator (SA) • Ethernet Subsystem • Packet DMA (PKTDMA) Controller Purpose of the Network Coprocessor • Motivation behind NETCP: – Use hardware accelerators to do L2, L3, and L4 processing and encryption that was previously required to be done in software • Goals for both Packet Accelerator and Security Accelerator: – Offload DSP processing power – Improve system integration – Allow cost savings at the system level – Expand DSP usability within current products – Allow DSP usage in new product areas • Security Key applications: – IPSec tunnel endpoint (e.g. LTE eNB, ...) – Secure RTP (SRTP) between gateways – Air interface (3GPP, Wimax) security processing NETCP Block Diagram Config 32-bits 32-bit VBUSP TeraNet SCR CPU/3 CFG TeraNet SCR Pass 1 LUT PKTDMA_VBUSM_TXRX CDE PKTDMA Controller 128 bits Pass 1 LUT CP_ACE Security Unit Switch Status INTS SGMII 0 SERDES CPSGMII SGMII 1 SERDES CPSGMII CPMDIO MDIO 0 INTS 3-Port Ethernet Switch CDE Pass 1 LUT CDE Pass 2 LUT Timer16 1 PDSP+ 2 Timer16 3 PDSP+ 3 CDE PDSP+ 4 CDE PDSP+ 5 CDE PDSP+ 6 PA Stats INTD Timer16 2 32-bit VBUSP TeraNet SCR Streaming Interface Switch CPU/3 Main TeraNet SCR PDSP+ 1 Timer16 4 Timer16 5 Timer16 6 PDSP Scratchpad RAM 1 PDSP Scratchpad RAM 2 . : PDSP Scratchpad RAM n Packet DMA in NETCP FFTC (B) FFTC (A) Queue Manager Subsystem Queue Manager PKTDMA PKTDMA 0 1 2 3 4 5 SRIO PKTDMA ... 8192 AIF PKTDMA Network Coprocessor PKTDMA PKTDMA Internet Protocol Classification Layers • • • Layer 2 (L2): Media Access Control (MAC) Layer – IEEE 802.3 standard Layer 3 (L3): Internet Layer – Internet Protocol Version 4 (IPv4) – Internet Protocol Version 6 (IPv6) – Custom L3 Classification Layer 4 (L4): Transport Layer – User Datagram Protocol (UDP) – Transmission Control Protocol (TCP) – Custom L4 Classification Example Packet L2 L3 L4 Data MAC IPv4 UDP Payload Communication with the NETCP NETCP relies on QMSS and PKTDMA to communicate with the CorePac. • TX Queue Mapping – Q640: PDSP1 – Q641: PDSP2 – Q642: PDSP3 – Q643: PDSP4 – Q644: PDSP5 – Q645: PDSP6 – Q646: SASS0 – Q647: SASS1 – Q648: Switch • RX Queues – Can use any general purpose queues (Q864Q8191) – Can also use other special purpose queues (e.g. 704-735) PKTDMA TX channels mapped to QMSS PA TX queues For More Information • For more information, refer to the Network Coprocessor (NETCP) User Guide. http://www.ti.com/lit/SPRUGZ6 • For questions regarding topics covered in this training, visit the support forums at the TI E2E Community website.