8 6 7 2 3 4 5 1 REVISIONS D DESCRIPTION DATE APPROVED D DRVDD KP_VDDIO REV R106 0 R107 0 AD9644BCPZ-155 DRVDD PDWN MODE DUT_CSB DUT_SCLK DUT_SDIO DGND DUT LAYOUT: DECOUPLING QUANTITY MAY VARY LAYOUT DEPENDING VCMA DNC DNC PDWN DNC CSB_N SCLK SDIO DRVDD DRVDD DRGND DNC 36 35 34 33 32 31 30 29 28 27 26 25 U101 VCMA DNI VCMB AVDD DNC AVDD CLK_POS CLK_NEG AVDD SYNC AVDD DRGND DRVDD DNC PAD 48 47 46 45 44 43 42 41 40 39 38 37 VIN+B VIN-B PAD AVDD AVDD VIN_NEG_B VIN_POS_B AVDD AVDD AVDD AVDD VIN_POS_A VIN_NEG_A AVDD AVDD C DSYNC_NEG_B DSYNC_POS_B DRVDD DRGND DOUT_NEG_B DOUT_POS_B DOUT_NEG_A DOUT_POS_A DRGND DRVDD DSYNC_NEG_A DSYNC_POS_A VIN-A VIN+A SYNC_A+ 13 14 15 16 17 18 19 20 21 22 23 24 AVDD DRVDD DNI DRVDD SYNC_A- C104 0.1UF DATA_A+ DATA_ADATA_B+ DATA_B- C107 1UF C101 0.1UF C102 0.1UF C103 0.1UF C121 1UF C122 1UF C SYNC_B+ DGND DRVDD R109 0 DNI AVDD SYNC_B- DGND C109 0.1UF C110 0.1UF C111 0.1UF C112 0.1UF C113 0.1UF C114 0.1UF C115 0.1UF C116 0.1UF C117 1UF C118 1UF C119 0.1UF C120 0.1UF 1 2 3 4 5 6 7 8 9 10 11 12 AGND R108 0 SYNC VCMB C105 0.1UF DRVDD VCMA CLK+ CLK- VCMB AGND AVDD C106 0.1UF DGND R110 0 AGND DNI AGND B B SYNC J101 1 R101 0 2 3 4 5 AGND R105 49.9 2.0K R102 AVDD DNI C123 SYNC MODE 1 2 0.1UF R103 2.0K AVDD P102 MODE P101 PDWN AGND 1 2 PDWN DNI AGND AGND A A AN A LOG DEV CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> AD9644 CUSTOMER BOARD DESIGN VIEW REV DRAWING NO. <DESIGN_VIEW> A 9644CE01 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 - 2 SCALE NONE SHEET 1 1 OF 6 8 6 7 2 3 4 5 1 REVISIONS 3 4 6 5 CR202 A C PGND AGND DESCRIPTION DATE APPROVED POWER VIN 261 LNJ314G8TRA (GREEN) 2 R201 D 1 SK33A-TP CR201 A C N PJ-202A 10UF C201 P 1 2 3 F201 1 2 1.1A CR203 P201 REV FL201 BNX016-01 D E212 1 2 3P3V_DIGITAL N U201 10UF ADP1708ARDZ-R7 C231 100MHZ 0.1UF C232 P AGND P202 P 100MHZ Z5.531.3625.0 DGND AGND DGND E214 1 2 AGND 10UF 100MHZ DRVDD N 2 PAD 5V_SUPPORT E213 1 2 0.1UF C234 5 6 DGND 1 2 3 4 5 6 C233 E201 1 2 4.7UF C202 4.7UF 10K 1.91K R202 R203 EN SENSE IN OUT IN2 OUT2 ADJ GND1 PAD C203 1 7 3 4 8 VIN 100PF R216 0 DNI AGND L201 E210 1 2 R217 0 JP204 1 2 0 100MHZ SS GND1 PAD 2 PAD SW2 22 21 20 19 PGND1 PGND2 PGND3 PGND4 2.2UH PGOOD2 COMP2 SW3 SW4 12 7 18 17 R213 13K C215 R215 TBD0603 C220 22UF PAD DNI AGND 100PF AGND R218 0 DNI AGND 100MHZ 10UF P 10UF TO EVALUATE SHARING OF AVDD AND DVDD GROUND PLANE TIES DRVDD 100MHZ AGND E209 1 2 RS202 0 RS203 0 RS204 0 RS210 0 RS211 0 DNI AGND VOUTB E211 1 2 RS201 0 DGND AGND C219 TBD0603 B DGND C221 22UF DNI 0.01UF C216 0.1UF C240 N C214 100MHZ E207 1 2 4.7UF 2200PF AVDD DNI 4.7UF 2 PAD ADP1706ARDZ-1.8-R7 U205 1 EN 7 SENSE 3 5 IN OUT 4 6 IN2 OUT2 8 JP203 1 2 0 VOUTA L202 RS205 0 RS206 0 RS207 0 RS208 0 RS209 0 100MHZ R219 0 DGND A AGND R221 EN2 2.2UH 0 R220 TBD0603 1.00K DNI R222 VIN SS GND1 PAD E205 1 2 C227 JP202 1 2 0 C213 29 PGOOD1 2 COMP1 24 SW1 23 100MHZ AGND C230 R208 100K R214 10.5K VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 U206 PAD A 0.01UF R212 15K C218 AGND 27 26 25 14 15 16 8 0.01UF C217 R211 15K SCFG FREQ SYNC_CLKOUT OPCFG EN1 V1SET FB1 SS1 EN2 V2SET FB2 SS2 GND 1 4 3 R241 SW_FREQ 5 6 0 28 EN1 31 VOUTA 32 30 EN2 13 10 VOUTB 9 11 ADP2114_PRELIM AGND R210 4.64K S2A-TP 0.01UF 1.00K R205 VDD R209 27K S2A-TP JP201 1 2 0 AGND AGND OUT5 CR206 A C E206 1 2 10 R207 100K 3P3V_ANALOG AGND AGND 0 DNI CR205 A C 4.7UF C229 EN1 E216 1 2 Z5.531.3425.0 ADP1706ARDZ-1.8-R7 U204 1 EN 7 SENSE 3 5 IN OUT 4 6 IN2 OUT2 8 C228 R204 AGND 1 2 3 4 DNI 100MHZ OPTIONAL SWITCHING SUPPLY 1UF AGND R206 C211 22UF C212 C210 22UF 100MHZ 0.01UF 2 3P3V_DIGITAL 4.7UF C226 GND E208 1 2 C225 4 VOUT 5 4.7UF EN NC E204 1 2 C209 3 0.01UF DNI 4.7UF C208 C207 VIN P203 DGND VIN 10UF N P N 100MHZ U203 ADP150AUJZ-3.3-R7 1 5V_SUPPORT 0.1UF C238 DNI AGND E215 1 2 C237 2 C 100MHZ C239 GND AGND 3P3V_ANALOG 100MHZ 4 VOUT 5 E203 1 2 EN NC E202 1 2 4.7UF 3 0.01UF C204 4.7UF C205 DNI C VIN C206 1 S2A-TP B C236 U202 ADP150AUJZ-3.3-R7 CR204 A C C235 100MHZ 0.1UF P AVDD 100MHZ C223 22UF C224 22UF AN A LOG DEV CES DNI C222 TBD0603 AGND THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR AGND DNI IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, AGND SCHEMATIC <DRAWING_TITLE_HEADER> AD9644 CUSTOMER BOARD DESIGN VIEW <DESIGN_VIEW> OF ANALOG DEVICES. OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 7 6 A 9644CE01 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS 8 REV DRAWING NO. 5 4 3 - 2 SCALE NONE SHEET 2 1 OF 6 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED ANALOG INPUT D C303 PASSIVE PATH A AMP_IN_A+ AMP_OUT_A+ DNI R309 0 DNI 3 DNI 6 DNI AGND AGND DNI J302 1 R305 R306 0 0 R304 49.9 1 4 ADT1-1WT+ T301 T303 3 4 MABA-007159-000000 T302 6 T304 3 AGND 0.1UF 2 AGND 33 0 R313 36 C301 DNI VCMA L301 100NH VIN-A AGND R314 36 C306 0.1UF R307 0 R319 0.1UF 1 4 ADT1-1WT+ DNI R310 0 DNI C DNI SEC DNI R315 R316 R320 33 0 R312 0 SHARE PADS AGND VIN+A R318 49.9 DNI C AGND C304 AMP_IN_A- 8.2PF DNI PRI 4 2 VCMA 2 3 4 5 1 PRI AGND 5 C305 8.2PF R308 0 R317 49.9 R311 0 C302 R301 49.9 2 3 4 5 MABA-007159-000000 0 3 0 SEC R303 SHARE PADS 5 AIN_A R302 AGND DNI 1 J301 1 8.2PF D AMP_OUT_A- LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER AGND AMP_OUT_B+ DNI DNI AGND J304 1 2 3 4 5 2 VCMB AGND DNI R324 49.9 DNI R325 R326 0 0 DNI B 1 4 ADT1-1WT+ 5 T306 1 PRI SEC 4 3 T307 MABA-007159-000000 R331 0 C311 0.1UF DNI 3 6 T308 2 AGND R328 0 R330 0 SHARE PADS AGND R339 33 0 R333 36 C307 DNI VCMB L302 100NH VIN+B AGND 0.1UF AGND R335 0.1UF 1 4 ADT1-1WT+ R334 36 C312 DNI DNI R337 49.9 8.2PF 3 T305 6 3 DNI AGND DNI 4 R327 0 SEC R321 49.9 2 3 4 5 MABA-007159-000000 0 0 PRI AIN_B R322 1 1 SHARE PADS 5 J303 AGND DNI R329 0 R323 C308 B C309 PASSIVE PATH B AMP_IN_B+ 8.2PF NOTE: CUTS REQ'D FOR 2ND TRANSF USE DNI R336 R340 33 0 R332 0 VIN-B R338 49.9 AGND 8.2PF C310 AMP_IN_B- AMP_OUT_B- A LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER A AGND AN A LOG DEV CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> AD9644 CUSTOMER BOARD DESIGN VIEW REV DRAWING NO. <DESIGN_VIEW> A 9644CE01 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 - 2 SCALE NONE SHEET 3 1 OF 6 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED ACTIVE PATH - CHANNEL A AND B 5V_SUPPORT 5V_SUPPORT AGND AGND 5V_SUPPORT 1 2 ENB_B 5V_SUPPORT 1 2 0 AGND AGND 0.1UF C412 10UF C414 C411 0.1UF C408 0.1UF 1UH P402 L402 ENB_A 5V_SUPPORT R402 1.1K P401 D 1UH R401 1.1K R409 AGND L401 AGND 0.1UF AGND C407 0.1UF C410 10UF C413 D C409 0.1UF AGND THESE RLCS ARE PLACE HOLDERS... PLACE CORRECT VALUES & COMPONENTS... AGND DNI DNI AGND 3 0.1UF TC3-1T+ 4 0 C403 12 IPB_N 0 0.1UF DNI 11 IPB_P GNDA 21 28 TC3-1T+ 4 AGND 0 DNI 3 AGND AMP_IN_A- 16 18 15 17 13 20 PAD AD8376ACPZ AGND AGND C406 C418 22PF C417 2.7PF DNI DNI L404 L406 100NH 100NH AMP_OUT_B+ 0.001UF DNI DNI C DNI 0 DNI C421 0.001UF L409 L411 100NH 100NH DNI DNI AMP_OUT_A- DNI 0.1UF DNI DNI AGND R414 0 C416 AMP_OUT_B- THESE RLCS ARE PLACE HOLDERS... PLACE CORRECT VALUES & COMPONENTS... DNI R408 130 1 R407 100NH 5V_SUPPORT DNI 0.1UF 100NH DNI DNI DNI AGND 2 6 OPB1_N OPB2_N OPB1_P OPB2_P GNDB PAD DNI 0.1UF C404 T402 23 25 24 26 C405 R406 AMP_IN_A+ OPA1_N OPA2_N OPA1_P OPA2_P 29 IPA_N 30 IPA_P R404 AMP_IN_B+ R411 C420 C AGND L405 DNI 1UH T401 R405 130 0.001UF L403 R412 300 L408 DNI 2 DNI C415 0 C401 ENBB B0 B1 B2 B3 B4 0 R413 0.1UF 1 R410 1UH 6 U401 L407 0 DNI 19 10 9 8 7 6 27 0.1UF R403 AMP_IN_B- ENB_B AD8376_B0 AD8376_B1 AD8376_B2 AD8376_B3 AD8376_B4 14 C419 C402 ENB_A AD8376_A0 AD8376_A1 AD8376_A2 AD8376_A3 AD8376_A4 22 31 32 1 2 3 5 0.1UF 4 VCMA VCMB VCCB VCCA ENBA A0 A1 A2 A3 A4 R426 300 R415 0 DNI C422 DNI DNI DNI B C424 22PF C423 2.7PF B L412 L410 AMP_OUT_A+ 100NH 0.001UF 100NH DNI DNI DNI THIS HEADER IS USED TO SET THE GAIN OF THE AD8376 THIS HEADER IS USED TO SET THE GAIN OF THE AD8376 5V_SUPPORT R416 10K R417 10K R418 10K R419 10K 5V_SUPPORT R420 10K R421 10K R422 10K R423 10K R424 10K J401 AD8376_A0 A 1 2 3 4 5 6 7 8 9 10 AD8376_A1 AD8376_A2 AD8376_A3 AD8376_A4 AD8376_B0 AD8376_B1 AD8376_B2 AD8376_B3 AD8376_B4 R425 10K J402 10 9 8 7 6 5 4 3 2 1 A AN A LOG DEV CES TSW-105-08-G-D TSW-105-08-G-D THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR AGND AGND IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> AD9644 CUSTOMER BOARD DESIGN VIEW REV DRAWING NO. <DESIGN_VIEW> A 9644CE01 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 - 2 SCALE NONE SHEET 4 1 OF 6 8 6 7 2 3 4 5 1 REVISIONS REV OUT0_N R506 C510 C509 0.001UF TBD0402 0.001UF R507 AGND Y502 VCC 1 TRISTATE CTRL 2 R555 1K 0 0 R547 0.1UF 80MHZ REF CLK 8 DOUT+ 7 0 R525 0.1UF C516 0.1UF R511 100 GND AGND 8.2PF C R517 R518 10K 10K AGND 3.3V_OUT_2-5 1 J501 3.3V_OUT_2-5 OUT5 3.3V_OUT_2-5 OUT4_N OUT4 1.8V_OUT_0-5 USB_CSB2 CYP_SCLK CYP_SDI CYP_SDO 13 14 15 16 17 18 19 20 21 22 23 24 AGND L506 DRVDD B 1.8V_OUT_0-5 3.3V_PLL2 3P3V_ANALOG R540 24.9 1UH L503 E501 1 2 3.3V_PLL1 1UH 45OHMS CLK0.1UF R549 DNI 3P3V_DIGITAL L504 E502 1 2 3.3V_OUT_0-1 1UH L505 45OHMS 1UH 3.3V_OUT_2-5 CLK_OUT- 10UF C533 DNI 0 AGND AGND TP505 REFCLK2AGND REFCLK2+ REFCLKREFCLK+ OUT3 A R551 REFCLK1- 0 R552 REFCLK1+ SCHEMATIC 0 R553 DNI R526 DNI REFCLK- 0 R527 DNI REFCLK+ AN A LOG DEV CES REFCLK2X+ 0 R554 DNI THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. REFCLK2X- IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, 0 <DRAWING_TITLE_HEADER> AD9644 CUSTOMER BOARD DESIGN VIEW <DESIGN_VIEW> OF ANALOG DEVICES. A 9644CE01 SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 6 REV DRAWING NO. OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS 0 7 LNJ314G8TRA (GREEN) 0 4 FIN1017M OUT3_N 8 200 NC7WZ16P6X TP503 1 TP504 CR502 2 3 0 R550 DNI 0 GND AGND R514 1 R543 100 2 DNI R534 0 DOUT- R524 2 DIN GND 4 10UF C527 MABA-007159-000000 AGND C530 Y2 U503 VCC 3 OUT 0 R541 DNI 0.1UF C531 0.1UF 1 3 A2 LNJ314G8TRA (GREEN) 10UF C534 3 CLK_IN+ 10K C536 0.1UF 10K 4 AGND R545 P501 1 2 4 CR503 DNI 1 T503 3P3V_ANALOG R544 0.1UF R548 DNI 3P3V_ANALOG A SEC AGND C535 200 1UH L502 0 AGND 6 3.3V_REF R523 R538 0 0 R532 R531 DNI DNI 49.9 AGND PRI 0.1UF R530 2 3 4 5 Y1 10UF C526 DNI C523 1 DNI 1 A1 10UF C525 DNI J506 1 5 AGND STATUS0/SP0 STATUS1/SP1 1.8V_OUT_0-5 OUT2 OUT2_N 3.3V_OUT_2-5 OUT3 OUT3_N EEPROM_SEL PDB RESETB CR501 R513 VCC 1 36 STATUS_0_I2C_SP0 35 STATUS_1_I2C_SP1 34 VDD_1_8_OUT_2_3 33 OUT2 32 OUT2_N 31 VDD3_OUT_2_3 30 OUT3 29 OUT3_N 28 EEPROM_SEL 27 PD_N 26 RESET_N 25 U300 5 C524 4 0.1UF 1 0.1UF TP502 0 0 2 AGND AGND 3.3V_OUT_0-1 R539 24.9 C528 C529 AGND C519 1UH L501 R542 DNI R537 49.9 DNI R529 AGND AGND 0.1UF DNI T502 ADT1-1WT+ 3 6 AGND DNI 3.3V_REF CLK+ 0 0.1UF 2 3 4 5 C532 R522 DNI B CLK_OUT+ 0 R533 DNI CLK_IN- C522 CLK_OUT- 0.1UF REF_TEST AGND PASSIVE CLOCK J505 1 AD9524_PRELIM 0 R508 0 CLK U501 100NH 1 2 3 C REFA REFA_N REFB REFB_N LF1_EXT_CAP OSC_CTRL OSC_IN OSC_IN_N LF2_EXT_CAP LDO_PLL2 VDD3_VCO LDO_VCO 5 4 3 2 10K 49.9 C507 0.1UF LAYOUT: SMA'S SHOULD BE 575 MILS CENTER TO CENTER LAYOUT: SHARE PADS WITH ACTIVE CLOCK PATH R'S PAD VDD3_CP LDO_PLL1 PLL1_OUT REF_SEL ZD_IN_N ZD_IN VDD_1_8_OUT_0_1 1 2 3 C508 4 5 0.33UF 6 7 8 9 C511 0.47UF 10 3.3V_PLL2 11 C512 12 0.1UF L507 0.1UF C521 OUT2_N R521 200 3.3V_OUT_0-1 DNI OUT2 J503 1 10K R516 3 49.9 0.1UF SYNC_N VDD3_REF CS_N_SDA SCLK_SCL SDIO SDO OUT5_N OUT5 VDD3_OUT_4_5 OUT4_N OUT4 VDD_1_8_OUT_4_5 0.1UF R505 R519 SYNCB 10K 3.3V_REF 60-800MHZ C506 4 5 OUT4_N R509 0.1UF 49.9 VC OUT+ OUTGND Y501 R503 VCC AGND C504 R604 C505 0.1UF AGND 1 C518 O4N CLK_OUT+ C520 DNI R515 C513 0.47UF D AGND OUT0 OUT0_N VDD3_OUT_0_1 OUT1 OUT1_N R502 1K VCXO_CTRL 5 4 3 2 AGND 10K 0.1UF DNI DNI PAD 48 3.3V_PLL1 47 46 45 44 43 42 1.8V_OUT_0-5 41 OUT0 40 OUT0_N 39 38 37 3.3V_REF 0.33UF C503 3.3V_PLL1 6 C514 0.1UF R501 C502 CLK_IN- SI04 1 0.1UF C515 TP501 49.9 D 0.1UF R520 200 J502 1 O4 OUT4 100 C501 CLK_IN+ APPROVED C537 PECL/CML/LVDS CLK CIRCUITRY C517 OUT0 100 R510 DATE DNI R512 ACTIVE CLOCK PATH DESCRIPTION 5 4 3 - 2 SCALE NONE SHEET 5 1 OF 6 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED 3P3V_DIGITAL DGND R626 1.1K 5 DGND Y1 3 A2 Y2 4 1 D DNI TP604 FPGA_SDIO DNI ADG734BRUZ 1 6 1 A1 DUT_SDIO 10 SA SB 9 7 D 8 3P3V_DIGITAL IN CYP_SDO U603 R606 GND 100K R602 10K R601 CYP_SDI R605 1.1K U601 NC7WZ07P6X VCC 3 DU603 R603 1.1K C601 0.1UF IN DRVDD 2 SA 4 SB DNI D R629 3P3V_DIGITAL 10K DRVDD ADG734BRUZ DNI FAST_SPI_EN 2 DNI 0 TP601 DGND 0 DNI C602 0.1UF LAYOUT: PLACE C602 NEAR DUT R607 CYP_SDIO 3P3V_DIGITAL DNI DNI DNI 1 DGND KP_VDDIO R608 0 C603 0.1UF CYP_CSB 3 A2 Y2 4 R612 GND NC7WZ16P6X 2 DGND DGND 15 NC15 6 GND 5 VSS R613 R616 0 0 DNI DNI R614 R617 0 0 DGND ADG734BRUZ DGND DNI TP603 1 DUT_SCLK SPI & FPGA CONN. FPGA_SCLK 100K 6 10K Y1 R610 1 A1 13 D U603 DUT_CSB VCC CYP_SCLK 11 DGND 1 DNI IN DNI TP602 NOTE: THIS SYMBOL IS DRAWN GIVEN INPUT 1 LOGIC 12 SA 14 SB 18 D U603 DNI ADG734BRUZ IN 20 ADG734BRUZ DNI FPGA_CSB 19 SA 17 SB 100K U602 5 C R611 10K R609 DGND R615 10K DNI C604 0.1UF DGND VDD FAST_SPI_EN DRVDD U603 16 DGND C LAYOUT: ROUTE ALL TRACES TO THE TYCO CONN ON TOP OF BOARD SYNC_A+ SYNC_B- B R618 0 R619 0 1 TP608 1 TP609 DNI 1 FAST_SPI_EN CYP_SDO CYP_SDI CYP_SCLK R620 DNI 0 R621 SYNC_ASYNC_B+ 0 DATA_B+ R622 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 0 DATA_B- R623 0 LAYOUT: PLACE THESE R'S NEAR DUT A DATA_A+ P601 DGND 6469169-1 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DNI DNI P602 P602 DGND TP611 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 1 DNI TP612 1 FPGA_SCLK FPGA_CSB FPGA_SDIO B DGND PLUG HEADER REFCLK2X- BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 BG10 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DNI 1 P602 DGND P601 PLUG HEADER REFCLK2X+ P601 PLUG HEADER REFCLK1- C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 PLUG HEADER REFCLK1+ PLUG HEADER P601 DNI P602 P602 BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 BG10 TP610 DNI PLUG HEADER 0 1 TP607 DNI PLUG HEADER CYP_CSB2 CYP_CSB2 CYP_CSB TP606 DNI D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 DNI P602 PLUG HEADER 1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 DNI PLUG HEADER R628 TP605 PLUG HEADER DNI A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 PLUG HEADER 10K R627 DNI USB_CSB2 DNI P601 P601 PLUG HEADER 3P3V_DIGITAL B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 REFCLK2- REFCLK2+ A LAYOUT: TYCO SPACING IS THE WIDER SPACING PER THE ALTERRA BD R624 0 AN A LOG DEV CES R625 DATA_A- 0 THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> AD9644 CUSTOMER BOARD DESIGN VIEW REV DRAWING NO. <DESIGN_VIEW> A 9644CE01 OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 - 2 SCALE NONE SHEET 6 1 OF 6