AD9642/AD9634/AD6672 Evaluation Board Schematic PDF

8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
AD9642/AD9634 ENG (SOCKET)
D
D
DUT
THE FOOTPRINT FOR THIS SOCKED NEEDS TO BE CHECKED AGAINST THE DRAWING
C
VCM
AVDD
AVDD
C
TP_KPIBIAS
1
VCM
C105
0.1UF
AGND
AGND
PAD
32
31
30 VIN+
29 VIN28
27
26
25
KP_VDDIO
LAYOUT: DECOUPLING QUANTITY MAY VARY LAYOUT DEPENDING
U1010
TP105
CLK+
CLKAVDD
D0/D1D0/D1+
D2/D3D2/D3+
DRVDD
B
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DUT_CSB
DUT_SCLK
DUT_SDIO
DCO+
DCOD12/D13+
D12/D13DRVDD
1
C107
1UF
TP101
TP102
1
1
AGND
1
AGND
C101
0.1UF
C103
0.1UF
C121
1UF
B
TP103
TP104
AGND
AGND
1
AVDD
SG-MLF32A-7004
D4/D5D4/D5+
D6/D7D6/D7+
D8/D9D8/D9+
D10/D11D10/D11+
9
10
11
12
13
14
15
16
DRVDD
C109
0.1UF
C110
0.1UF
ADD 1UF AT DUT PIN #3
C111
0.1UF
C112
0.1UF
C113
0.1UF
C122
1UF
C117
1UF
C118
1UF
AGND
A
A
AN A LOG
DEV CES
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
9642 & 9634 ENGINEERING EVAL. PCB
AD9642
Engineering Board
DESIGN VIEW
<DESIGN_VIEW>
DRAWING NO.
REV
9642EE01
B
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
<PTD_ENGINEER>
2
D
SCALE
NONE SHEET 1
1
OF 6
8
6
7
2
3
4
5
1
F201
1
2
1.1A
1
2
3
4
6
5
CR202 VIN
A
C
SK33A-TP
AGND
PGND
261
R201
CR201
A
C
N
PJ-202A
10UF
C201
P
1
2
3
FL201
BNX016-01
CR203
P201
LNJ314G8TRA (GREEN)
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
POWER
D
AGND
D
E212
1
2
3P3V_DIGITAL
10UF
N
C231
100MHZ
0.1UF
C232
P
VIN
P202
P
N
10UF
0.1UF
C234
AGND
E214
1
2
P
N
10UF
C236
0.1UF
C235
100MHZ
P110
100MHZ
GND
4
2
1
2
C
E217
1
2
4.7UF
EN
NC
AGND
C243
0.01UF
DNI
100MHZ
4.7UF
C242
3P3V_DIGITAL
C241
2
U207
ADP150AUJZ-1.8-R7
1
VIN
5
VOUT
3
1
2
4.7UF
E204
1
2
C209
0.01UF
DNI
4.7UF
C208
C207
4
GND
DNI
P105
U203
ADP150AUJZ-3.3-R7
1
VIN
5
VOUT
3
EN
NC
AGND
100MHZ
AGND
C
AGND
3P3V_ANALOG
E203
1
2
2
100MHZ
AVDD
4.7UF
4
GND
DRVDD
Z5.531.3625.0
E202
1
2
C206
EN
NC
0.01UF
C204
4.7UF
C205
DNI
S2A-TP
1
2
U202
ADP150AUJZ-3.3-R7
1
VIN
5
VOUT
3
E213
1
2
C233
P104
CR204
A
C
AGND
1
2
3
4
5
6
1P8V_CLOCK
100MHZ
P106
AGND
Z5.531.3425.0
P203
1
2
3
4
E216
1
2
P
3P3V_ANALOG
N
10UF
100MHZ
100MHZ
0.1UF
C240
E208
1
2
C239
1
2
AGND
U204
ADP1706ARDZ-1.8-R7
EN2
VOUTB
0.01UF
C218
AGND
R214
10.5K
C214
100PF
R216
0
DNI
AGND
PGOOD1
COMP1
SW1
SW2
L201
2.2UH
PGOOD2
COMP2
SW3
SW4
R213
13K
R215
TBD0603
C215
DNI
E210
1
2
1
2
DNI
100MHZ
100MHZ
C220
22UF
DNI
AGND
AGND
R218
0
DNI
L202
TO EVALUATE SHARING OF AVDD AND DVDD
P108
1
2
EN
SENSE
IN
OUT
IN2
OUT2
SS
GND1 PAD
2 PAD
E207
1
2
5
6
DRVDD
100MHZ
P109
AGND
E209
1
2
AGND
100PF
1
7
3
4
8
C221
22UF
C219
TBD0603
B
100MHZ
E206
1
2
4.7UF
C227
0.01UF
4.7UF
C226
R217
0
DNI
1500PF
C216
PAD
ADP2114_PRELIM
JP203
1
2
0
VOUTA
2200PF
AGND
VOUTB
E211
1
2
100MHZ
R219
0
A
AGND
R221
EN2
2.2UH
0
R220
TBD0603
1.00K
DNI
R222
VIN
2 PAD
AVDD
1
2
SCFG
FREQ
SYNC_CLKOUT
OPCFG
EN1
V1SET
FB1
SS1
EN2
V2SET
FB2
SS2
GND
PGND1
PGND2
PGND3
PGND4
C217
0.01UF
VOUTA
A
E205
1
2
5
6
4.7UF
EN1
R212
15K
EN
SENSE
IN
OUT
IN2
OUT2
SS
GND1 PAD
U205
ADP1706ARDZ-1.8-R7
C213
C228
SW_FREQ
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
AGND
R210
4.64K
AGND
C230
1.00K
R205
VDD
AGND
R208
100K
AGND
U206
R211
15K
C225
10
R207
100K
0
R209
27K
1
7
3
4
8
0.01UF
EN1
DNI
S2A-TP
4.7UF
C229
R204
S2A-TP
JP201
1
2
0
OPTIONAL
SWITCHING
SUPPLY
1UF
VIN
CR206
A
C
AGND
AGND
C212
B
C211
22UF
R206
C210
22UF
CR205
A
C
AGND
P107
DNI
100MHZ
C223
22UF
C224
22UF
AN A LOG
DEV CES
DNI
C222
TBD0603
AGND
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
AGND
DNI
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
AGND
SCHEMATIC
9642 & 9634 ENGINEERING EVAL. PCB
AD9642
Engineering Board
DESIGN VIEW
<DESIGN_VIEW>
OF ANALOG DEVICES.
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
7
6
REV
9642EE01
B
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
8
DRAWING NO.
5
4
3
<PTD_ENGINEER>
2
D
SCALE
NONE SHEET 2
1
OF 6
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
ANALOG INPUT
D
DNI
4
3
PRI
SEC
T303
T301
R306
MABA-007159-000000
0.1UF
SHARE PADS
R320
VIN-
0
33
R312
0
R318
49.9
C304
DNI
AGND
0
R304
49.9
R310
2 3 4 5
DNI
0
DNI
0
C306
T302
AGND
AGND
8.2PF
R305
0.1UF
R314 AGND
36
R316
AGND
0
1
DNI
R307
DNI
DNI
1
3
5
AGND
SEC
6
1
0.1UF
J302
C303
VCM
2
3
0
VIN+
8.2PF
C314
AGND
33
R313
36
C301
C302
AGND
4
R319
82NH
1
0.1UF
ADT1-1WT+
R315
L301
DNI
C305
R317
49.9
DNI
R301
49.9
MABA-007159-000000
4
0
PRI
0
DNI
AGND
C
R311
0
SHARE PADS
5
R303
0
2 3 4 5
R302
DNI
AIN
AGND
DNI
R308
J301
1
PASSIVE PATH
AMP_OUT+
0
DNI
C
R309
AMP_IN+
8.2PF
D
AMP_OUT-
AMP_IN-
AGND
B
B
LAYOUT: SMA'S SHOULD BE PLACED 540 MILS CENTER TO CENTER
A
A
AN A LOG
DEV CES
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
9642 & 9634 ENGINEERING EVAL. PCB
AD9642
Engineering Board
DESIGN VIEW
<DESIGN_VIEW>
DRAWING NO.
REV
9642EE01
B
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
<PTD_ENGINEER>
2
D
SCALE
NONE SHEET 3
1
OF 6
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
ACTIVE PATH
D
D
3P3V_ANALOG
P
C404
0.1UF
C
N
AGND
T401
AMP_IN+
AMP_IN-
THESE RLCS ARE PLACE HOLDERS... PLACE CORRECT VALUES & COMPONENTS...
0.1UF
C406
DNI
PRI
SEC
4
3
R401
40.2
0
1
VIP2
2
VIP1
3
VIN1
4
R404
R405
AGND
C402
MABA-007159-000000
0.1UF
R408
VOP
VON
PD_N_A
0
DNI
R406
12
11
10
ENBL
GND
ADL5562_PRELIM
R402
40.2
VCOM
9
PAD
DNI
JP401
1
2
JPR0402
DNI
C407
C403
0.1UF
0.1UF
L405
82NH
C408
0.1UF
DNI
DNI
AGND
R412
DNI
C410
5PF
C409
5PF
0 DNI
R411
1.00K
DNI
DNI
R410
1.00K
DNI
VCM
120NH
120NH
0.1UF
0 DNI
R409
AGND
3P3V_ANALOG
L403
AMP_OUT+
VCC
VIN2
0
L401
U401
5
6
7
8
1
13
14
15
16
PAD
5
0
C
AGND
R403
C401
C405
10UF
VCM
0
L406
DNI
DNI
82NH
DNI
L402
L404
120NH
120NH
DNI
DNI
DNI
AMP_OUT-
DNI
AGND
AGND
R407
1.1K
P401
PD_N_A
1
2
AGND
B
B
A
A
AN A LOG
DEV CES
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
9642 & 9634 ENGINEERING EVAL. PCB
AD9642
Engineering Board
DESIGN VIEW
<DESIGN_VIEW>
DRAWING NO.
REV
9642EE01
B
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
<PTD_ENGINEER>
2
D
SCALE
NONE SHEET 4
1
OF 6
8
6
7
2
3
4
5
1
REVISIONS
REV
ACTIVE CLOCK PATH
R510
L507
0.1UF
100
R512
OUT2
DNI
3.9NH
C521
OUT2_N
CLK_OUT-
0.1UF
EEPROM_SEL
3.3V_OUT_4-13
0.1UF
C516
C515
0.1UF
3.3V_REF
STATUS0_SP0
STATUS1_SP1
0.1UF
0.1UF
C548
C547
0.1UF
0.1UF
C539
0.1UF
C538
0.1UF
C537
E502
1
2
1UH
L505
3.3V_OUT_0-3
3.3V_OUT_4-13
AGND
CLK-
R542
390PF
AGND
A
AGND
AGND
AN A LOG
DEV CES
SCHEMATIC
9642 & 9634 ENGINEERING EVAL. PCB
AD9642
Engineering Board
CLK_IN+
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
DESIGN VIEW
<DESIGN_VIEW>
DRAWING NO.
REV
9642EE01
B
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
6
5
10UF
5 4 3 2
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
7
10UF
C530
10UF
C527
C534
10UF
1UH
J502
1
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
8
0.1UF
0.1UF
C546
0.1UF
C545
0.1UF
C544
0.1UF
C543
0.1UF
C536
C535
3.3V_PLL1
AGND
C533
DNI
0
R534
0
AGND
L504
DNI
CLK_OUTAGND
3.3V_PLL2
C524
J503
1
2 3 4 5
0
DNI
T501
3.3V_REF
3
AGND
R523
R538
DNI
49.9
R530
AGND
R543
100
2
R540
33
390PF
1UH
L503
E501
1
2
B
1.8V_OUT_0-13
1UH
3P3V_DIGITAL
49.9
AGND
C523
2 3 4 5
0
3 MABA-007159-000000
DNI
J506
1
0 DNI
0
1
49.9
DNI R521
CLK
1
CR503
R528
DNI
DNI R520
4
4 0.1UF
DNI
0 DNI
0
R537
49.9
DNI R529
SEC
3P3V_ANALOG
C517
0.1UF
1
PRI
DNI
1UH
L502
5
2
1UH
L501
45OHMS
SEC
C529
AGND
AGND
1
L506
MABA-007159-000000
390PF
R539
33
T503
5
CLK+
3
AGND
T502
ADT1-1WT+
3
6
AGND
AD9523
45OHMS
PRI
0
390PF
2 3 4 5
C518
0.1UF
C532
R522
100
4
C522
J505
1
CLK_OUT+
R541
DNI
C
AGND
AGND
1P8V_CLOCK
R511
CLK_IN-
R533 DNI
DNI
A
USB_CSB2
CYP_SCLK
CYP_SDI
CYP_SDO
PASSIVE CLOCK
LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER
LAYOUT: SHARE PADS WITH ACTIVE CLOCK PATH R'S
OUT9
OUT9_N
54
1.8V_OUT_0-13
R546
53
52
100
51 3.3V_OUT_4-13
R526
50
49
100
48
3.3V_OUT_4-13
R527
47
46
100
45
R531
44
43
100
42
R532
41
40
100
39
1.8V_OUT_0-13
R535
38
37
100
RESETB
10K
B
AGND
TP503
C526
1
LNJ314G8TRA (GREEN)
10UF
R515
CR502
200
GND
NC7WZ16P6X
2
10UF
C525
3.3V_OUT_4-13
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
TP505
R514
0.1UF
C542
RESET_N
CS_N
SCLK_SCL
3.3V_REF
4
C540
3.3V_OUT_4-13
VDD_1_8_OUT4_5
1.8V_OUT_0-13
AGND
1
SYNCB
10K
Y2
LNJ314G8TRA (GREEN)
100
3.3V_REF
3 A2
200
3.3V_OUT_0-3
OUT8
OUT8_N
VDD3_OUT8_9
10K
0.47UF
0
PDB
R519
DNI
TP504
R509
10K
0
R508
3.3V_PLL2
0.47UF
R516
0.001UF
C510
0.001UF
C509
R506
C512
6
AGND
OUT7
OUT7_N
VDD_1_8_OUT8_9
R536
C511
TBD0402
100
R507
Y1
CR501
R513
VCC
1 A1
1
DNI
U300
5
U501
OUT6
OUT6_N
VDD3_OUT6_7
R544
AGND
100
0.33UF
STATUS0/SP0
STATUS1/SP1
OUT5
OUT5_N
VDD_1_8_OUT6_7
R545
C508
0.1UF
1
OUT4
OUT4_N
VDD3_OUT4_5
OUT13
3.3V_OUT_4-13
0.1UF
C
LDO_PLL1
VDD3_PLL1
REFA
REFA_N
REFB
REFB_N
LF1_EXT_CAP
OSC_CTRL
OSC_IN
OSC_IN_N
LF2_EXT_CAP
LDO_PLL2
VDD3_PLL2
LDO_VCO
PD_N
REF_SEL
SYNC_N
VDD3_REF
OUT13_N
3.3V_PLL1
C507
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SDIO_SDA
0.1UF
0.47UF
AGND
49.9
10K
3.3V_OUT_0-3
TP502
SDO
REF_TEST
OUT13_N
OUT13
VDD3_OUT12_13
OUT12_N
OUT12
VDD_1_8_OUT12_13
OUT11_N
OUT11
VDD3_OUT10_11
OUT10_N
OUT10
VDD_1_8_OUT10_11
C513
R505
C506
3
PAD
PLL1_OUT
49.9
DNI
ZD_IN_N
ZD_IN
VDD_1_8_OUT0_1
OUT0
OUT0_N
VDD3_OUT0_1
OUT1
OUT1_N
VDD_1_8_OUT2_3
OUT2
OUT2_N
VDD3_OUT2_3
OUT3
OUT3_N
EEPROM_SEL
60-800MHZ
4
5
0.1UF
49.9
VC
OUT+
OUTGND
R604
VCC
R503
Y501
1
C514
PAD
0.1UF
72
71
70
69 1.8V_OUT_0-13
68 OUT0
67 OUT0_N
66
65 R524
64
100
63
62
61
60
59 R525
58
100
57
56
55
R502
1K
0.33UF
C503
6
AGND
C504
10K
D
3.3V_OUT_0-3
VCXO_CTRL
AGND
C505
0.1UF
1
SI04
0.1UF
R518
AGND
C519
AGND
TP501
R517
0.1UF
C541
49.9
R501
C502
CLK_IN-
3.3V_PLL1
C531
12PF
C501
0.1UF
APPROVED
CLK_OUT+
100
CLK_IN+
DATE
C520
PECL/CML/LVDS CLK CIRCUITRY
D
DESCRIPTION
4
3
<PTD_ENGINEER>
2
D
SCALE
NONE SHEET 5
1
OF 6
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
APPROVED
DATE
FAST_SPI_EN
1
DRVDD
3P3V_DIGITAL
DNI
AGND
10K
R629
DRVDD
R626
1.1K
5
IN
TP_DUT_SDIO
Y1
3 A2
Y2 4
DUT_SDIO
10
SA
SB
9
7
D
8
3P3V_DIGITAL
IN
CYP_SDO
R606
GND
2
DNI
C602
0.1UF
DNI
C603
0.1UF
DNI
1
AGND
3P3V_DIGITAL
0
LAYOUT: PLACE C602 NEAR DUT
AGND
KP_VDDIO
R608
DNI
0
TP_CYP_SDIO
AGND
D
U603
ADG734BRUZ
1
FPGA_SDIO
6
1 A1
100K
R602
10K
R601
U601
NC7WZ07P6X
VCC
CYP_SDI
R605
1.1K
DNI
3 D
R603
1.1K
C601
0.1UF
D
U603
2 SA ADG734BRUZ
4 SB
DRVDD
16
CYP_SDIO
VDD
15 NC15
6 GND
5 VSS
AGND
DNI
AGND
CYP_CSB
3 A2
Y2
4
R612
GND
NC7WZ16P6X 2
AGND
AGND
13 D
DUT_CSB
R616
0
0
DUT_SCLK
SPI & FPGA CONN.
DNI
1
DCO+
D2/D3+
D6/D7+
D10/D11+
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
PLUG HEADER
1
DNI
DNI
TP612
1
TP611
DNI
TP610
TP609
DNI
DNI
TP608
1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
DCOD2/D3D6/D7D10/D11-
R643
D2/D3+
100 DNI
R635
D4/D5+
100 DNI
R644
100
D6/D7+
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D0/D1+
D4/D5+
D8/D9+
D12/D13+
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
AGND
PLUG HEADER
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
PLUG HEADER
PLUG HEADER
PLUG HEADER
D4/D5-
B
DNI
D6/D7-
R636
100
D2/D3-
DNI
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D8/D9+
D0/D1D4/D5D8/D9D12/D13-
R645
D8/D9-
100 DNI
D10/D11+
R637
100
D12/D13+
D10/D11DNI
D12/D13-
R646
DNI
P602 P602
6469169-1
AGND
D0/D1-
P602 P602
P601 P601
A
DNI
D0/D1+
100
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
DCO-
R633
100
P602
PLUG HEADER
PLUG HEADER
PLUG HEADER
1
P602
P601
P601
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
1
DCO+
PLUG HEADER
0
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
A
SCHEMATIC
AGND
AN A LOG
DEV CES
AGND
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
9642 & 9634 ENGINEERING EVAL. PCB
AD9642
Engineering Board
DESIGN VIEW
<DESIGN_VIEW>
DRAWING NO.
REV
9642EE01
B
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
C
USING FIFO5(UNUSED PINS REMOVED
PLUG HEADER
CYP_CSB2
TP607
TP606
DNI
R628
CYP_CSB2
CYP_CSB
1
B1
B2
B3 FAST_SPI_EN
B4
CYP_SDO
B5
CYP_SDI
B6
CYP_SCLK
B7
FPGA_SCLK
FPGA_CSB
B8
B9
FPGA_SDIO
B10
PLUG HEADER
10K
R627
B
TP605
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
PLUG HEADER
P601 P601
DNI
USB_CSB2
AGND
AGND
3P3V_DIGITAL
1
ADG734BRUZ
1
LAYOUT: ROUTE ALL TRACES TO THE TYCO CONN ON TOP OF BOARD
DNI
AGND
TP_DUT_SCLK
FPGA_SCLK
R613
DNI
DNI
DNI
12 SA
14 SB
18 D
19 SA
17 SB
100K
R611
FPGA_CSB
NOTE: THIS SYMBOL IS DRAWN GIVEN INPUT 1 LOGIC
TP_DUT_CSB
100K
6
10K
Y1
R610
1 A1
U603
ADG734BRUZ
11
DNI
VCC
CYP_SCLK
IN
IN
R615
10K
1
AGND
U602
5
C
ADG734BRUZ
U603
C604
0.1UF
10K
R609
DRVDD
20
FAST_SPI_EN
DNI
U603
6
5
4
3
<PTD_ENGINEER>
2
D
SCALE
NONE SHEET 6
1
OF 6