DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator Features General Description The DSC557-03 is a crystal-less, two output PCI express clock generator meeting Gen1, Gen2, and Gen3 specifications. The clock generator uses proven silicon MEMS technology to provide 100MHz* differential output clocks with excellent jitter and stability over a wide range of supply voltages and temperatures. By eliminating the external quartz crystal, the DSSC557-03 significantly enhances reliability and accelerates product development, while meeting stringent clock performance criteria for a variety of communications, storage, and networking applications. DSC557-03 has an Output Enable / Disable feature allowing it to disable the outputs when OE is low. The device is available in two different packages; a “drop-in” replacement 16 pin TSSOP or a space saving 14 pin QFN (77% less board space). Additional output formats are also available in any combination of LVPECL, LVDS, and HCSL. Block Diagram OE * PLL Available Output Formats: o o HCSL, LVPECL, or LVDS HCSL/LVPECL, HCSL/LVDS, LVPECL/LVDS Wide Temperature Range o Ext. Industrial: -40° to 105° C o Industrial: -40° to 85° C o Ext. commercial: -20° to 70° C Supply Range of 2.25 to 3.6 V Low Power Consumption o 30% lower than competing devices Excellent Shock & Vibration Immunity o Qualified to MIL-STD-883 Available Footprints: o o 16 TSSOP 14 QFN Lead Free & RoHS Compliant Short Lead Time: 2 Weeks Applications Communications/Networking Control Circuitry MEMS Meets PCIe Gen1, Gen2 & Gen3 specs. Output Control and Divider CLK0+ CLK0- CLK1CLK1+ Clk0+/- and Clk1+/- are 100 MHz as per PCIe standards. For other frequencies, please contact the factory. o o o o o Ethernet 1G, 10GBASE-T/KR/LR/SR, and FcoE Routers and Switches Gateways, VoIP, Wireless AP’s Passive Optical Networks Storage o SAN, NAS, SSD, JBOD Embedded Applications o Industrial, Medical, and Avionics o Security Systems and Office Automation o Digital Sinage, POS and others Consumer Electronics o Smart TV, Bluray, STB _____________________________________________________________________________________________________________________________ _________________ DSC557-03 Page 1 MK-QB-P-D-120917-01-2 DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator Specifications (Unless specified otherwise: T=25° C, VDD =3.3V) Parameter Supply Voltage Condition 1 VDD Supply Current IDD Supply Current2 (Two HCSL Outputs) IDD Frequency Stability Δf Startup Time3 Input Logic Levels Input logic high Input logic low tSU VIH VIL Output Disable Time4 Output Enable Time Min. Typ. 2.25 EN pin low – outputs are disabled EN pin high – outputs are enabled RL=50 Ω, FO1=FO2=100 MHz Includes frequency variations due to initial tolerance, temp. and power supply voltage 21 Max. Unit 3.6 V 23 mA 60 mA ±100 ±50 ppm 5 ms 0.25xVDD V tDA 5 ns tEN 20 ns 2 Pull-Up Resistor 0.75xVDD - Pull-up on OE pin 40 kΩ HCSL Outputs6 Parameter Output Logic Levels Output logic high Output logic low VOH VOL Pk to Pk Output Swing Output Transition time Rise Time Fall Time Condition Min. RL=50Ω 0.725 - Single-Ended 4 Frequency Output Duty Cycle 5 Period Jitter Jitter, Phase (Common Clock Architecture) Max. Unit 0.1 V 750 mV 20% to 80% RL=50Ω, CL= 2pF 200 f0 Single Frequency 2.3 SYM Differential 48 JPER FO1=FO2=100 MHz 2.5 psRMS RJ PCIe Gen 1.1 TJ=DJ + 14.069 x RJ (BER 10-12) 0.540 PsRMS DJ TJ PCIe Gen 1.1 TJ=DJ + 14.069 x RJ (BER 10-12) 0.832 8.536 41.98 86.08 psp-p JRMS-CCHF PCIe Gen 2.1, 1.5 MHz to Nyquist 0.458 3.18 psRMS JRMS-CCLF PCIe Gen 2.1, 10 kHz to 1.5 MHz 0.030 3.08 psRMS 0.165 1.0 8 psRMS 0.561 4.08 psRMS 1.778 0.147 7.58 1.08 psRMS psRMS tR tF JRMS-CC Integrated Phase Noise (Data Clock Architecture) Typ. JRMS-DCHF JRMS-DCLF JRMS-DC PCIe Gen 3.0 PCIe Gen 2.1, 1.5 MHz to Nyquist PCIe Gen 2.1, 10 kHz to 1.5 MHz PCIe Gen 3.0 1007 400 ps 460 MHz 52 % Notes: 1. VDD should be filtered with 0.01uf capacitor. 2. Output is enabled if OE pin is floated or not connected. 3. tsu is time to 100PPM stable output frequency after VDD is applied and outputs are enabled. 4. Output Waveform and Connection Diagram define the parameters. 5. Period Jitter includes crosstalk from adjacent output. 6. Contact [email protected] for alternate output options (LVPECL, LVDS, LVCMOS). 7. Contact [email protected] for alternative frequency options 8. Jitter limits established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards. _____________________________________________________________________________________________________________________________ _________________ DSC557-03 Page 2 MK-QB-P-D-120917-01-2 DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator Absolute Maximum Ratings Item Min Max Unit Supply Voltage -0.3 +4.0 V Input Voltage -0.3 VDD+0.3 V Junction Temp - +150 °C Storage Temp -55 +150 °C Soldering Temp - +260 °C ESD HBM MM CDM - Condition 40sec max. V 4000 400 1500 Solder Reflow Profile Se 3C / 217°C 200°C 60-150 Sec S 6C/ ax cM 3C /S e 25°C 60-180 Sec Pre heat 8 min max Reflow x. 150°C Ma . ec Temperature (°C) cM ax . 260°C 20-40 Sec Cool Time 14 QFN MSL 1 @ 260°C refer to JSTD-020C 16 TSSOP MSL 3 @ 260°C refer to JSTD-020C Ramp-Up Rate (200°C to Peak Temp) 3°C/Sec Max. Preheat Time 150°C to 200°C 60-180 Sec Time maintained above 217°C 60-150 Sec Peak Temperature 255-260°C Time within 5°C of actual Peak 20-40 Sec Ramp-Down Rate 6°C/Sec Max. Time 25°C to Peak Temperature 8 min Max. _____________________________________________________________________________________________________________________________ _________________ DSC557-03 Page 3 MK-QB-P-D-120917-01-2 DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator Pin Diagram (16 TSSOP) Connection Diagram (16 TSSOP Two HCSL Outputs) NC 1 16 VDD NC 2 15 CLK0+ 1 16 NC 3 14 CLK0- 2 15 NC 4 13 NC 3 14 NC 5 12 NC 4 13 OE 6 11 CLK1- VSS 7 10 CLK1+ NC 8 9 NC + VDD - 0.01 uF + Enable - CLK0+ CLK050 W 50 W Ropt 5 12 6 11 CLK1- 7 10 CLK1+ 8 9 50 W 50 W Ropt 22W - 33 W optional 16-TSSOP (173 mil) (5.1 x 6.8 mm) Pin Description (16 TSSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name9 NC NC NC NC NC OE VSS NC NC CLK1+ CLK1NC NC CLK0CLK0+ VDD Pin Type NA NA NA NA NA I Power NA NA O O NA NA O O Power Description No connect No connect No connect No connect No connect Output Enable; active high Ground No connect No connect True output of differential pair Complement output of differential pair No connect No connect Complement output of differential pair True output of differential pair Power Supply _____________________________________________________________________________________________________________________________ _________________ DSC557-03 Page 4 MK-QB-P-D-120917-01-2 DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator Pin Diagram (14 QFN) Connection Diagram NC VDD1 VDD0 (14 QFN Two HCSL Outputs) 14 13 12 0.01 uF 14 OE 1 11 CLK0+ NC 2 10 CLK0- NC 3 9 CLK1- 4 8 6 CLK1+ 12 1 11 2 10 3 9 4 CLK0+ CLK050 W 50 W 8 5 6 7 CLK1- Ropt 7 CLK1+ Ropt 22W - 33 W optional NC NC 5 NC VSS + Enable - 13 + VDD - 0.01 uF 50 W 50 W 14 QFN 3.2x2.5mm Pin Description (14 QFN) Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OE NC NC VSS NC NC NC CLK1+ CLK1CLK0CLK0+ VDD1 VDD0 NC Pin Type I NA NA Power NA NA NA O O O O Power Power NA Description Output Enable; active high Ground recommended or leave as a NC Ground recommended or leave as a NC Ground Ground recommended or leave as a NC Ground recommended or leave as a NC Ground recommended or leave as a NC True output of differential pair Complement output of differential pair Complement output of differential pair True output of differential pair Power Supply for Core and Output 1 (CLK0+/-) Power Supply for Output 0 (CLK1+/-) Ground recommended or leave as a NC _____________________________________________________________________________________________________________________________ _________________ DSC557-03 Page 5 MK-QB-P-D-120917-01-2 DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator OE Function and Output Waveform: HCSL tR Output tF 80% 675 mV 830 mv 50% Output 20% tEN 1/f o tDA VIH Enable VIL Ordering Information9 DSC557-03 4 4 F I 0 - T CLK 1 Output Format 1: LVCMOS 2: LVPECL 3: LVDS 4: HCSL CLK 0 Output Format 1: LVCMOS 2: LVPECL 3: LVDS 4: HCSL Packing T: Tape & Reel Stability 0: ±100ppm 1: ±50ppm Temp Range E: -20 to 70 I: -40 to 85 L: -40 to 105 Package F: 14 QFN S: 16 TSSOP Note 9. CLK0 and CLK1 are configured at the factory to 100 MHz. (For other frequencies, contact the factory at [email protected].) _____________________________________________________________________________________________________________________________ _________________ DSC557-03 Page 6 MK-QB-P-D-120917-01-2 DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator Package Dimensions F: 14 QFN, 3.2 x 2.5 mm _____________________________________________________________________________________________________________________________ _________________ DSC557-03 Page 7 MK-QB-P-D-120917-01-2 DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator S: 16 TSSOP (173 mil body width) Recommended Solder Pad Layout Units mm [in] 1.1[0.043] 0.65 [0.256] 6.8[0.268] 4.6 [0.181] 0.3 [0.012] 4.85 [0.191] _____________________________________________________________________________________________________________________________ _________________ DSC557-03 Page 8 MK-QB-P-D-120917-01-2 DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator Disclaimer: Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. MICREL, Inc. Phone: +1 (408) 944-0800 ● ● 2180 Fortune Drive, Fax: +1 (408) 474-1000 San Jose, California 95131 ● Email: [email protected] ● ● USA www.micrel.com _____________________________________________________________________________________________________________________________ _________________ DSC557-03 Page 9 MK-QB-P-D-120917-01-2