CYPRESS SEMICONDUCTOR PSoC Creator 210: Intro to Datapath Components PSoC Creator 210: Intro to Datapath Components Cypress Blogs • Latest posts: www.cypress.com/go/blogs • PSoC Sensei: www.cypress.com/go/psocsensei Online Training • http://www.cypress.com/go/training www.cypress.com/go/psoc3 www.cypress.com/go/psoc5 Chip Documentation • Datasheets and Technical Reference Manuals • Available on the web: Help->Documentation->Component Author Guide Software Documentation • From within PSoC Creator select: Various aspects of component development are documented in the following locations Component Development Documentation 2 PSoC Creator 210: Intro to Datapath Components PSoC Development Kit (CY8CKIT-001) is used for all examples Shown using the PSoC 3 processor module All examples can also use the PSoC 5 processor module Many of the examples could also be run on: • PSoC 3 FirstTouch Starter Kit (CY8CKIT-003) • PSoC 5 FirstTouch Starter Kit (CY8CKIT-014) Development Kit wired as follows: P0_2 – SW1 P0_3 – SW2 P0_4 – LED1 P0_5 – LED2 P0_6 – LED3 P0_7 – LED4 Development Kit Setup for Examples 3 PSoC Creator 210: Intro to Datapath Components Run the tool from the Start Menu Separate tool installed by default with the FCS release of PSoC Creator For PSoC Creator Beta 5 the “Complete” install is required Datapaths must be instantiated into a Verilog based component Datapath Configuration Tool used to configure datapaths Datapath Configuration Tool 4 PSoC Creator 210: Intro to Datapath Components Write the file back Make any further Verilog changes within the PSoC Creator editor Be careful to only edit with one tool at a time Make sure changes are saved before switching between the PSoC Creator Editor and the Datapath Configuration Tool Select the specific instance to be edited Make changes Read in a component Verilog file to modify Add any new instances of datapaths that are needed Make modifications Datapath Configuration Tool Flow 5 • Covered in later training • Defaults are backwards compatible • New silicon features are shown grayed out PSoC 3 ES3 • Datapath initialized with this constant configuration • Single configuration chosen at build time Static • Changes on each clock cycle • 8 Configurations Dynamic PSoC Creator 210: Intro to Datapath Components Static Configuration Dynamic Configuration Dynamic and Static Configuration 6 Special CRC Parallel Input Variable Width FIFO Comparison Arithmetic Shift Datapath PSoC Creator 210: Intro to Datapath Components Datapath Configuration Functions 7 PSoC Creator 210: Intro to Datapath Components Configuration Hardware Implementation Configuration for the datapath is controlled on a cycle by cycle basis 8 Configurations are held in a control store RAM for each datapath 3 Inputs select/address the configuration used for each cycle Table below shows the functions selected by the configuration word Dynamic Datapath Configuration 8 PSoC Creator 210: Intro to Datapath Components 8-bit wide datapath 2 Accumulators (A0, A1) 2 Data registers (D0, D1) 2 4-entry FIFOs (F0, F1) 8 Function ALU 4 Function shift Masking Datapath ALU Architecture 9 F1 F0 D1 D0 A1 A0 D0 ALU A1 A0 F1 F0 D1 D0 A1 A0 SRCB F1 F0 D1 D0 A1 A0 ALU A0 D1 D0 A1 A0 SUB A-B PSoC Creator 210: Intro to Datapath Components F0 F1 F0 D1 D0 A1 A0 A0 WR SRC A1 A0 A1 A0 ADD A+B SWAP NONE >> SR << SL PASS DEC INC PASS A-1 A+1 A F1 F0 D1 D0 A1 A0 SRCA SHIFT FUNC A1 D1 D0 A1 A0 D1 F1 F0 D1 D0 A1 A0 D0 D1 D0 A1 A0 AND A&B F1 F1 F0 D1 D0 A1 A0 A1 WR SRC XOR A^B Core Datapath Configuration F1 F0 D1 D0 A1 A0 NONE D1 D1 D0 A1 A0 OR A|B 10 PSoC Creator 210: Intro to Datapath Components Reset: A0 directly loaded from D0 A1 loaded from the result of the ALU • Simple method to clear a register • ALU = A0 ^ A0 = 0 Shift A0 A0 “PASS”ed through the ALU and shifted right (SR) A0 written with the shifted result from the ALU A1 not updated Increment A1 A1 “INC”remented by the ALU A1 written with the incremented value A0 not updated Core Datapath Examples Increment A1 A+1 D1 D0 A1 A0 Reset A^B D1 D0 A1 A0 Shift A0 A >> D1 D0 A1 A0 11 0 1 sol sol_reg sor_reg routed chained def sol sol_reg 6 7 1 1 . . . Output of Shifter . . . Shift Left Operation . . . Output of Shifter . . . . . . Input from ALU . . . . . . Input from ALU . . . 6 6 PSoC Creator 210: Intro to Datapath Components 6 7 7 7 Shift Right Operation 1 1 0 0 Shift Operation (Right or Left) 0 0 sol_reg routed chained sor sor_reg sor 0 1 sor_reg 12 sol sol_reg sol sol_reg 3 . . Output of Shifter . . . 7 2 2 PSoC Creator 210: Intro to Datapath Components 3 Swap Operation 1 1 1 . . . Output of Shifter . . . . . . Input from ALU . . . 6 7 1 . . . Input from ALU . . . 7 6 7 Pass Operation 0 0 Shift Operation (Pass or Swap) 0 0 sor sor_reg sor sor_reg 13 – Single cycle multi-byte shifts ROUTE: Routed hardware signal CHAIN: Chained from adjacent datapath SL: Shift left (output MSB of input value) SR: Shift right (output LSB of input value) PSoC Creator 210: Intro to Datapath Components Static choice that is independent on the dynamic shift direction Applies even when the dynamic shift operation is PASS or SWAP • • Shift Output Selection (SHIFT SEL) Choice of which bit to route out • • – Multi-byte shifts with a single datapath Shift Input Select (SI SEL) Dynamic choice between two shift input sources • CFGA: Use SI SELA selection • CFGB: Use SI SELB selection Default Shift Input (DEF SI) Value for the default shift input • DEF_0 (0 value) • DEF_1 (1 value) Shift Selection A and B (SI SELA / SELB) Choice of bit value to shift in • DEFSI: Default shift input • REGIS: Registered input (sol_reg / sor_reg) Shift Configuration sor sol so 14 PSoC Creator 210: Intro to Datapath Components Determine static configuration Implement Operations and Assign to Locations 1 to 1 mapping possible with 8 or less states • Some configuration locations may be duplicates 1 Operation to Many States will require decode logic Map States to Datapath Operations 8 dynamic operations available Design State Machine Determine Datapath Operations Required 2 Data Registers 2 Accumulators 2 FIFOs Allocate Registers and FIFOs DP Component Design Process 15 PSoC Creator 210: Intro to Datapath Components Repeatedly output an 8-bit pattern 1 input: clock 1 output: pattern Implement using a single datapath element and Verilog logic Simple 8-bit Pattern Generator Walkthrough Example 16 A >> Shift A|B >> Load State 0 1 Config 0 1 • 1:1 Mapping • Registers initialize to 0, so State 0 is the starting state Name Load Shift PSoC Creator 210: Intro to Datapath Components • D0 is not a choice for Source A, so it can’t be passed through the ALU • A0 is 0 at initialization and after shifting all 8-bits, so A0 OR D0 = D0 D1 D0 A1 A0 Usage Pattern Shift Register D1 D0 A1 A0 Register D0 A0 Pattern Generator Design 17