PSoC Creator 211: Datapath Computation CYPRESS SEMICONDUCTOR Component Development Documentation Various aspects of component development are documented in the following locations Software Documentation • From within PSoC Creator select: Help->Documentation->Component Author Guide Chip Documentation • Datasheets and Technical Reference Manuals • Available on the web: www.cypress.com/go/psoc3 www.cypress.com/go/psoc5 Cypress Blogs • Latest posts: www.cypress.com/go/blogs • PSoC Sensei: www.cypress.com/go/psocsensei Online Training • http://www.cypress.com/go/training PSoC Creator 211: Datapath Computation 2 Development Kit Setup for Examples PSoC Development Kit (CY8CKIT-001) is used for all examples Shown using the PSoC 3 processor module All examples can also use the PSoC 5 processor module Many of the examples could also be run on: • PSoC 3 FirstTouch Starter Kit (CY8CKIT-003) • PSoC 5 FirstTouch Starter Kit (CY8CKIT-014) Development Kit wired as follows: P0_2 – SW1 P0_3 – SW2 P0_4 – LED1 P0_5 – LED2 P0_6 – LED3 P0_7 – LED4 PSoC Creator 211: Datapath Computation 3 Arithemetic Configuration Carry Input Select (CI SEL) Dynamic choice between two carry input sources • CFGA: Use CI SELA selection • CFGB: Use CI SELB selection Carry Selection A and B (CI SELA / SELB) Choice of bit value to shift in • ARITH: Default carry input based on the arithmetic operation being performed • REGIS: Registered input (co_reg) – Multi-byte arithmetic with a single datapath • ROUTE: Routed hardware signal – Can be used for hardware controlled counting • CHAIN: Chained from adjacent datapath – Single cycle multi-byte arithmetic Carry Chain Operation co_reg co 7 6 . . . Arithmetic ALU . . . (INC, DEC, ADD, SUB) PSoC Creator 211: Datapath Computation 1 0 default co_reg routed chained 4 Datapath Comparison Generation Many conditions are continuously calculated by the datapath Used to drive outputs Used to control a state machine Outputs available from the Verilog Datapath instance All the comparisons are done based on the value of registers (A0, A1, D0, D1) • None of the comparisons are done using the ALU output directly Comparison Datapath Outputs Condition Verilog Description Port Compare Equal Compare Less Than Zero Detect Ones Detect Compare Equal Compare Less Than Zero Detect Ones Detect ce0 cl0 z0 ff0 ce1 cl1 z1 ff1 A0 == D0 A0 < D0 A0 == 0 A0 == 0xFF A1 or A0 == D1 or A0 (dynamic) A1 or A0 < D1 or A0 (dynamic) A1 == 0 A1 == 0xFF PSoC Creator 211: Datapath Computation 5 Datapath Outputs Up to 6 outputs from a datapath can be used Use up to 6 outputs and PSoC Creator will configure the muxes appropriately Both registered and unregistered outputs are available • Either or both can be used – If both are used they each count towards the total of 6 • • • Registering an output delays the value by one clock cycle Unregistered outputs are subject to combinatorial glitches Ports are in the default Verilog instance just for the unregistered versions – Underlying primitive has both registered and unregistered ports – Add an additional port or rename the existing port with “_reg” added to the name for a registered port Remaining Datapath Outputs Condition Overflow Carry Out CRC MSB Shift Out FIFO0 Bus Status FIFO0 Block Status FIFO1 Bus Status FIFO1 Block Status Verilog Port ov_msb co_msb cmsb so f0_bus_stat f0_blk_stat f1_bus_stat f1_blk_stat Description Carry(MSB) ^ Carry(MSB-1) Carry out of MSB defined bit MSB of CRC/PRS function Selected shift output FIFO0 status for use by the CPU FIFO0 status for use by the block (Verilog) FIFO1 status for use by the CPU FIFO1 status for use by the block (Verilog) PSoC Creator 211: Datapath Computation 6 Comparison Configuration Comparison 1 Select (CMP SEL) Dynamic choice between two comparison result sources • CFGA: Use CMP SELA selection • CFGB: Use CMP SELB selection Comparison Selection A and B (CMP SELA / SELB) Choice of A0 or A1 as the first input Choice of A0 or D1 as the second input • A0_D1: A0 < D1, A0 == D1 • A1_D1: A1 < D1, A1 == D1 • A1_A0: A1 < A0, A1 == A0 • A0_A0: Not a useful choice Chain Comparison Selection (CHAIN 0 / CHAIN 1) Separate selection for the 0 comparisons and the 1 comparisons NOCHN: Compare with just this datapath CHNED: Include the chained comparison result from the adjacent less significant datapath PSoC Creator 211: Datapath Computation 7 Controlling a Component Control Registers are available directly as a Verilog instance Accessible for read and write from the CPU / DMA Readable by the hardware Provides an 8-bit value to control hardware cy_psoc3_control #(.cy_force_order(1)) ControlReg ( /* output [07:00] */ .control() ); Always set the cy_force_order parameter to 1 • Value of 0 is reserved for future routing optimizations Accessed from the CPU (using this example instance name of ControlReg) with the address: <InstanceName>_ControlReg__CONTROL_REG PSoC Creator 211: Datapath Computation 8 Walkthrough Example 8-bit One Output PWM 1 input: clock 1 output: pwm (glitch-free) CPU controllable enable Implement using: • Single Datapath • Single Control register • Verilog logic PSoC Creator 211: Datapath Computation 9 PWM Design Register Usage A0 Counter D0 Limit (Low pulse width) D1 Period • “Period” is the upper count of the PWM counter • Counter counts from 0 to Period for a clock period of (D1 + 1) D0 (D1+1) Name Disable Disable Count Reset Config 000 001 010 011 Description Control register disabled Control register disabled Increment counter Clear counter • Config[0] = (A0 == D1) • Config[1] = Ctrl[0] D1 D0 A1 A0 D1 D0 A1 A0 D1 D0 A1 A0 A A+1 A^B A0==D1 cs_addr[0] ce1 cl0_reg DP pwm Disable Count Reset A0<D0 Disable PSoC Creator 211: Datapath Computation 10