4 3 V+ E8 REFADJ 100 C17 100pF 3 GND 2.7V D2 BAT54C 2 1 V- U10 74VHC595MTC 11 C 10 12 PARALLEL INTERFACE 13 R9 P1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 HD2X20-100 G S0 G G G G G G G B D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 G 9 VCC Q'H 7 QH 6 C19 QG 5 0.1uF QF 4 QE 3 8 GND QD 2 QC 1 QB 15 14 SER QA AMP V- D16 D14 D12 D10 D8 D6 D4 D2 D0 RCK 16 C18 10uF,25V 1206 E5 SCLR D17 D15 D13 D11 D9 D7 D5 D3 D1 S2 S1 100 C23 100pF SCK S2 S1 S0 SCLR RCK U11 74VHC595MTC R16 4.99K 9 VCC Q'H 7 QH 6 C25 QG 5 0.1uF QF 4 QE 3 8 GND QD 2 QC 1 QB 15 14 SER QA 11 10 12 13 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IOUT2F IOUT2S GND/IOUT3 13 8 3 A 2 3 4 100 R23 100 R25 10K R28 20K A0 VCC A1 WP A2 SCL VSS SDA 8 7 R29 4.99K R30 4.99K R31 10K 10 12 2 13 SCK SCLR RCK G 2 3 C40 0.1uF 9 7 6 5 4 3 2 1 15 C16 OPT 0603 4 D5 BAT54C 2 + 2 - C6 0.1uF RVOS GND J2 OPT U5 LT1360CS8 6 C12 0.1uF D V- C15 OPT 0603 R5 10 0603 R6 4.02K 0603 R7 1K 0603 4 E9 RVOS 39 JP5 C 3 2 1 EXT GND U15 LT1761ES5-5 2 3 VIN +5V OUT 5 GND SHDN BYP MANUAL SPAN CONTROL C35 C36 0.01uF 10uF,25V 1206 4 SHDN GND VIN VOUT_F GND VOUT_S GND GND U16 LT1964ES5-5 8 1 C37 1uF 25V 0603 7 6 2 3 GND VCC 1 3 NC 2 VIN C30 10uF,25V 3 NC 1206 4 GND NC NC VOUT TRIM C41 10uF,25V 1206 SHDN 3 4 C38 0.01uF E6 8 5V 6 5 EXT JP3 1 3 5 5 1 3 MSPAN 1 0 HD2X3-079 2 REF 4 6 REG HD2X3-079 VREF VCC E7 5V VCC CONTRACT NO. APPROVALS TECHNOLOGY DRAWN: CHECKED: APPROVED: S2 S1 S0 SPAN 0 0 0 0 5 0 0 1 0 10 0 1 0 -5 5 0 1 1 -10 10 1 0 0 -2.5 2.5 1 0 1 -2.5 7.5 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 Fax: (408)434-0507 LTC Confidential-For Customer Use Only TITLE: SCHEMATIC 18-BIT PARALLEL INPUT, CURRENT OUTPUT DAC WITH READBACK ENGINEER: LEO C. DESIGNER: KIM T. SIZE A DATE: 2 B C39 10uF,25V 1206 VREF 7 JP2 6 4 2 S0 -5V IN BYP JP1 1 6 5 4 3 S1 2 1 0 HD2X3-079 V- CUSTOMER NOTICE 5 5 5 LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. 6 S2 OUT U8 LT1236ACS8-5 1 3 -5V 5 U6 LTC6655AHMS8-5 V+ V+ 7 + 0603 R19 4.99K 4 U13 NC7SZ14P5X 4 - 3 C20 100pF 1206 U4 LTC6240CS5 1 C10 0.1uF 6 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. 5 4 1206 C34 1uF 25V 0603 G U12 74VHC595MTC 11 R26 10K VCC C31 0.1uF R27 4.99K U14 24LC025-I /ST 1 R22 R3 1K -5V C14 1uF UPD D_/S WR_ CLR_ MSPAN RCK C29 0.1uF 5 C33 0.1uF 100 + V+ 3 R24 10K R21 - 3 U3 LTC2054CS5 1 C11 0.1uF 1 SCLR VCC Q'H QH QG QF QE 8 GND QD QC QB 14 SER QA CS/ CLK SDI SDO 5V GND GND GND 1 V+ 2 5V 6 CS 4 SCK/SCL 7 MOSI/SDA 5 MISO 10 EEVCC 9 EESDA 11 EESCL 12 EEGND 14 AUX 4 R8 1K 0603 R17 4.99K R18 4.99K SCK 16 40 C4 0.1uF C5 100pF 1206 READ 1 100 C28 100pF 4 IOUT1 R20 J1 HD2X7-079-MOLEX 0603 C9 1uF 0805 C3 0.1uF U1 LTC2757CLX 3 38 S2 37 S1 S0 R11 4.99K G 16 D_/S READ WR_ CLR_ MSPAN UPD 8 9 10 11 12 13 14 15 16 23 24 25 26 27 28 29 30 31 +5V R2 10K VREF +5V NC NC 2 1 13 R4 C21 OPT GND GND GND 12 C13 10uF,25V 1206 SCK MSPAN 10 D1 BAT54C R1 10K 0603 1206 18 19 7 3 AMP V+ V- 21 11 - 17 VDD 48 REFADJ 1 RINS 2 RINF 47 RCOM 46 REFF 45 REFS 43 ROFSF 44 ROFSS 42 RFBS 41 RFBF V+ E3 + 2 VCC C8 0.1uF 33 34 35 36 20 VinD 3 E2 4 9 VCC Q'H 7 QH 6 C2 QG 5 0.1uF QF 4 QE 3 8 GND QD 2 QC 1 QB 15 14 SER QA U2 LT1012ACS8 6 C7 0.1uF 5 16 2. INSTALL SHUNTS ON JUMPERS AS SHOWN. E1 VOUT VOUT 3 2 1 2 EXT GND C1 0.1uF 5 U9 74VHC595MTC VCC D_/S READ UPD WR_ CLR_ 1. ALL RESISTORS ARE IN OHMS, 0402. ALL CAPACITORS ARE IN MICROFARADS, 0402. 7 JP4 1 2 NOTES: UNLESS OTHERWISE SPECIFIED E4 2 22 32 5 DWG NO. REV DC1485A-2 * LTC2757CLX Wednesday, July 29, 2009 SHEET 1 1 2 OF 1 A