6 5 4 3 2 1 REVISION RECORD LTR ECO NO: APPROVED: DATE: Power Supplies D D +5V ADP7104ACPZ-5.0 +7V ADP7102ACPZ R63 8 +12V_FMC VIN VOUT R7 1 8 +5V +12V_FMC 0r U10 C34 4.7 µF PG_C2M 5 N/C 4 U18 PG 5 PG_C2M 7 C36 4.7 µF GND EP GND 3 9 6 VOUT 1 +7V 0r C69 4.7 µF SENSE 2 EN/UVLO VIN N/C 4 57.6K R18 ADJ 2 EN/UVLO PG 7 C70 4.7 µF GND EP GND 3 9 6 12.1K R19 100K R62 C C VIN = +12V , VOUT= +5V, IOUT = upto 500 mA VIN = +12V , VOUT= +7V, IOUT = upto 300 mA C37 + 4.7 µF -2P5V U2 ADP2300AUJZ B + 0.1uF SW R12 -2.5V 2 + VIN C38 4.7 µF 4 D3 1 6 4.7 µH +5V C66 1 L2 IND 2 1 5 BST 0r PD3S130L 1A, 30V + B 10 µF C71 R11 EN FB 3 35.7K GND 2 R6 16.9K VIN = +5V , VOUT= -2.5V, IOUT = 250 mA COMPANY: A Analog Devices A TITLE: DRAWN: AD7960 Eval Board DATED: Maithil P. CHECKED: MAY 12 DATED: <Checked By> QUALITY CONTROL: <QC By> RELEASED: <Released By> <Checked Date> DATED: <QC Date> CODE: SIZE: DRAWING NO: REV: <Code> A2 EVAL-AD7960FMCZ A1 DATED: <Release Date>SCALE: <Scale> SHEET: 1OF 6 6 5 4 3 2 1 REVISION RECORD LTR ECO NO: APPROVED: DATE: Power Supplies D D LK4 A +5V B C16 10 µF AMP_PWR+ JP8 AMP_PWR+ 1 2 C30 1uF AMP_PWR+_EXT VIO_1PT8V U3 3 +7V 8 IN OUT 1 7 IN OUT 2 5 EN OUTSEN 3 6 NC 4 GND LK2 EP R20 VIO 0r C14 1uF 9 ADP124ACPZ-1.8 +5V C C C19 10 µF J3-1 Screw Terminals J3-2 1PT8V U12 J3-3 AMP_PWR-_EXT LK3 8 IN OUT 1 7 IN OUT 2 C64 5 EN OUTSEN 3 4.7 µF 6 NC 4 GND 2 C29 10 µF EP R4 1.8V 0r C63 4.7 µF 9 ADP124ACPZ-1.8 AMP_PWRJP9 AMP_PWR- 3 1 LK5 A -2.5V B C18 10 µF The ADP124 is available in 2mmx2mm LFCSP packages. B B OPAMP POWR SUPPLY OPTIONS COMPANY: A Analog Devices A TITLE: DRAWN: AD7960 Eval Board DATED: Maithil P. CHECKED: MAY 12 DATED: <Checked By> QUALITY CONTROL: <QC By> RELEASED: <Released By> <Checked Date> DATED: <QC Date> CODE: SIZE: DRAWING NO: REV: <Code> A2 EVAL-AD7960FMCZ A1 DATED: <Release Date>SCALE: <Scale> SHEET: 2OF 6 6 5 4 3 2 1 REVISION RECORD LTR ECO NO: APPROVED: DATE: External Reference D D VCM_EXTERNAL C4 AMP_PWR+ 5V_REF U5 ADR4550BRZ 2 +7V +VIN VOUT 10 µF 0.1uF C27 0.1uF 0r 6 3 R16 C6 0r R21 10 µF C20 GND 4 C21 2.2µF C22 JP5 C42 TBD DNI 1 0.1uF 2 U4 A R22 3 LK7 R23 DNI U8 ADR4540BRZ +VIN VOUT 2 0r V- R14 REF 0.1uF REF C VCM_OUT 4 U11 R15 6 0r VCM 3 0r C44 10 µF C43 GND 4 C23 2.2µF 0.1uF 7 AD8031ARZ + V+ C24 TBD DNI OP 2 R24 4PT096V_REF C11 0r LK6 6 R17 VCM VCM 0r V- 4 R36 1M 10 µF C26 TBD DNI R25 A 2 DNI 6 C40 B R39 OP C25 AMP_PWR+ VCM_OUT REF AD8031ARZ V+ 0r B C 7 + TBD DNI R45 DNP U13 ADR4520BRZ 2_048V R30 +VIN VOUT 6 2 2 +5V 0r C60 C35 0.1uF 10 µF 0.1uF C62 10 µF REFIN JP7 B C61 1 3 GND 4 B 0r R26 GND2 There are 3 options for using an External Reference 1) Externally buffered reference source of 5V applied to the REF pin. 2) Externally buffered reference source of 4.096V applied to the REF pin. 3) External reference of 2.048V applied to the REFIN pin (high impedance input). The on-chip buffer gains this by 2 and drives the REF pin with 4.096V. COMPANY: A Analog Devices A TITLE: DRAWN: AD7960 Eval Board DATED: Maithil P. CHECKED: MAY 12 DATED: <Checked By> QUALITY CONTROL: <QC By> RELEASED: <Released By> <Checked Date> DATED: <QC Date> CODE: SIZE: DRAWING NO: REV: <Code> A2 EVAL-AD7960FMCZ A1 DATED: <Release Date>SCALE: <Scale> SHEET: 3OF 6 6 5 4 3 2 1 REVISION RECORD LTR ECO NO: APPROVED: DATE: AMP_PWR+ Analog Front End C58 D D ADA4899-1 U15 tba 3 OP_AMP+ 0r VCM J6-1 8 D R57 R48 820r 2 100pF C76 J6-2 J6-4 - V- VOUT V5 4 6 R35 0r R10 0r R41 AMP_PWR+ J6-5 7 V+ FB 1 R28 0r J6-3 + C59 VCM 1K AMP_PWRDNP R38 C54 0.1uF C55 DNP AMP_PWR- J6-6 AMP_PWR+ C56 ADA4899-1 U16 2 820r 100pF C77 V- VOUT V5 4 C 6 R60 0r R27 JP1 AIN+ FB 1 3 J2 7 V+ 1 0r R29 0r 33r C57 R37 2 VCM AMP_PWR- DIFF_IN+ C47 1K 3 C53 DNP DNP R40 JP2 C52 0.1uF JP4 3 OP_AMP- 1 IN- R53 1 33r J4 C48 AMP_PWR+ 2 2 J1 AIN- IN+ R52 1 2 J5 C49 3 0r OP_AMP+ + JP3 3 OP_AMP- C 8 D R58 R59 C41 0.1uF R56 0r 2 R49 0r 5 VS+ 6 OUT- 12 11 U14 ADA4932-1 499r R51 /PD IN+ 3 IN- OUT+ FB+ VCM 10 499r R43 9 VCM VS- C46 13 16 DNP 4 499r VS- DNP C50 14 R54 VS- DIFF_IN+ R44 15 GND3 R50 B 499r VS- DIFF_IN- FB- VS+ C51 DNP 1 VS+ DNP R42 VS+ 8 B 7 DIFF_IN- R55 DNP AMP_PWR- C45 0.1uF COMPANY: A Analog Devices A TITLE: DRAWN: AD7960 Eval Board DATED: Maithil P. CHECKED: MAY 12 DATED: <Checked By> QUALITY CONTROL: <QC By> RELEASED: <Released By> <Checked Date> DATED: <QC Date> CODE: SIZE: DRAWING NO: REV: <Code> A2 EVAL-AD7960FMCZ A1 DATED: <Release Date>SCALE: <Scale> SHEET: 4OF 6 6 5 4 3 2 1 REVISION RECORD LTR ECO NO: APPROVED: DATE: AD7960 D D C1 and C10 should be placed between REF and REF_GND and be placed very close to the DUT REF C1 C10 0.1uF U1 1.8V 1 2 3 4 5 6 7 8 +5V 1.8V C15 EN0 C8 0.1uF 0.1uF 10 µF C9 0.1uF EN1 EN2 EN3 R31 0r R32 0r R33 0r 0r R34 0.1uF GND IN+ INVCM VDD1 VDD1 VDD2 CLK+ 24 23 22 21 20 19 18 17 IN+ IN- VCM_OUT C +5V +5V 1.8V CLK+ CNV+ DD+ VIO GND DCODCO+ CLK- C7 33 PADDLE C17 C3 C12 0.1uF TP2 0.1uF C2 0.1uF 9 10 11 12 13 14 15 16 C REFIN VDD1 VDD2 REFIN EN0 EN1 EN2 EN3 CNV- REF REF REF REF REF_GND REF_GND REF_GND VDD2 32 31 30 29 28 27 26 25 10 µF CNV- TP4 R1 100R TP3 R2 100R TP1 CLK- CNV+ D- C5 TP6 TP5 EN0-EN3 are 1.8V Logic. TP8 TP7 D+ B DCODCO+ VIO B All the decoupling cap must be placed very close to the DUT COMPANY: A Analog Devices A TITLE: DRAWN: AD7960 Eval Board DATED: Maithil P. CHECKED: MAY 12 DATED: <Checked By> QUALITY CONTROL: <QC By> RELEASED: <Released By> <Checked Date> DATED: <QC Date> CODE: SIZE: DRAWING NO: REV: <Code> A2 EVAL-AD7960FMCZ A1 DATED: <Release Date>SCALE: <Scale> SHEET: 5OF 6 6 5 4 3 2 1 REVISION RECORD LTR ECO NO: APPROVED: DATE: FMC-LPC Male Connector D 3P3VAUX R9 C C186 U7 8 VCC GA1 GA0 1 E0 2 E1 3 E2 6 7 SDA 5 FPGA I2C Lines GA0 SCL +12V WP +12V_FMC VSS 4 M24C02-WMN6TP J7-A ASP-134604-01 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 AK20 AK21 AJ24 AK25 AD21 AE21 AD27 AD28 AJ28 AJ29 PG_C2M GND DP0_C2M_P DP0_C2M_N GND GND DP0_M2C_P DP0_M2C_N GND GND LA06_P LA06_N GND GND LA10_P LA10_N GND GND LA14_P LA14_N GND GND LA18_P_CC LA18_N_CC GND GND LA27_P LA27_N GND GND SCL SDA GND GND GA0 12P0V GND 12P0V GND 3P3V GND CNV+ CNV- 3P3VAUX GA1 J7-B ASP-134604-01 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 AE23 AF23 AG22 AH22 AK23 AK24 AB24 AC25 AB27 AC27 AH26 AH27 AK29 AK30 PG_C2M GND GND GBTCLK0_M2C_P GBTCLK0_M2C_N GND GND LA01_P_CC LA01_N_CC GND LA05_P LA05_N GND LA09_P LA09_N GND LA13_P LA13_N GND LA17_P_CC LA17_N_CC GND LA23_P LA23_N GND LA26_P LA26_N GND TCK TDI TDO 3P3VAUX TMS TRST_L GA1 3P3V GND 3P3V GND 3P3V D CLK+ CLKEN0_FMC EN1_FMC VADJ VADJ J7-C ASP-134604-01 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 AD23 AE24 AG20 AH20 AJ22 AJ23 AA20 AB20 AC22 AD22 AF26 AF27 AJ27 AK28 AC26 AD26 AE28 AF28 AD29 AE29 AC29 AC30 GND CLK1_M2C_P CLK1_M2C_N GND GND LA00_P_CC LA00_N_CC GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ GND DCO+ DCOD+ DEN2_FMC EN3_FMC VADJ J7-D ASP-134604-01 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 AF22 AG23 AF20 AF21 AH21 AJ21 AG25 AH25 AE25 AF25 AC24 AD24 AJ26 AK26 AG27 AG28 AG30 AH30 AE30 AF30 AB29 AB30 Y30 AA30 VREF_A_M2C PRSNT_M2C_L GND CLK0_M2C_P CLK0_M2C_N GND LA02_P LA02_N GND LA04_P LA04_N GND LA07_P LA07_N GND LA11_P LA11_N GND LA15_P LA15_N GND LA19_P LA19_N GND LA21_P LA21_N GND LA24_P LA24_N GND LA28_P LA28_N GND LA30_P LA30_N GND LA32_P LA32_N GND VADJ Board present pin C R101 560r +12V_FMC EEPROM required in VITA standard I2C line pull-up resistors on FPGA board GREEN 1.8V VADJ B 1 16 VCCA VCCB 2 R64 10k U17 PG_C2M 2 NC7S04 EN3 3 EN2 4 EN1 5 EN0 6 7 4 B C28 0.1uF 0.1uF C31 9 T/R0 T/R1 A0 B0 A1 B1 A2 A3 T/R3 OE GND 8 B2 B3 T/R2 EP 17 U9 15 14 EN3_FMC 13 EN2_FMC 12 EN1_FMC 11 EN0_FMC 10 FXL4TD245BQX COMPANY: A Analog Devices A TITLE: DRAWN: AD7960 Eval Board DATED: Maithil P. CHECKED: MAY 12 DATED: <Checked By> QUALITY CONTROL: <QC By> RELEASED: <Released By> <Checked Date> DATED: <QC Date> CODE: SIZE: DRAWING NO: REV: <Code> A2 EVAL-AD7960FMCZ A1 DATED: <Release Date>SCALE: <Scale> SHEET: 6 OF 6