Application Note 1665 FMC ADC Evaluation Board User’s Guide High-Speed ADC Evaluation Platform • Interfaces Intersil’s High-Speed ADC Evaluation PCB Family to FMC Based Evaluation Platforms • 40MSPS to 500MSPS Operation • SPI Access for ADC Configuration • Compatible with all Intersil High-Speed ADC Daughter Cards Evaluation Platform Overview Intersil’s FMC based high-speed ADC evaluation platform consists of custom designed hardware, which allows interfacing to an FMC based FPGA evaluation platform. This allows for direct FPGA processing of the ADC output data and system prototyping for a user. SPI access to the ADC is possible at the FMC connector or optionally at a separate header on the PCB (JP3). Hardware There are two components in the hardware portion of the evaluation platform: the daughter card and the motherboard (Figure 1). The ADC is contained on the daughter card, which routes power from the motherboard and contains the analog input circuitry, clock drive and decoupling. The daughter card interfaces to the motherboard through a mezzanine connector. The motherboard provides power to the ADCs analog and digital supply pins from separate LDOs from Intersil’s High performance linear regulator family. The ADCs digital outputs are routed through the mezzanine connector to the FMC connector at the motherboard card edge. The user must supply low-jitter RF generators for the clock and analog inputs. Recommendations of suitable generators can be found in “Appendix A: RF Generators” on page 2. Many low-jitter RF generators exhibit high harmonic spectral content relative to the ADC performance. A band-pass filter is recommended to attenuate the harmonics. A wideband attenuator in series with the band-pass filter is also recommended for daughter cards without on-board attenuators. Current spikes from the ADCs switched capacitor sample-and-hold amplifier can create signal reflections in the coaxial cable. The attenuator reduces these reflections and improves performance. Software There is no software provided with the evaluation system. Data capture and ADC performance verification needs to be done at the receiving FPGA. A reset of the ADC is possible at switch S1 on the PCB. FIGURE 1. EVALUATION PLATFORM BLOCK DIAGRAM September 30, 2011 AN1665.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright Intersil Americas Inc. 2011. All Rights Reserved. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Daughter Cards Each daughter card is designed to produce optimal ADC performance and simplify the evaluation process. Some boards have multiple connections for the analog input and clock. For example, low-frequency and high-frequency input paths are provided on certain boards. A high-frequency input path may have a balun interface, while a low frequency path may use a transformer or buffer amplifier (for DC-coupling). Motherboard MOSI GND 1 CSB JP3 MISO Referring to Figure 1, connect the daughter card to the motherboard by aligning the two mating mezzanine connectors. Four screws on the motherboard (not shown) align with mounting holes in the daughter card. The FMC connector should be aligned and connected with an appropriate mating FMC-based FPGA evaluation system. Next, connect the RF generators to the Clock and Analog input SMA connectors. Set the clock frequency as desired with the power level at +10dBm. Similarly, set the analog input frequency with a power level of approximately +7dBm (the full-scale value will vary depending on the loss of the input path and gain of the ADC). With the RF generators on, apply +5V power supply to the motherboard. The daughter card is powered by Intersil linear regulators on the motherboard. GND Initial Start-Up SCLK Application Note 1665 FIGURE 3. JP3 PINOUT SPI Programming Access to the ADC SPI port is available at both the FMC connector and header JP3. The ADCs typically support both 3-wire and 4-wire SPI communication and the default mode at power-up is 3-wire mode (consult the appropriate ADC data sheet for more information). It is recommended to use 4-wire SPI communication with the FMC based ADC motherboard, requiring that the ADC first be placed in 4-wire SPI mode by writing to the appropriate ADC register (consult data sheet). A resistor on the daughter card (R4) at the CPLD will need to be removed. Logic levels for the SPI port on card is 3.3V LVCMOS (level translation to 1.8V is done on the ADC daughter cards). Appendix A: RF Generators Intersil uses the following RF generators as clock and signal sources when characterizing high-speed ADCs: • Rohde & Schwarz: SMA100A The only connection required for the motherboard is +5V power at J1 (5V wall supply is supplied), JP1 is an optional connection. The data outputs are LVDS and will require 100Ω differential termination resistors at the receiver/FPGA. . • Agilent: 8644B (with Low-Noise option) These generators provide very low jitter to optimize the SNR performance of the ADC under test. Other generators with similar phase noise performance can also be used. Contact Intersil Technical Support for recommendations. Appendix B: Daughter Cards The FMC ADC Evaluation Board (KAD-FMC-EVALZ) connects data, clock, and SPI control signals to/from an ADC to an external FPGA through an LPC FMC connector and a 180 pin Molex connector. The Molex connector interfaces with any of the KAD5XXX and ISLAXXX ADC daughtercards. The schematic for the respective Intersil ADC daughtercard can be downloaded from our website for additional information and bit-ordering. Note that the MSB bit-ordering is different for the ISLA2XXX and KAD5XXX,ISL1XXP50 families. Additional information on Intersil ADC Daughter Cards can be found at the respective ADC product pages on our website. FIGURE 2. PCB TOP VIEW 2 AN1665.0 September 30, 2011 Application Note 1665 TABLE 1. LPC FMC CONNECTOR PINOUT H G D C 1 NC GND NC GND 2 NC NC GND NC 3 GND NC GND NC 4 NC GND NC GND 5 NC GND NC GND 6 GND CLKOUTP (FMC LA00_P_CC) GND NC 7 DIG_OUT14 (FMC LA02_P) CLKOUTN (FMC LA00_N_CC) GND NC 8 DIG_OUT14N (FMC LA02_N) GND DIG_OUT15 (FMC LA01_P) GND 9 GND DIG_OUT13 (FMC LA03_P) DIG_OUT15N (FMC LA01_N) GND 10 DIG_OUT12 (FMC LA04_P) DIG_OUT13N (FMC LA03_N) GND DIG_OUT10 (FMC LA06_P) 11 DIG_OUT12N (FMC LA04_N) GND DIG_OUT11 (FMC LA05_P) DIG_OUT10N (FMC LA06_N) 12 GND DIG_OUT9 (FMC LA08_P) DIG_OUT11N (FMC LA05_N) GND 13 DIG_OUT8 (FMC LA07_P) DIG_OUT9N (FMC LA08_N) GND GND 14 DIG_OUT8N (FMC LA07_N) GND DIG_OUT7 (FMC LA09_P) DIG_OUT6 (FMC LA10_P) 15 GND DIG_OUT5 (FMC LA12_P) DIG_OUT7N (FMC LA09_N) DIG_OUT6N (FMC LA10_N) 16 DIG_OUT4 (FMC LA11_P) DIG_OUT5N (FMC LA12_N) GND GND 17 DIG_OUT4N (FMC LA11_N) GND DIG_OUT3 (FMC LA13_P) GND 18 GND DIG_OUT1 (FMC LA16_P) DIG_OUT3N (FMC LA13_N) DIG_OUT2 (FMC LA14_P) 19 DIG_OUT0 (FMC LA15_P) DIG_OUT1N (FMC LA16_N) GND DIG_OUT2N (FMC LA14_N) 20 DIG_OUT0N (FMC LA15_N) GND NC GND 21 GND NC NC GND 22 NC NC GND NC 23 NC GND NC NC 24 GND NC NC GND 25 SCLK (LA21_P) NC GND GND 26 CSB (LA21_N GND NC NC 27 GND NC NC NC 28 MISO (LA24_P) NC GND GND 3 AN1665.0 September 30, 2011 Application Note 1665 TABLE 1. LPC FMC CONNECTOR PINOUT (Continued) H G D C 29 MOSI (LA24_N) GND NC GND 30 GND NC NC NC 31 NC NC NC NC 32 NC GND NC GND 33 GND NC NC GND 34 NC NC NC NC 35 NC GND NC NC 36 GND NC NC GND 37 PC2 (LA32_P) NC GND NC 38 NC GND NC GND 39 GND NC GND NC 40 NC GND NC GND 4 AN1665.0 September 30, 2011 Application Note 1665 TABLE 2. FMC PIN OUT DAUGHTER CARD CROSS REFERENCE FMC PCB 180 PIN DATA CONNECTOR ISLA2XXX DAUGHTER CARD(72pin QFN) KAD5XXX DAUGHTER CARD (72 pin QFN) (Note) (Note) PIN NUMBER PIN NAME PIN NAME PIN NAME 14 dig_out15 lvds_0 ORP 16 dig_outn15 lvds_n0 ORN 20 dig_out14 lvds_1 D13P (MSB) 22 dig_outn14 lvds_n1 D13N (MSB) 26 dig_out13 lvds_2 D12P 28 dig_outn13 lvds_n2 D12N 32 dig_out12 lvds_3 D11P 34 dig_outn12 lvds_n3 D11N 38 dig_out11 lvds_4 D10P 40 dig_outn11 lvds_n4 D10N 44 dig_out10 lvds_5 D9P 46 dig_outn10 lvds_n5 D9N 50 dig_out9 lvds_6 D8P 52 dig_outn9 lvds_n6 D8N 62 dig_out8 lvds_7 D7P 64 dig_outn8 lvds_n7 D7N 68 dig_out7 lvds_8 D6P 70 dig_outn7 lvds_n8 D6N 74 dig_out6 lvds_9 D5P 76 dig_outn6 lvds_n9 D5N 80 dig_out5 lvds_10 D4P 82 dig_outn5 lvds_n10 D4N 86 dig_out4 lvds_11 D3P 88 dig_outn4 lvds_n11 D3N 92 dig_out3 lvds_12 D2P 94 dig_outn3 lvds_n12 D2N 98 dig_out2 lvds_13 D1P 100 dig_outn2 lvds_n13 D1N 104 dig_out1 lvds_14 D0P 106 dig_outn1 lvds_n14 D0N 110 dig_out0 lvds_15 (MSB) NC 112 dig_outn0 lvds_n15 (MSB) NC 56 clk_out clk_out clkoutp 58 clk_outn clk_outn clkoutn 124 sclk_3v sclk_3v sclk_3v 126 csb_3v csb_3v csb_3v 128 miso_3v miso_3v miso_3v 5 AN1665.0 September 30, 2011 Application Note 1665 TABLE 2. FMC PIN OUT DAUGHTER CARD CROSS REFERENCE (Continued) FMC PCB 180 PIN DATA CONNECTOR ISLA2XXX DAUGHTER CARD(72pin QFN) KAD5XXX DAUGHTER CARD (72 pin QFN) (Note) (Note) PIN NUMBER PIN NAME PIN NAME PIN NAME 130 mosi_3v mosi_3v mosi_3v 140 PORn_ExtResetn_fpga PORn_ExtResetn_fpga PORn_ExtResetn_fpga NOTE: The 72 pin QFN ADC eval boards are MSB justified; J6 pins 110/112 are the MSB for 16,14,and 12-bit devices: ISLA2XXX while J6 pins 20/22 are the MSB for 14, 12, 10 and 8-bit devices: KAD5XXX, and ISL1XXP50 Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 6 AN1665.0 September 30, 2011 Schematics vdd2_anlg_sense LDO U1 R4 R5 DNP optional 500 ohm pot 33uF 0 R7 2.6K R3 1K 1.8V ISL28006 DNP C2 .1uF R1pot DNP 5 D1 GND RS_N C5 33nF R36 464 Ohms CHIP SUPPLY vdd2_anlg C3 33uF 1 C4 DNP LDO C31 33nF R8 DNP 4 R6 1K R9 OUT C28 33uF TP2 0 Ohms anlg_1.8V C6 VCC RS_P R35 2.6K C9 10uF 1 2 3 4 5 VOUT VOUT SENS_ADJ PG GND 2 VCC ISL80101-ADJ VIN VIN NC ENABLE SS 3 C32 DNP EPAD R25 1K 1 2 3 4 5 VOUT VOUT SENS_ADJ PG GND 11 C29 10uF VIN VIN NC ENABLE SS 10 9 8 7 6 vdd3_anlg EPAD 10 9 8 7 6 Dig_5V U2 3.3V Norminal ISL80101-ADJ 11 U7 Anlg_5V TP9 7 28006 placed for internal use only EPAD D2 LDO 33nF C14 R12 R17 2.6K U8 C26 10uF R23 1K TP10 DNP C23 R20 1K ISL80101-ADJ VIN VIN NC ENABLE SS 1 2 3 4 5 VOUT VOUT SENS_ADJ PG GND EPAD 10 9 8 7 6 Anlg_5V ISL28006 DNP vdd2_lvds_sense R22pot DNP 28006 placed for internal use only GND RS_N 0 vdd3_anlg_sense 0 5 4 R13 R14 2.6K C16 33uF R11 464 Ohms 1 R21 DNP U3 OUT D3 R10 VCC RS_P EPAD R19 DNP LDO optional 500 ohm pot vdd3_anlg 3.3V R18 DNP vdd2_lvds C7 33uF 2 C11 33nF 1 2 3 4 5 3 C12 DNP VOUT VOUT SENS_ADJ PG GND 1 2 3 4 5 VOUT VOUT SENS_ADJ PG GND TP4 0 Ohms ISL80101-ADJ VIN VIN NC ENABLE SS 11 R15 1K C13 DNP ISL80101-ADJ VIN VIN NC ENABLE SS anlg_3.3V R33 2.6K C27 33uF LDO 33nF C25 Dig_5V R34 464 Ohms C10 .1uF MMZ2012R102A L1 MMZ2012R102A MMZ2012R102A L6 MMZ2012R102A BLM41PG102SN1L L5 Dig_5V C15 330uF 4 EGND R2 249 3 EGND L12 MMZ2012R102A DS1 MMZ2012R102A L7 J1 Removed C109 , C113, C44 MMZ2012R102A BLM41PG102SN1L L14 Anlg_5V C33 330uF 1 3 TP3 TP5 TP8 TP6 TP7 C18 .1uF C24 .1uF Anlg_5V U24 pin2 U3 pin2 Dig_5V MMZ2012R102A Anlg_5V MMZ2012R102A L10 U12 pin2 L8 TP1 board supply D4 L13 MMZ2012R102A T1 DLW5BSN351SQ2 1 2 5V_external 1 2 L11 MMZ2012R102A L2 F1 FUSE2 EDZ350/2 JP1 L9 1 L4 MMZ2012R102A 2 L3 2 PJ-102AH C1 33uF INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGREEMENT EGND EGND Title C30 .1uF MBlite Size B FIGURE 4. Date: File: Number Revision B 1-Aug-2011 Sheet of C:\Documents and Settings\GHENDRIC\MyDrawn Documents\MBlite\RevB\MBliteRevB By: Application Note 1665 U4 C8 10uF C19 LDO 33nF C21 10 9 8 7 6 VCC R16 1K 11 C22 DNP C17 10uF vdd2_sense 33uF EPAD R24 1K 10 9 8 7 6 Anlg_5V Board_1.8V 11 C20 10uF U5 ISL80101IR18Z (1.8V) 1 VOUT 2 VOUT 3 SENS_ADJ 4 PG 5 GND VIN VIN NC ENABLE SS 11 U6 10 9 8 7 6 VCC AN1665.0 September 30, 2011 Schematics (Continued) vdd2_lvds_sense vdd2_lvds J2 8 FPGA_spare_2 DGND GND vdd2_anlg_sense vdd2_anlg anlg_1.8V vdd3_anlg_sense AN1665.0 September 30, 2011 vdd3_anlg anlg_3.3V Anlg_5V 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 Dig_5V VCC Sxx1 DGND J3 dig_out15 dig_outn15 dig_out14 dig_outn14 dig_out13 dig_outn13 clk_out dig_out12 dig_outn12 H1 GND D1 GND H2 G2 GND C2 GND G3 GND C3 H4 GND D4 GND H5 GND D5 GND GND G6 GND C6 H7 G7 GND C7 H8 GND D8 GND GND G9 D9 GND H10 G10 GND C10 H11 GND D11 C11 clk_outn dig_out11 dig_outn11 dig_out14 dig_outn14 dig_out10 dig_outn10 dig_out15 dig_outn15 dig_out13 dig_outn13 dig_out9 dig_outn9 dig_out10 dig_out12 dig_outn10 dig_outn12 clk_out clk_outn dig_out11 dig_out9 GND G12 D12 GND H13 G13 GND GND dig_out8 dig_outn8 dig_out7 dig_outn7 H14 GND D14 C14 GND G15 D15 C15 H16 G16 GND GND H17 GND D17 GND GND G18 D18 C18 dig_out7 dig_outn7 dig_out6 dig_out5 dig_outn6 dig_outn5 dig_out6 dig_outn6 dig_out4 dig_outn4 dig_out5 dig_outn5 dig_out1 dig_out4 dig_outn4 dig_out0 VCC dig_out2 dig_outn2 R29 1K R27 1K dig_outn0 VCC R28 1K SC2 dig_out0 dig_outn0 SD2 dig_out3 dig_outn3 dig_out2 dig_outn2 dig_outn1 dig_out3 dig_outn3 dig_out1 dig_outn1 dig_outn11 dig_outn9 dig_out8 dig_outn8 Application Note 1665 52760-1879 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 H19 G19 GND C19 H20 GND D20 GND GND G21 D21 GND H22 G22 GND C22 H23 GND D23 C23 GND G24 D24 GND H25 G25 GND GND H26 GND D26 C26 GND G27 D27 C27 3 2 1 Board_1.8V JP2 CON3 PC0 = NC PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 SD0 SC0 SD2 PC1=WP=NC PC2 = SPI_Master_Drive PC3=CPLD_spare1=NC PC4=SCLK_3V PC5=CSB_3V PC6=MISO_3V PC7=MOSI_3V NC NC SD2 SC2 SC2 PORn/ExtResetn PD2 NC PD4 NC PD5 NC PD7 NC FPGA_spare_1 NC DGND GND VCC PC5=CSB_3V PC5 PC6=MISO_3V PC6 H28 G28 GND GND PC7=MOSI_3V PC7 H29 GND D29 GND GND G30 D30 C30 H31 G31 D31 C31 H32 GND D32 GND GND G33 D33 GND H34 G34 D34 C34 H35 GND D35 C35 GND G36 D36 GND H37 G37 GND C37 H38 GND D38 GND GND G39 GND C39 H40 GND D40 GND 1 3 5 7 9 PC6 PC4 PC5 2 4 6 8 10 PC7 HEADER 5X2 R31 1K R30 R32 1K 1K VCC FMC_PC2 DGND PC4 JP3 PC2 TP11 PC4=SCLK_3V R26 1K FMC_PC2 I Title S1 SW-PBX PORn/ExtResetn ASP-127797-01 Size B Date: File: FIGURE 5.