Schematic PDF

8
6
7
2
3
4
5
REV
DESCRIPTION
D
AVDD_P5V
R117
10K
AVDD_P5V
R118
10K
C114
0.1UF
AGND
AGND
C101
C109
0.1UF
AMPAIN+
R103
0
T100
-(NC)
3
4
2
SEC
PRI
C
AMPAIN2 3 4 5
1
J101
1
C102
200
0.1UF
R116
TBD0402
AGND
C110
R107
25
0.1UF
R102
0
R114
AVDD_P5V
200
0.1UF
ON
OFF
AGND
1
2
3
P100
AGND
AGND
SMA-J-P-X-ST-EM1
ADT1-1WT
T101
3
6
0.1UF
XFMRAIN+
J100
1
R101
R100
51
0
2 3 4 5
C100
0.1UF
ETC1-1-13
5
SEC
AGND
PRI
3
-(NC)
ETC1-1-13
T102
0.1UF
C105
2
4
4
PRI
2
5
R104
R110
0
33
R105
R111
0
33
0.1UF
-(NC)
3
SEC
T103
1
C106
AGND
AGND
0.1UF
SMA-J-P-X-ST-EM1
AGND
VIN-A
C111
1
AGND
AMP+A
C107
VIN+A
R108
33
R109
33
4
1
5 (NC)
C104
R115
0
AMP-A
4.7PF
C103
2
B
1
2
3
4
5
6
16
AGND
5
AGND
R106
25
ETC1-1-13
R113
0.1UF
C108
0.1UF
AGND
R112
0
CML
VIP
IIP
IIN
VIN
VCIO
VCI
PD_N
OUT_POS
OUT_NEG
AGND
AGND
U100
VS_POS1
VS_POS2
VS_POS3
VS_POS4
VOCM
7
8
9
12
13
C113
0.1UF
14 VS_NEG1
15 VS_NEG2
PAD PAD
1
TP100
C112
0.1UF
R119
0
CML
C115
0.1UF
AGND
C116
0.1UF
R120
39
11
10
AGND
C117
0.1UF
ADA4960_PRELIM
R121
39
1
L100
10NH
R122
100
R123
100
1
L101
10NH
8
6
7
2
3
4
5
REV
CLOCK CIRCUITRY
DEFAULT CLOCK PATH
OPT_CLK_P
CLK_P_LO
D
0
0
0.1UF
2 3 4 5
AGND
3
AGND
PRI
0.1UF
C201
3
1
SEC
4
AGND
CLOSE TO DUT
1
2
CR200
HSMS-2812BLK
3
ETC1-1-13
ADT1-1WT
CLOSE TO DUT
C205
R208
R203
0
0
0.1UF
2 3 4 5
5
C202
CLK_P
0.1UF
T200
6
2
CLK_N
0.1UF
R210
0
R204
0
R201
51
CLK-
T201
4
1
5 (NC)
AGND
J201
SMA-J-P-X-ST-EM1
1
C204
R207
R202
R200
51
CLK+
C200
R212
100
0201
J200
SMA-J-P-X-ST-EM1
1
C206
0.1UF
R209
0
C207
0.1UF
CLOSE TO DUT
AGND
CLK_N_LO
OPT_CLK_N
AGND
C
KILOPASS VOLTAGE
ADG734BRUZ
1
1
2
3
U200
PWDN
AVDD_3P3V
R213
0
3
R214
0
R211
PWDN_DUT
0
ADG734BRUZ
PWDN
10
AGND
SA
SB
9
7
U200
IN
D
8
RESET
8P5V AGND
C203
0.1UF
AVDD_3P3V
R215
0
RESET_DUT
KP_V_CTRL
R206
10K
ADG734BRUZ
11
U200
SA 12
SB 14
IN
D
16
U200
VDD
AGND
15 NC15
6 GND
5 VSS
B
D
R205
1K
P200
OFF
2
4
IN
AVDD_DUT
ON
SA
SB
ADG734BRUZ
13
AGND
AGND
ADG734BRUZ
20
SA
SB
U200
19
17
IN
D
18
NOTE: ADG734 SYMBOL IS SHOWN WITH INPUT = LOGIC 1
C208
0.1UF
DESCRIPTION
8
6
7
2
3
4
5
REV
WALWART POWER SUPPLY INPUT
6VDC, 2A MAX
CR305
A
C
S2A-TP
S2A-TP
PWR2
DECOUPLING CAPS
E300
E302
AGND
GND1 PAD
AGND
Z5.530.3225.0
AGND
0.1UF
0.1UF
50OHMS
8P5V
C318
DRVDD_DUT
2
C319
1
1
2
1 JP302 2
P5V_AVDD
BERG69157-102
AGND
E303
P302
4.7UF
R300
10K
4.7UF
R301
1.91K
PWR0
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
AGND
10UF
50OHMS
AGND
U303
ADP1708ARDZ-R7
1
EN
7
SENSE
3
5
IN
OUT
4
6
IN2
OUT2
8 ADJ
AVDD_DUT
2
10UF
1 JP301 2
1P8V_DRVDD
BERG69157-102
1
C314
P301
1P8V_AVDD
1
2
1P8V_DRVDD
3
4
Z5.531.3425.0
C315
2 PAD
0.1UF
C328
DRVDD_DUT
AGND
4.7UF
GND1 PAD
C310
4.7UF
C306
C302
PWR2
0.01UF
B
C326
0.1UF
AGND
AGND
U302
ADP1706ARDZ-1.8-R7
1
EN
7
SENSE
3
5
IN
OUT
4
6
IN2
OUT2
8 SS
C327
0.1UF
C317
10UF
C313
50OHMS
1 JP303 2
1P8V_AVDD
BERG69157-102
C323
2 PAD
AVDD_P5V
AVDD_DUT
2
4.7UF
GND1 PAD
C309
0.01UF
4.7UF
C305
C301
PWR2
E301
1
C325
AGND
C322
50OHMS
AGND
U301
ADP1706ARDZ-1.8-R7
1
EN
7
SENSE
3
5
IN
OUT
4
6
IN2
OUT2
8 SS
0.1UF
AVDD_3P3V
2
0.1UF
1
10UF
P300
3P3V_AVDD
4
3
P5V_AVDD
2
1
Z5.531.3425.0
C321
OPTIONAL POWER CONNECTIONS
C316
AGND
AVDD_DUT
C312
2 PAD
1 JP300 2
3P3V_AVDD
BERG69157-102
4.7UF
GND1 PAD
C308
4.7UF
C304
C
C300
PWR1
0.01UF
U300
ADP1706ARDZ-3.3-R7
1
EN
7
SENSE
3
5
IN
OUT
4
6
IN2
OUT2
8 SS
0.1UF
C331
C332
AGND
AGND
C333
0.1UF
0.1UF
C329
C330
AVDD_DUT
0.1UF
AGND
S2A-TP
CR304
A
C
0.1UF
BNX016-01
S2A-TP
CR303
A
C PWR1
PWR0
C324
3
4
6
5
CR301
A
C
0.1UF
2
C320
1
LNJ314G8TRA (GREEN)
CR302
R302
C
A
249
RAPC722X
S2A-TP
1 2
FL300
CR300
A
C
SH1
1 F300 2
2A
10UF
D
SIG
SH2
C307
J300
3
DESCRIPTION
8
6
7
2
3
4
5
REV
SPI
COPIED FROM 9644EE01A SHEET 6
D
NOTE: ADG734 SYMBOL IS DRAWN WITH INPUT = LOGIC 1
AVDD_3P3V
P400
1
2
3
SPI_VDD
AVDD_DUT
R404
1.1K
1 A1
Y1
6
3 A2
Y2
4
R407
1.1K
U402
NC7WZ07P6X
0
AGND
1
TP400
R415
0
CSB_USB
3 A2
R401
10K
SCLK_USB
VCC
6
Y2
4
GND
NC7WZ16P6X2
AGND
AGND
AGND
FPGA_CSB
TP401
11
IN
ADG734BRUZ
20
1
13 D U400
U401
Y1
R408
100K
5
1 A1
AGND
R406
100K
R402
10K
C401
0.1UF
R411
10K
AGND
12 SA
14 SB
SPI_VDD
FAST_SPI_EN
IN
ADG734BRUZ
SDIO_USB
DUT_CSB
FPGA_SCLK
R409
R412
0
0
R410
R413
0
0
1
DUT_SCLK
TP403
ADG734BRUZ
10
TP402
SA
SB
9
7
D
8
IN
U400
R414
AGND
B
1
DUT_SDIO
SDO_USB
2
AGND
1
FPGA_SDIO
GND
R403
100K
R400
10K
SDI_USB
5
VCC
2 SA
4 SB
R405
1.1K
18 D U400
C
AVDD_3P3V
AGND
19 SA
17 SB
C400
0.1UF
IN
SPI_VDD
SPI_VDD
3 DU400
ADG734BRUZ
FAST_SPI_EN
DESCRIPTION
8
6
7
2
3
4
5
REV
RESET_DUT
10K
AGND
28 RESET /DNC
31 RBIAS /VREF
40 CML
CML
CLK_P
CLK_N
44 CLK_P
45 CLK_N
C501
0.1UF
AGND
DUT_SCLK
R502
1K
DUT_SDIO
DUT_CSB
PWDN_DUT
R503
26 SCLK_DFS
27 CSB
29 PWDN
25 SDIO_DCS
1K
AGND
PAD
B
AGND
AVDD_DUT
C500
U500
ADR130AUJZ
3 VIN
VOUT 4
5 SET
GND
2
50
49
AD9230BCPZ-170
AD9434
AD6641
1
R504
0
C502
DCO_P
DCO_N
DRGND
8
23
48
FUNCTION
HI=ENABLED
LOW=DISABLED
52
51
54
53
56
55
2
1
4
3
6
5
10
9
12
11
14
13
16
15
18
17
20
19
TP500
VREFOUT
5RN501
12
47
R520
100
6RN501
11
47
RN501
3
14
47
R521
100
4RN501
13
47
RN500
7
10
47
R522
100
8RN5009
47
5RN500
12
47
R523
100
6RN500
11
47
RN500
3
14
47
R524
100
4RN500
13
D4B
D5
D5B
D6
D6B
D7
DCOB
FILLD1B
D3B
D5B
D7B
D9B
D11B
D8B
D9
6469169-1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
D0B
D2B
D4B
D6B
D8B
D10B
DORB
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
6469169-1
D1 P501
D2
D3
D4
D5
D6
D7
D8
D9
D10
6469169-1
PLUG HEADER
AD9517_CSB
CSB_USB
6469169-1
P502
KP_V_CTRL
FAST_SPI_EN
SDO_USB
SDI_USB
SCLK_USB
6469169-1
P501
FPGA_SCLK
FPGA_CSB
FPGA_SDIO
D0
D2
D4
D6
D8
D10
DOR
D7B
D8
P502
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
P501
D3B
D4
PLUG HEADER
D3
D1
D3
D5
D7
D9
D11
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
P501
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
AGND
AGND
6469169-1
P502
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
6469169-1
D1 P502
D2
D3
D4
D5
D6
D7
D8
D9
D10
6469169-1
DG1 P501
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
P502
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
AGND
6469169-1
6469169-1
6469169-1
DG1 P502
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
AGND
D9B
D10
AD6641: USE FILL+/AD9434: USE DCO+/AD9230: USE DCO+/-
D10B
D11
D11B
R508
FILL-
PLUG HEADER
R500
D0_P
D0_N
D1_P
D1_N
D2_P
D2_N
D3_P
D3_N
D4_P
D4_N
D5_P
D5_N
D6_P
D6_N
D7_P
D7_N
D8_P
D8_N
D9_P
D9_N
D10_P
D10_N
D11_P
D11_N
D2B
DCO
FILL+
PLUG HEADER
VREFOUT
35 VIN_P
36 VIN_N
D2
PLUG HEADER
VIN+A
VIN-A
U501
22
21
P501
D1B
PLUG HEADER
AGND
DRVDD
OR_P
OR_N
D1
PLUG HEADER
AVDD
D0B
PLUG HEADER
RESET
HIGH SPEED
CONNECTION
TO FPGA (FIFO5)
PLUG HEADER
OFF
DRVDD_DUT
47
24
7
1
2
3
ON
SPI RESET
AVDD_DUT
46
43
42
41
39
38
37
34
33
32
30
C
R501
1K
P500
D0
PLUG HEADER
AVDD_DUT
DORB
PLUG HEADER
DUT CIRCUITRY
DOR
PLUG HEADER
D
1 RN500
16
47
R512
100
2RN500
15
47
5RN503
12
47
R513
100
6RN503
11
47
RN503
3
14
47
R514
100
4RN503
13
47
RN503
1
16
47
R515
100
2RN503
15
47
5RN502
12
47
R516
100
6RN502
11
47
RN502
3
14
47
R517
100
4RN502
13
47
RN502
1
16
47
R518
100
2RN502
15
47
7RN501
10
47
R519
100
8RN5019
47
DESCRIPTION
6469169-1
8
6
7
2
3
4
5
REV
OPTIONAL CLOCK PATH CIRCUIT
P601
1
2
3
D
AVDD_3P3V
0.1UF
OPT_CLK_N
P600
C
REF_SEL
BYPASS_LDO
9
LF
8
C607
OPT_CLK_P
R602
1.00K
R604
1.00K
C606 0.1UF
OPT_CLK_N
0.1UF
CP
BYPASS
STATUS
LF
OUT0
OUT0_N
OUT1
OUT1_N
OUT2
OUT2_N
OUT3
OUT3_N
OUT4_OUT4A
OUT4_N_OUT4B
OUT5_OUT5A
OUT5_N_OUT5B
OUT6_OUT6A
OUT6_N_OUT6B
OUT7_OUT7A
OUT7_N_OUT7B
11
CLK
12
CLK_N
18
PD_N
7
SYNC_N
17
RESET_N
AVDD_3P3V
TSW-104-08-T-D
AGND
R607
1.00K
R606
AD9517_CSB
SCLK_USB
SDI_USB
13
SCLK
16
SDIO
14
CS_N
0
VCP
RSET
REFMON
CPRSET
LD
REFIN_N_REF2
AVDD_3P3V
R601
1.00K
VS
48
REFIN_REF1
47
C601
0.1UF
1
2
3
4
5
6
7
8
VS_LVPECL
6
C600
OPT_CLK_P
21
40
R609
1.00K
10
24
25
30
31
36
37
43
45
3
AVDD_3P3V
PAD
PAD
AGND
SDO
U600
R614
44
1
46
5.11K
2
4
4.12K AGND
R613
CP
5
249
42
41
39
38
19
20
22
23
35
34
33
32
26
27
28
29
15
AGND
CR600
R611
A
C
SML-LXT0805IW-TR
AGND
CLK_P_LO
CLK_N_LO
C609
SDO_USB
AD9517-4BCPZ
R615
249
R616
249
AGND
AGND
TP600
K24A
1
0.1UF
R612
100
C610
1
TP601
K24A
0.1UF
B
CP
DECOUPLING
R608
0
J600
R605
100
1
R600
0
CHARGE PUMP FILTER
AVDD_3P3V
R610
C603
0.1UF
C608
1500PF
R603
200
C604
C602
JOHNSON142-0701-201
AGND
.033UF
1800PF
0
AGND
.22UF
BYPASS_LDO
C605
2 3 4 5
LF
AGND
C611
C616
0.1UF
C612
0.1UF
C617
0.1UF
C613
0.1UF
C618
0.1UF
C614
0.1UF
C619
0.1UF
C615
0.1UF
C620
0.1UF
0.1UF
DESCRIPTION