8 6 7 2 3 4 5 1 REVISIONS REV POWER SUPPLY INPUT J101 3 1 2 1.6A C101 10UF APPROVED DATE AD9286CE01A 07/28/10 C.H. VIN CR102 A C CR101 SH1 SIG SH2 S2A-TP RAPC722X F101 A S2A-TP FL101 DESCRIPTION A LTST-C190GKT C CR103 BNX016-01 PGND GND D D R101 300 GND J103 1 2 3 VARIABLE POWER SUPPLY INPUT E109 1 C125 10UF GND ADP2108AUJZ-3.3-R7 VIN L101 GND C104 1UF R102 100K 3 GND SW EN FB 5 4 C105 10UF C 3.3V_AMPVDD 39OHM C108 10UF C106 10UF GND GND 3.3V_AMPVDD_REG 2 2 3.3V_AMPVDD_REG 1 100NH 2.2UH VIN 1 GND GND C107 1UF 39OHM GND J105 1 2 3 GND C103 10UF E110 2 E102 GND 2 3.3V_CLK_REG 1 C109 1UF J102 3.3V GND DVDD (1.8V) GND AVDD (1.8V) 39OHM GND C E111 1 1 2 3 4 5 6 GND DRVDD_REG DRVDD_BENCH 2 C127 10UF 39OHM GND C128 0.1UF DRVDD ALIAS SPI_DVDD R104 0 GND J106 1 2 3 C102 10UF L102 3.3V_CLK 39OHM GND E101 U101 1 C126 0.1UF J104 1 2 3 SUPPLY REGULATORS 3.3V_CLK_REG 2 Z5.530.3625.0 E112 GND 1 AVDD_REG AVDD_BENCH 2 ADP2108AUJZ-1.8-R7 C115 10UF GND C116 10UF GND C117 1UF GND VIN 3 SW EN L104 2.2UH 100NH FB 5 4 C110 10UF GND GND C129 10UF 2 AVDD_REG 1 U102 1 R103 100K L103 39OHM E105 GND C113 10UF C111 10UF GND GND C112 1UF C130 0.1UF AVDD REF_AVDD ALIAS R105 0 GND 39OHM GND 2 E107 GND 1 C114 1UF B 2 DRVDD_REG 39OHM B GND TP102 BLK TP101 BLK GND POWER SUPPLY A AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, A SCHEMATIC 9284 CUSTOMER EVALUATION BOARD AD9284 DESIGN VIEW REV DRAWING NO. - A 9284CE01A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 JON HARRIS 2 SCALE NONE SHEET 1 1 OF 7 8 6 7 2 3 4 5 1 REVISIONS REV AVDD PIN 1 AVDD DESCRIPTION DATE APPROVED AVDD C201 .1UF C202 .1UF DNI D D GND J201 DRVDD PIN 20 DRVDD AVDD PIN 4 AVDD DRVDD C219 .1UF C204 .1UF C220 .1UF 1-2 SCLK MODE 1 2-3 LVDS MODE 2 NO CONNECT CMOS MODE (DEFAULT) 3 SAMTECTSW10608GS3PIN DNI DNI GND GND DNI GND AVDD PINS 16 AVDD C214 .1UF AVDD AVDD ENC_A+ ENC_ACSB_DUT SDIO_DUT_PWRDN SCLK_DUT_CMOS_LVDS REF_AVDD C224 0.1UF GND R201 2.7K U202 1 V_P 3 TRIM ADR512ARTZ-REEL7 R202 0 R206 0 0 2 REF IN GND DRVDD GND R204 5K D6A(D7A-/D7B-) AD9284 D1A/(D4A+/D4B+) 65/135/250 MSPS DCOA/(DCO+) D0A/(D4A-/D4B-) AVDD DCOB/(DCO-) AVDD D7B/(D3A+/D3B+) AIN B+ D6B/(D3A-/D3B-) AIN BD5B/(D2A+/D2B+) AVDD D4B/(D2A-/D2B-) D5A_D6P D4A_D6M D3A_D5P D2A_D5M D1A_D4P D0A_D4M DCO_A DCO_B D7B_D3P D6B_D3M D5B_D2P D4B_D2M D3B_D1P D2B_D1M D1B_D0P D0B_D0M DRVDD B J204 CONNECT CLKB ENABLED 1 DEFAULT LOW (DISABLED) 2 TSW-102-08-G-S 3 2 RBIAS C225 0.1UF GND 10K GND R205 10K AVDD PINS 45 AVDD C215 .1UF AVDD U201 SG-MLF-7006 R203 V_N D2A/(D5A-/D5B-) CMV OUT 24 23 22 21 20 19 18 17 16 15 14 13 D3B/(D1A+/D1B+) C212 .1UF C223 0.1UF GND D3A/(D5A+/D5B+) AVDD D2B/(D1A-/D1B-) C211 .1UF REF IN CKT AIN_B+ AIN_BAVDD GND D4A/(D6A-/D6B-) D1B/(D0A+/D0B+) AVDD PINS 13 AVDD GND AVDD D7A_D7P D6A_D7M AIN A+ D0B/(D0A-/D0B-) GND C227 0.1UF C D5A/(D6A+/D6B+) AIN A- DRVDD DNI AVDD C226 0.1UF AVDD DRGND C210 .1UF CMV_OUT 37 38 39 40 41 42 43 44 45 46 47 48 PAD CLOCK B ENABLE C209 .1UF GND GND DRVDD AVDD PINS 12 AVDD AVDD AIN_AAIN_A+ AVDD RBIAS GND ENC B- DNI ENC B+ C208 .1UF GND AVDD C207 .1UF DNI 36 35 AVDD 34 ENC A+ 33 ENC A32 SPI_CSB 31 SPI_SDIO/PWRDN 30 SPI_SCLK/CMOS_LVDS 29 OUTPUT_ENABLE 28 DRGND 27 DRVDD 26 D7A(D7A+/D7B+) 25 AVDD PINS 8 & 9 AVDD DEFAULT HIGH (EN) 1 CONNECT OUTPUT DISABLED 2 TSW-102-08-G-S AVDD GND J203 AVDD DNI C222 .1UF 1 2 3 4 5 6 7 8 9 10 11 12 C206 .1UF C221 .1UF 1-2 SDIO MODE 1 2-3 PWRDN MODE 2 NO CONNECT (DEFAULT) 3 SAMTECTSW10608GS3PIN CW B C205 .1UF SDIO_DUT SDIO_DUT_PWRDN DRVDD DRVDD PIN 39 DRVDD SHARE PADS C DURING LAYOUT CHECK IF WE CAN FIT 0402 ELSE 0201 AVDD PIN 6 AVDD 1 DECOUPLING CAPACITORS, ONE ON THE TOP AND ONE ON THE BOTTOM CLOSE TO THE PINS J202 AVDD AVDD ENC_B+ ENC_B- C203 .1UF SCLK_DUT SCLK_DUT_CMOS_LVDS DRVDD TP201 1 BLK GND C216 .1UF DNI GND AVDD PINS 48 AVDD DUT C218 .1UF A A GND AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC 9284 CUSTOMER EVALUATION BOARD AD9284 DESIGN VIEW REV DRAWING NO. - A 9284CE01A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 JON HARRIS 2 SCALE NONE SHEET 1 2 OF 7 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED D D SPI CIRCUITRY SPI_DVDD C301 0.1UF R302 1.1K 3.3V_CLK GND C C R303 1.1K SDIO_DUT U301 NC7WZ07P6X VCC R305 1.1K 6 1 A1 Y1 3 A2 Y2 4 USB_SDO GND 100K R304 10K R301 USB_SDI 5 2 GND GND SPI_DVDD 5 GND 100K U302 R308 R310 0 C302 0.1UF 10K R306 GND VCC USB_CSB 1 A1 Y1 6 USB_SCLK 3 A2 Y2 4 CSB_DUT SCLK_DUT B NC7WZ16P6X R309 10K R307 GND 2 100K SDIO_DUT_1P8 B GND GND GND R311 0 R312 0 CSB_DUT_1P8 SCLK_DUT_1P8 SPI A AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC 9284 CUSTOMER EVALUATION BOARD AD9284 DESIGN VIEW REV DRAWING NO. - A 9284CE01A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 A JON HARRIS 2 SCALE NONE SHEET 1 3 OF 7 8 6 7 2 3 4 5 1 REVISIONS REV PASSIVE PATH A DESCRIPTION DATE APPROVED AMP_OUT_ADNI J402 AIN_A - R404 1 DNI 0 R402 49.9 2 3 4 5 DNI C402 ETC1-1-13 R411 33 C404 DNI DNI 0.1UF R405 0 DNI GND DNI TBD0402 0.1UF R448 0 0.1UF 0 D AIN_A- DNI 3 0 2.7PF 4 33 R410 33 C405 R449 CMV_OUT R416 C407 SEC R414 4.7PF 1 4 ADT1-1WT+ PRI R412 C406 2 1 DNI GND 5 0 0.1UF ETC1-1-13 GND T403 T402 3 3 T401 6 DNI 4 R401 49.9 2 3 4 5 C403 0.1UF SEC 0 PRI AIN_A + 1 D R403 1 R406 0 SHARE PADS R407 C401 5 J401 GND R408 R413 R415 R417 0 33 0 0 AIN_A+ DNI SHARE PADS R409 0 GND GND GND AMP_OUT_A+ LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER C C ACTIVE PATH A AND B R440 200 R442 CMV_OUT 9 2 3 12 PAD R439 1 1 11 10 4 0 THESE 0 OHMS ARE THERE FOR ALIASES. WE DON'T REQUIRE THESE COMPONENTS GND -VS ADA4937-1YCPZ-R7 R437 27.4 R446 DNI R441 R447 200 0 GND AMP_OUT_B- 0 24 DNI DNI GND FB-OUT -OUT +OUT FB+OUT AMP_OUT_A+ DNI R443 GND 200 2 3 4 5 VOCM +IN -IN PD_N PAD 16 15 14 13 0.1UF J406 DNI +VS C416 GND 24 5 6 7 8 U401 DNI 0 R450 GND DNI 10UF 0.1UF DNI GND GND DNI R436 61.9 2 3 4 5 DNI R445 0.1UF 200 AMP_OUT_A- 0 C418 AIN_AMP C417 R438 C419 J405 1 R444 3.3V_AMPVDD AMP_OUT_B+ DNI B B PASSIVE PATH B AMP_OUT_B+ DNI 3 ETC1-1-13 A J404 R421 1 AIN_B + 0 2 3 4 5 R419 49.9 GND DNI 0 0.1UF R429 33 C412 DNI R451 C410 0.1UF 0.1UF GND R425 R430 R432 R434 0 33 0 0 DNI SHARE PADS DNI 4 CMV_OUT AIN_B+ R435 SEC 0 TBD0402 1 4 ADT1-1WT+ PRI 0 DNI 2 1 R428 33 C413 33 2.7PF GND 5 0.1UF R433 C415 GND T406 DNI 6 R431 4.7PF T405 T404 3 ETC1-1-13 R422 0 DNI GND 0 R427 C414 DNI 3 DNI 4 R418 49.9 2 3 4 5 C411 0.1UF SEC 0 PRI AIN_B - R423 0 SHARE PADS R424 C409 1 DNI R420 5 J403 1 ANALOG INPUT AIN_B- R426 0 AN A LO G DE V CES GND GND AMP_OUT_BTHIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, A SCHEMATIC 9284 CUSTOMER EVALUATION BOARD AD9284 DESIGN VIEW REV DRAWING NO. - A 9284CE01A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 JON HARRIS 2 SCALE NONE SHEET 1 4 OF 7 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED XFMR / BALUN CLK CIRCUITRY DNI C501 R503 0 DNI R501 49.9 SHARE PADS? DNI C503 0.1UF DNI DNI GND GND C505 C502 R504 1 CLK_A + 0 0.1UF 2 3 4 5 R502 49.9 1 GND 0.1UF 4 0 0 ADT1-1WT+ DNI C507 1 4 0.1UF R506 24.9 0.1UF 2 3 R508 C508 R510 0 ENC_A+ 0 T502 0.1UF 2ND CR IS TO MAKE LAYOUT AND PARASITIC LOADING SYMMETRICAL GND PRI OPTIONAL TERMINATION NEAR DUT HMPS-2822-BLK GND TP501 BLK LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER ENC_A- CR501 C506 2 J502 R509 R505 24.9 6 T501 3 R507 D R511 0 DNI DNI 2 3 4 5 100 0.1UF R512 D CLK_A - XSTAL_INSHARE PADS 1 SHARE PADS J501 SEC R513 0 DNI XSTAL_IN+ -(NC)- C504 MABA-007159-000000 1000PF GND C C OPTIONAL CRYSTAL OSCIALLATOR CLOCK SOURCE C517 3.3V_CLK 0.1UF GND R526 130 Y505 6 R527 130 VDD 1 TRISTATE 2 NC 4 5 XSTAL_IN+ XSTAL_IN- GND R525 1K GND Q Q_N 3 R528 75 500MEGHZ GND R529 75 GND OPTIONAL CLOCK B INPUT 2 3 4 5 0 0.1UF R515 49.9 TP502 BLK DNI ADT1-1WT+ 1 4 GND DNI 2 DNI J503 C509 R516 1 CLK_B 2 3 4 5 B R517 0.1UF R514 49.9 0 SHARE PADS? DNI C513 0 1 4 C514 GND 6 T503 DNI 0 C515 ENC_B- 0.1UF CR503 0.1UF R519 24.9 C511 0.1UF DNI R522 R518 24.9 0.1UF 3 R520 MABA-007159-000000 2 3 DNI CLK_B + C510 1 100 J504 R524 B OPTIONAL TERMINATION NEAR DUT HMPS-2822-BLK GND R521 R523 0 0 C516 ENC_B+ 0.1UF 2ND CR IS TO MAKE LAYOUT AND PARASITIC LOADING SYMMETRICAL GND GND 6 C512 1000PF A 1 PRI SEC 4 5 3 2 -(NC)- CLOCK T504 A GND AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC 9284 CUSTOMER EVALUATION BOARD AD9284 DESIGN VIEW REV DRAWING NO. - A 9284CE01A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 JON HARRIS 2 SCALE NONE SHEET 1 5 OF 7 8 7 6 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED 0 OHM RESISTOR NETWORK FOR LVDS MODE D D 47 OHM RESISTOR NETWORK FOR CMOS MODE 0 AND 47 0 AND 47 D7A_D7P 1 RN601 16 D7B_D3P 1 O_D7A D6A_D7M D6B_D3M 2 O_D6A D5A_D6P RN601 14 D5B_D2P 3 O_D5A RN601 13 CHANNEL B CHANNEL A C 4 O_D4A 0 D3A_D5P RN601 5 12 O_D6B RN602 14 O_D5B 0 0 D4A_D6M RN602 15 0 0 3 O_D7B 0 0 RN601 2 15 RN602 16 D4B_D2M 4 RN602 13 O_D4B 0 D3B_D1P 5 O_D3A RN602 12 C O_D3B 0 0 D2A_D5M RN601 6 11 D2B_D1M 6 O_D2A RN602 11 O_D2B 0 0 D1A_D4P 7 RN601 10 D1B_D0P 7 O_D1A RN602 10 O_D1B 0 0 D0A_D4M RN601 8 9 D0B_D0M O_D0A 8 RN602 9 O_D0B 0 0 B B DCO DCO_A R601 O_DCO_A 0 DCO_B R602 O_DCO_B 0 OUTPUT NETWORK A AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, A SCHEMATIC 9284 CUSTOMER EVALUATION BOARD AD9284 DESIGN VIEW REV DRAWING NO. - A 9284CE01A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 JON HARRIS 2 SCALE NONE SHEET 1 6 OF 7 8 7 6 5 2 3 4 1 REVISIONS REV DESCRIPTION DATE APPROVED D D 6469169-1 B GND 6469169-1 PLUG HEADER PLUG HEADER C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 CSB_DUT_1P8 O_D0B O_D4B O_D0A O_D4A P1 6469169-1 P1 P2 BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 BG10 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 GND GND 6469169-1 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 PLUG HEADER P1 6469169-1 USB_SDO USB_SDI USB_SCLK C 6469169-1 PLUG HEADER BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 BG10 PLUG HEADER P2 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 6469169-1 6469169-1 P2 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 P1 6469169-1 P1 PLUG HEADER O_D1B O_D5B O_D1A O_D5A C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 USB_CSB O_D2B O_D6B O_D2A O_D6A 6469169-1 PLUG HEADER SDIO_DUT_1P8 SCLK_DUT_1P8 PLUG HEADER P2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 O_DCO_B PLUG HEADER 6469169-1 C B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 PLUG HEADER O_D3B O_D7B O_D3A O_D7A P1 P2 PLUG HEADER A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 O_DCO_A PLUG HEADER P2 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 6469169-1 B GND FIFO5 CONNECTIONS A AN A LO G DE V CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, A SCHEMATIC 9284 CUSTOMER EVALUATION BOARD AD9284 DESIGN VIEW REV DRAWING NO. - A 9284CE01A OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER D THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 JON HARRIS 2 SCALE NONE SHEET 1 7 OF 7